drivers/pinctrl/sh-pfc/sh_pfc.h

   1 /*
   2  * SuperH Pin Function Controller Support
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #ifndef __SH_PFC_H
  12 #define __SH_PFC_H
  13
  14 #include <linux/bug.h>
  15 #include <linux/pinctrl/pinconf-generic.h>
  16 #include <linux/stringify.h>
  17
  18 enum {
  19         PINMUX_TYPE_NONE,
  20         PINMUX_TYPE_FUNCTION,
  21         PINMUX_TYPE_GPIO,
  22         PINMUX_TYPE_OUTPUT,
  23         PINMUX_TYPE_INPUT,
  24 };
  25
  26 #define SH_PFC_PIN_CFG_INPUT            (1 << 0)
  27 #define SH_PFC_PIN_CFG_OUTPUT           (1 << 1)
  28 #define SH_PFC_PIN_CFG_PULL_UP          (1 << 2)
  29 #define SH_PFC_PIN_CFG_PULL_DOWN        (1 << 3)
  30 #define SH_PFC_PIN_CFG_IO_VOLTAGE       (1 << 4)
  31 #define SH_PFC_PIN_CFG_NO_GPIO          (1 << 31)
  32
  33 struct sh_pfc_pin {
  34         u16 pin;
  35         u16 enum_id;
  36         const char *name;
  37         unsigned int configs;
  38 };
  39
  40 #define SH_PFC_PIN_GROUP(n)                             \
  41         {                                               \
  42                 .name = #n,                             \
  43                 .pins = n##_pins,                       \
  44                 .mux = n##_mux,                         \
  45                 .nr_pins = ARRAY_SIZE(n##_pins),        \
  46         }
  47
  48 struct sh_pfc_pin_group {
  49         const char *name;
  50         const unsigned int *pins;
  51         const unsigned int *mux;
  52         unsigned int nr_pins;
  53 };
  54
  55 /*
  56  * Using union vin_data saves memory occupied by the VIN data pins.
  57  * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups
  58  * in this case.
  59  */
  60 #define VIN_DATA_PIN_GROUP(n, s)                                \
  61         {                                                       \
  62                 .name = #n#s,                                   \
  63                 .pins = n##_pins.data##s,                       \
  64                 .mux = n##_mux.data##s,                         \
  65                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
  66         }
  67
  68 union vin_data {
  69         unsigned int data24[24];
  70         unsigned int data20[20];
  71         unsigned int data16[16];
  72         unsigned int data12[12];
  73         unsigned int data10[10];
  74         unsigned int data8[8];
  75         unsigned int data4[4];
  76 };
  77
  78 #define SH_PFC_FUNCTION(n)                              \
  79         {                                               \
  80                 .name = #n,                             \
  81                 .groups = n##_groups,                   \
  82                 .nr_groups = ARRAY_SIZE(n##_groups),    \
  83         }
  84
  85 struct sh_pfc_function {
  86         const char *name;
  87         const char * const *groups;
  88         unsigned int nr_groups;
  89 };
  90
  91 struct pinmux_func {
  92         u16 enum_id;
  93         const char *name;
  94 };
  95
  96 struct pinmux_cfg_reg {
  97         u32 reg;
  98         u8 reg_width, field_width;
  99         const u16 *enum_ids;
 100         const u8 *var_field_width;
 101 };
 102
 103 /*
 104  * Describe a config register consisting of several fields of the same width
 105  *   - name: Register name (unused, for documentation purposes only)
 106  *   - r: Physical register address
 107  *   - r_width: Width of the register (in bits)
 108  *   - f_width: Width of the fixed-width register fields (in bits)
 109  * This macro must be followed by initialization data: For each register field
 110  * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
 111  * one for each possible combination of the register field bit values.
 112  */
 113 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
 114         .reg = r, .reg_width = r_width, .field_width = f_width,         \
 115         .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 116
 117 /*
 118  * Describe a config register consisting of several fields of different widths
 119  *   - name: Register name (unused, for documentation purposes only)
 120  *   - r: Physical register address
 121  *   - r_width: Width of the register (in bits)
 122  *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
 123  *                          From left to right (i.e. MSB to LSB)
 124  * This macro must be followed by initialization data: For each register field
 125  * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
 126  * one for each possible combination of the register field bit values.
 127  */
 128 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
 129         .reg = r, .reg_width = r_width, \
 130         .var_field_width = (const u8 [r_width]) \
 131                 { var_fw0, var_fwn, 0 }, \
 132         .enum_ids = (const u16 [])
 133
 134 struct pinmux_data_reg {
 135         u32 reg;
 136         u8 reg_width;
 137         const u16 *enum_ids;
 138 };
 139
 140 /*
 141  * Describe a data register
 142  *   - name: Register name (unused, for documentation purposes only)
 143  *   - r: Physical register address
 144  *   - r_width: Width of the register (in bits)
 145  * This macro must be followed by initialization data: For each register bit
 146  * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
 147  */
 148 #define PINMUX_DATA_REG(name, r, r_width) \
 149         .reg = r, .reg_width = r_width, \
 150         .enum_ids = (const u16 [r_width]) \
 151
 152 struct pinmux_irq {
 153         const short *gpios;
 154 };
 155
 156 /*
 157  * Describe the mapping from GPIOs to a single IRQ
 158  *   - ids...: List of GPIOs that are mapped to the same IRQ
 159  */
 160 #define PINMUX_IRQ(ids...)                         \
 161         { .gpios = (const short []) { ids, -1 } }
 162
 163 struct pinmux_range {
 164         u16 begin;
 165         u16 end;
 166         u16 force;
 167 };
 168
 169 struct sh_pfc;
 170
 171 struct sh_pfc_soc_operations {
 172         int (*init)(struct sh_pfc *pfc);
 173         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 174         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 175                          unsigned int bias);
 176         int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
 177         int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
 178                               u16 voltage_mV);
 179 };
 180
 181 struct sh_pfc_soc_info {
 182         const char *name;
 183         const struct sh_pfc_soc_operations *ops;
 184
 185         struct pinmux_range input;
 186         struct pinmux_range output;
 187         struct pinmux_range function;
 188
 189         const struct sh_pfc_pin *pins;
 190         unsigned int nr_pins;
 191         const struct sh_pfc_pin_group *groups;
 192         unsigned int nr_groups;
 193         const struct sh_pfc_function *functions;
 194         unsigned int nr_functions;
 195
 196 #ifdef CONFIG_SUPERH
 197         const struct pinmux_func *func_gpios;
 198         unsigned int nr_func_gpios;
 199 #endif
 200
 201         const struct pinmux_cfg_reg *cfg_regs;
 202         const struct pinmux_data_reg *data_regs;
 203
 204         const u16 *pinmux_data;
 205         unsigned int pinmux_data_size;
 206
 207         const struct pinmux_irq *gpio_irq;
 208         unsigned int gpio_irq_size;
 209
 210         u32 unlock_reg;
 211 };
 212
 213 /* -----------------------------------------------------------------------------
 214  * Helper macros to create pin and port lists
 215  */
 216
 217 /*
 218  * sh_pfc_soc_info pinmux_data array macros
 219  */
 220
 221 /*
 222  * Describe generic pinmux data
 223  *   - data_or_mark: *_DATA or *_MARK enum ID
 224  *   - ids...: List of enum IDs to associate with data_or_mark
 225  */
 226 #define PINMUX_DATA(data_or_mark, ids...)       data_or_mark, ids, 0
 227
 228 /*
 229  * Describe a pinmux configuration without GPIO function that needs
 230  * configuration in a Peripheral Function Select Register (IPSR)
 231  *   - ipsr: IPSR field (unused, for documentation purposes only)
 232  *   - fn: Function name, referring to a field in the IPSR
 233  */
 234 #define PINMUX_IPSR_NOGP(ipsr, fn)                                      \
 235         PINMUX_DATA(fn##_MARK, FN_##fn)
 236
 237 /*
 238  * Describe a pinmux configuration with GPIO function that needs configuration
 239  * in both a Peripheral Function Select Register (IPSR) and in a
 240  * GPIO/Peripheral Function Select Register (GPSR)
 241  *   - ipsr: IPSR field
 242  *   - fn: Function name, also referring to the IPSR field
 243  */
 244 #define PINMUX_IPSR_GPSR(ipsr, fn)                                      \
 245         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
 246
 247 /*
 248  * Describe a pinmux configuration without GPIO function that needs
 249  * configuration in a Peripheral Function Select Register (IPSR), and where the
 250  * pinmux function has a representation in a Module Select Register (MOD_SEL).
 251  *   - ipsr: IPSR field (unused, for documentation purposes only)
 252  *   - fn: Function name, also referring to the IPSR field
 253  *   - msel: Module selector
 254  */
 255 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)                                \
 256         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
 257
 258 /*
 259  * Describe a pinmux configuration with GPIO function where the pinmux function
 260  * has no representation in a Peripheral Function Select Register (IPSR), but
 261  * instead solely depends on a group selection.
 262  *   - gpsr: GPSR field
 263  *   - fn: Function name, also referring to the GPSR field
 264  *   - gsel: Group selector
 265  */
 266 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                                \
 267         PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
 268
 269 /*
 270  * Describe a pinmux configuration with GPIO function that needs configuration
 271  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
 272  * Function Select Register (GPSR), and where the pinmux function has a
 273  * representation in a Module Select Register (MOD_SEL).
 274  *   - ipsr: IPSR field
 275  *   - fn: Function name, also referring to the IPSR field
 276  *   - msel: Module selector
 277  */
 278 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)                                \
 279         PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn)
 280
 281 /*
 282  * Describe a pinmux configuration for a single-function pin with GPIO
 283  * capability.
 284  *   - fn: Function name
 285  */
 286 #define PINMUX_SINGLE(fn)                                               \
 287         PINMUX_DATA(fn##_MARK, FN_##fn)
 288
 289 /*
 290  * GP port style (32 ports banks)
 291  */
 292
 293 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
 294 #define PORT_GP_1(bank, pin, fn, sfx)   PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
 295
 296 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)                                               \
 297         PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),   \
 298         PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 299 #define PORT_GP_4(bank, fn, sfx)        PORT_GP_CFG_4(bank, fn, sfx, 0)
 300
 301 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)                                               \
 302         PORT_GP_CFG_4(bank, fn, sfx, cfg),                                              \
 303         PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),   \
 304         PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
 305 #define PORT_GP_8(bank, fn, sfx)        PORT_GP_CFG_8(bank, fn, sfx, 0)
 306
 307 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)                                               \
 308         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 309         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
 310 #define PORT_GP_9(bank, fn, sfx)        PORT_GP_CFG_9(bank, fn, sfx, 0)
 311
 312 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)                                              \
 313         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 314         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg),   \
 315         PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 316 #define PORT_GP_12(bank, fn, sfx)       PORT_GP_CFG_12(bank, fn, sfx, 0)
 317
 318 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)                                              \
 319         PORT_GP_CFG_12(bank, fn, sfx, cfg),                                             \
 320         PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
 321 #define PORT_GP_14(bank, fn, sfx)       PORT_GP_CFG_14(bank, fn, sfx, 0)
 322
 323 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)                                              \
 324         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 325         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
 326 #define PORT_GP_15(bank, fn, sfx)       PORT_GP_CFG_15(bank, fn, sfx, 0)
 327
 328 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)                                              \
 329         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 330         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
 331 #define PORT_GP_16(bank, fn, sfx)       PORT_GP_CFG_16(bank, fn, sfx, 0)
 332
 333 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)                                              \
 334         PORT_GP_CFG_16(bank, fn, sfx, cfg),                                             \
 335         PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
 336 #define PORT_GP_18(bank, fn, sfx)       PORT_GP_CFG_18(bank, fn, sfx, 0)
 337
 338 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)                                              \
 339         PORT_GP_CFG_18(bank, fn, sfx, cfg),                                             \
 340         PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),   \
 341         PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),   \
 342         PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg),   \
 343         PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
 344 #define PORT_GP_26(bank, fn, sfx)       PORT_GP_CFG_26(bank, fn, sfx, 0)
 345
 346 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)                                              \
 347         PORT_GP_CFG_26(bank, fn, sfx, cfg),                                             \
 348         PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
 349 #define PORT_GP_28(bank, fn, sfx)       PORT_GP_CFG_28(bank, fn, sfx, 0)
 350
 351 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)                                              \
 352         PORT_GP_CFG_28(bank, fn, sfx, cfg),                                             \
 353         PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
 354 #define PORT_GP_30(bank, fn, sfx)       PORT_GP_CFG_30(bank, fn, sfx, 0)
 355
 356 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)                                              \
 357         PORT_GP_CFG_30(bank, fn, sfx, cfg),                                             \
 358         PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
 359 #define PORT_GP_32(bank, fn, sfx)       PORT_GP_CFG_32(bank, fn, sfx, 0)
 360
 361 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
 362         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
 363         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
 364         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
 365         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
 366         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
 367         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
 368         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
 369         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
 370         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
 371         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
 372         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
 373         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
 374         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
 375         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
 376         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
 377         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
 378
 379 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
 380 #define _GP_ALL(bank, pin, name, sfx, cfg)      name##_##sfx
 381 #define GP_ALL(str)                     CPU_ALL_PORT(_GP_ALL, str)
 382
 383 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
 384 #define _GP_GPIO(bank, _pin, _name, sfx, cfg)                           \
 385         {                                                               \
 386                 .pin = (bank * 32) + _pin,                              \
 387                 .name = __stringify(_name),                             \
 388                 .enum_id = _name##_DATA,                                \
 389                 .configs = cfg,                                         \
 390         }
 391 #define PINMUX_GPIO_GP_ALL()            CPU_ALL_PORT(_GP_GPIO, unused)
 392
 393 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 394 #define _GP_DATA(bank, pin, name, sfx, cfg)     PINMUX_DATA(name##_DATA, name##_FN)
 395 #define PINMUX_DATA_GP_ALL()            CPU_ALL_PORT(_GP_DATA, unused)
 396
 397 /*
 398  * PORT style (linear pin space)
 399  */
 400
 401 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
 402
 403 #define PORT_10(pn, fn, pfx, sfx)                                         \
 404         PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),     \
 405         PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),     \
 406         PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),     \
 407         PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),     \
 408         PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
 409
 410 #define PORT_90(pn, fn, pfx, sfx)                                         \
 411         PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
 412         PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
 413         PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
 414         PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
 415         PORT_10(pn+90, fn, pfx##9, sfx)
 416
 417 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
 418 #define _PORT_ALL(pn, pfx, sfx)         pfx##_##sfx
 419 #define PORT_ALL(str)                   CPU_ALL_PORT(_PORT_ALL, PORT, str)
 420
 421 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
 422 #define PINMUX_GPIO(_pin)                                               \
 423         [GPIO_##_pin] = {                                               \
 424                 .pin = (u16)-1,                                         \
 425                 .name = __stringify(GPIO_##_pin),                       \
 426                 .enum_id = _pin##_DATA,                                 \
 427         }
 428
 429 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
 430 #define SH_PFC_PIN_CFG(_pin, cfgs)                                      \
 431         {                                                               \
 432                 .pin = _pin,                                            \
 433                 .name = __stringify(PORT##_pin),                        \
 434                 .enum_id = PORT##_pin##_DATA,                           \
 435                 .configs = cfgs,                                        \
 436         }
 437
 438 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
 439 #define SH_PFC_PIN_NAMED(row, col, _name)                               \
 440         {                                                               \
 441                 .pin = PIN_NUMBER(row, col),                            \
 442                 .name = __stringify(PIN_##_name),                       \
 443                 .configs = SH_PFC_PIN_CFG_NO_GPIO,                      \
 444         }
 445
 446 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 447  *                   PORT_name_OUT, PORT_name_IN marks
 448  */
 449 #define _PORT_DATA(pn, pfx, sfx)                                        \
 450         PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,                  \
 451                     PORT##pfx##_OUT, PORT##pfx##_IN)
 452 #define PINMUX_DATA_ALL()               CPU_ALL_PORT(_PORT_DATA, , unused)
 453
 454 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
 455 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)                        \
 456         [gpio - (base)] = {                                             \
 457                 .name = __stringify(gpio),                              \
 458                 .enum_id = data_or_mark,                                \
 459         }
 460 #define GPIO_FN(str)                                                    \
 461         PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 462
 463 /*
 464  * PORTnCR helper macro for SH-Mobile/R-Mobile
 465  */
 466 #define PORTCR(nr, reg)                                                 \
 467         {                                                               \
 468                 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
 469                         /* PULMD[1:0], handled by .set_bias() */        \
 470                         0, 0, 0, 0,                                     \
 471                         /* IE and OE */                                 \
 472                         0, PORT##nr##_OUT, PORT##nr##_IN, 0,            \
 473                         /* SEC, not supported */                        \
 474                         0, 0,                                           \
 475                         /* PTMD[2:0] */                                 \
 476                         PORT##nr##_FN0, PORT##nr##_FN1,                 \
 477                         PORT##nr##_FN2, PORT##nr##_FN3,                 \
 478                         PORT##nr##_FN4, PORT##nr##_FN5,                 \
 479                         PORT##nr##_FN6, PORT##nr##_FN7                  \
 480                 }                                                       \
 481         }
 482
 483 /*
 484  * GPIO number helper macro for R-Car
 485  */
 486 #define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
 487
 488 #endif /* __SH_PFC_H */