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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_port.c
blob00ad2637b08c082f523e3a28c3e3472b91b82438
1 /*
2 * Base port operations for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * A note about mapbase / membase
13 *
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
16 */
17
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 /*
48 * Debugging.
49 */
50 #if 0
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #else
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
54 #endif
55
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
57
58 /*
59 * Here we define the default xmit fifo size used for each type of UART.
60 */
61 static const struct serial8250_config uart_config[] = {
62 [PORT_UNKNOWN] = {
63 .name = "unknown",
64 .fifo_size = 1,
65 .tx_loadsz = 1,
66 },
67 [PORT_8250] = {
68 .name = "8250",
69 .fifo_size = 1,
70 .tx_loadsz = 1,
71 },
72 [PORT_16450] = {
73 .name = "16450",
74 .fifo_size = 1,
75 .tx_loadsz = 1,
76 },
77 [PORT_16550] = {
78 .name = "16550",
79 .fifo_size = 1,
80 .tx_loadsz = 1,
81 },
82 [PORT_16550A] = {
83 .name = "16550A",
84 .fifo_size = 16,
85 .tx_loadsz = 16,
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
89 },
90 [PORT_CIRRUS] = {
91 .name = "Cirrus",
92 .fifo_size = 1,
93 .tx_loadsz = 1,
94 },
95 [PORT_16650] = {
96 .name = "ST16650",
97 .fifo_size = 1,
98 .tx_loadsz = 1,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
100 },
101 [PORT_16650V2] = {
102 .name = "ST16650V2",
103 .fifo_size = 32,
104 .tx_loadsz = 16,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 UART_FCR_T_TRIG_00,
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
109 },
110 [PORT_16750] = {
111 .name = "TI16750",
112 .fifo_size = 64,
113 .tx_loadsz = 64,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 UART_FCR7_64BYTE,
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
118 },
119 [PORT_STARTECH] = {
120 .name = "Startech",
121 .fifo_size = 1,
122 .tx_loadsz = 1,
123 },
124 [PORT_16C950] = {
125 .name = "16C950/954",
126 .fifo_size = 128,
127 .tx_loadsz = 128,
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
131 },
132 [PORT_16654] = {
133 .name = "ST16654",
134 .fifo_size = 64,
135 .tx_loadsz = 32,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 UART_FCR_T_TRIG_10,
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
140 },
141 [PORT_16850] = {
142 .name = "XR16850",
143 .fifo_size = 128,
144 .tx_loadsz = 128,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 },
148 [PORT_RSA] = {
149 .name = "RSA",
150 .fifo_size = 2048,
151 .tx_loadsz = 2048,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
154 },
155 [PORT_NS16550A] = {
156 .name = "NS16550A",
157 .fifo_size = 16,
158 .tx_loadsz = 16,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
161 },
162 [PORT_XSCALE] = {
163 .name = "XScale",
164 .fifo_size = 32,
165 .tx_loadsz = 32,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
168 },
169 [PORT_OCTEON] = {
170 .name = "OCTEON",
171 .fifo_size = 64,
172 .tx_loadsz = 64,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
175 },
176 [PORT_AR7] = {
177 .name = "AR7",
178 .fifo_size = 16,
179 .tx_loadsz = 16,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
182 },
183 [PORT_U6_16550A] = {
184 .name = "U6_16550A",
185 .fifo_size = 64,
186 .tx_loadsz = 64,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
189 },
190 [PORT_TEGRA] = {
191 .name = "Tegra",
192 .fifo_size = 32,
193 .tx_loadsz = 8,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_01,
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
198 },
199 [PORT_XR17D15X] = {
200 .name = "XR17D15X",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
205 UART_CAP_SLEEP,
206 },
207 [PORT_XR17V35X] = {
208 .name = "XR17V35X",
209 .fifo_size = 256,
210 .tx_loadsz = 256,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 UART_FCR_T_TRIG_11,
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
214 UART_CAP_SLEEP,
215 },
216 [PORT_LPC3220] = {
217 .name = "LPC3220",
218 .fifo_size = 64,
219 .tx_loadsz = 32,
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
223 },
224 [PORT_BRCM_TRUMANAGE] = {
225 .name = "TruManage",
226 .fifo_size = 1,
227 .tx_loadsz = 1024,
228 .flags = UART_CAP_HFIFO,
229 },
230 [PORT_8250_CIR] = {
231 .name = "CIR port"
232 },
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
235 .fifo_size = 32,
236 .tx_loadsz = 32,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 },
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
242 .fifo_size = 64,
243 .tx_loadsz = 64,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 },
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 },
254 /*
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
258 */
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
261 .fifo_size = 64,
262 .tx_loadsz = 63,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 UART_FCR7_64BYTE,
265 .flags = UART_CAP_FIFO,
266 },
267 [PORT_RT2880] = {
268 .name = "Palmchip BK-3103",
269 .fifo_size = 16,
270 .tx_loadsz = 16,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
274 },
275 };
276
277 /* Uart divisor latch read */
278 static int default_serial_dl_read(struct uart_8250_port *up)
279 {
280 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
281 }
282
283 /* Uart divisor latch write */
284 static void default_serial_dl_write(struct uart_8250_port *up, int value)
285 {
286 serial_out(up, UART_DLL, value & 0xff);
287 serial_out(up, UART_DLM, value >> 8 & 0xff);
288 }
289
290 #ifdef CONFIG_SERIAL_8250_RT288X
291
292 /* Au1x00/RT288x UART hardware has a weird register layout */
293 static const s8 au_io_in_map[8] = {
294 0, /* UART_RX */
295 2, /* UART_IER */
296 3, /* UART_IIR */
297 5, /* UART_LCR */
298 6, /* UART_MCR */
299 7, /* UART_LSR */
300 8, /* UART_MSR */
301 -1, /* UART_SCR (unmapped) */
302 };
303
304 static const s8 au_io_out_map[8] = {
305 1, /* UART_TX */
306 2, /* UART_IER */
307 4, /* UART_FCR */
308 5, /* UART_LCR */
309 6, /* UART_MCR */
310 -1, /* UART_LSR (unmapped) */
311 -1, /* UART_MSR (unmapped) */
312 -1, /* UART_SCR (unmapped) */
313 };
314
315 static unsigned int au_serial_in(struct uart_port *p, int offset)
316 {
317 if (offset >= ARRAY_SIZE(au_io_in_map))
318 return UINT_MAX;
319 offset = au_io_in_map[offset];
320 if (offset < 0)
321 return UINT_MAX;
322 return __raw_readl(p->membase + (offset << p->regshift));
323 }
324
325 static void au_serial_out(struct uart_port *p, int offset, int value)
326 {
327 if (offset >= ARRAY_SIZE(au_io_out_map))
328 return;
329 offset = au_io_out_map[offset];
330 if (offset < 0)
331 return;
332 __raw_writel(value, p->membase + (offset << p->regshift));
333 }
334
335 /* Au1x00 haven't got a standard divisor latch */
336 static int au_serial_dl_read(struct uart_8250_port *up)
337 {
338 return __raw_readl(up->port.membase + 0x28);
339 }
340
341 static void au_serial_dl_write(struct uart_8250_port *up, int value)
342 {
343 __raw_writel(value, up->port.membase + 0x28);
344 }
345
346 #endif
347
348 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
349 {
350 offset = offset << p->regshift;
351 outb(p->hub6 - 1 + offset, p->iobase);
352 return inb(p->iobase + 1);
353 }
354
355 static void hub6_serial_out(struct uart_port *p, int offset, int value)
356 {
357 offset = offset << p->regshift;
358 outb(p->hub6 - 1 + offset, p->iobase);
359 outb(value, p->iobase + 1);
360 }
361
362 static unsigned int mem_serial_in(struct uart_port *p, int offset)
363 {
364 offset = offset << p->regshift;
365 return readb(p->membase + offset);
366 }
367
368 static void mem_serial_out(struct uart_port *p, int offset, int value)
369 {
370 offset = offset << p->regshift;
371 writeb(value, p->membase + offset);
372 }
373
374 static void mem16_serial_out(struct uart_port *p, int offset, int value)
375 {
376 offset = offset << p->regshift;
377 writew(value, p->membase + offset);
378 }
379
380 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
381 {
382 offset = offset << p->regshift;
383 return readw(p->membase + offset);
384 }
385
386 static void mem32_serial_out(struct uart_port *p, int offset, int value)
387 {
388 offset = offset << p->regshift;
389 writel(value, p->membase + offset);
390 }
391
392 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
393 {
394 offset = offset << p->regshift;
395 return readl(p->membase + offset);
396 }
397
398 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
399 {
400 offset = offset << p->regshift;
401 iowrite32be(value, p->membase + offset);
402 }
403
404 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
405 {
406 offset = offset << p->regshift;
407 return ioread32be(p->membase + offset);
408 }
409
410 static unsigned int io_serial_in(struct uart_port *p, int offset)
411 {
412 offset = offset << p->regshift;
413 return inb(p->iobase + offset);
414 }
415
416 static void io_serial_out(struct uart_port *p, int offset, int value)
417 {
418 offset = offset << p->regshift;
419 outb(value, p->iobase + offset);
420 }
421
422 static int serial8250_default_handle_irq(struct uart_port *port);
423 static int exar_handle_irq(struct uart_port *port);
424
425 static void set_io_from_upio(struct uart_port *p)
426 {
427 struct uart_8250_port *up = up_to_u8250p(p);
428
429 up->dl_read = default_serial_dl_read;
430 up->dl_write = default_serial_dl_write;
431
432 switch (p->iotype) {
433 case UPIO_HUB6:
434 p->serial_in = hub6_serial_in;
435 p->serial_out = hub6_serial_out;
436 break;
437
438 case UPIO_MEM:
439 p->serial_in = mem_serial_in;
440 p->serial_out = mem_serial_out;
441 break;
442
443 case UPIO_MEM16:
444 p->serial_in = mem16_serial_in;
445 p->serial_out = mem16_serial_out;
446 break;
447
448 case UPIO_MEM32:
449 p->serial_in = mem32_serial_in;
450 p->serial_out = mem32_serial_out;
451 break;
452
453 case UPIO_MEM32BE:
454 p->serial_in = mem32be_serial_in;
455 p->serial_out = mem32be_serial_out;
456 break;
457
458 #ifdef CONFIG_SERIAL_8250_RT288X
459 case UPIO_AU:
460 p->serial_in = au_serial_in;
461 p->serial_out = au_serial_out;
462 up->dl_read = au_serial_dl_read;
463 up->dl_write = au_serial_dl_write;
464 break;
465 #endif
466
467 default:
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
471 }
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
475 }
476
477 static void
478 serial_port_out_sync(struct uart_port *p, int offset, int value)
479 {
480 switch (p->iotype) {
481 case UPIO_MEM:
482 case UPIO_MEM16:
483 case UPIO_MEM32:
484 case UPIO_MEM32BE:
485 case UPIO_AU:
486 p->serial_out(p, offset, value);
487 p->serial_in(p, UART_LCR); /* safe, no side-effects */
488 break;
489 default:
490 p->serial_out(p, offset, value);
491 }
492 }
493
494 /*
495 * For the 16C950
496 */
497 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
498 {
499 serial_out(up, UART_SCR, offset);
500 serial_out(up, UART_ICR, value);
501 }
502
503 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
504 {
505 unsigned int value;
506
507 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
508 serial_out(up, UART_SCR, offset);
509 value = serial_in(up, UART_ICR);
510 serial_icr_write(up, UART_ACR, up->acr);
511
512 return value;
513 }
514
515 /*
516 * FIFO support.
517 */
518 static void serial8250_clear_fifos(struct uart_8250_port *p)
519 {
520 if (p->capabilities & UART_CAP_FIFO) {
521 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
522 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
523 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
524 serial_out(p, UART_FCR, 0);
525 }
526 }
527
528 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
529 {
530 unsigned char mcr = serial_in(p, UART_MCR);
531
532 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
533 mcr |= UART_MCR_RTS;
534 else
535 mcr &= ~UART_MCR_RTS;
536 serial_out(p, UART_MCR, mcr);
537 }
538
539 static void serial8250_em485_handle_start_tx(unsigned long arg);
540 static void serial8250_em485_handle_stop_tx(unsigned long arg);
541
542 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
543 {
544 serial8250_clear_fifos(p);
545 serial_out(p, UART_FCR, p->fcr);
546 }
547 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
548
549 void serial8250_rpm_get(struct uart_8250_port *p)
550 {
551 if (!(p->capabilities & UART_CAP_RPM))
552 return;
553 pm_runtime_get_sync(p->port.dev);
554 }
555 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
556
557 void serial8250_rpm_put(struct uart_8250_port *p)
558 {
559 if (!(p->capabilities & UART_CAP_RPM))
560 return;
561 pm_runtime_mark_last_busy(p->port.dev);
562 pm_runtime_put_autosuspend(p->port.dev);
563 }
564 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
565
566 /**
567 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
568 * @p: uart_8250_port port instance
569 *
570 * The function is used to start rs485 software emulating on the
571 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
572 * transmission. The function is idempotent, so it is safe to call it
573 * multiple times.
574 *
575 * The caller MUST enable interrupt on empty shift register before
576 * calling serial8250_em485_init(). This interrupt is not a part of
577 * 8250 standard, but implementation defined.
578 *
579 * The function is supposed to be called from .rs485_config callback
580 * or from any other callback protected with p->port.lock spinlock.
581 *
582 * See also serial8250_em485_destroy()
583 *
584 * Return 0 - success, -errno - otherwise
585 */
586 int serial8250_em485_init(struct uart_8250_port *p)
587 {
588 if (p->em485 != NULL)
589 return 0;
590
591 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
592 if (p->em485 == NULL)
593 return -ENOMEM;
594
595 setup_timer(&p->em485->stop_tx_timer,
596 serial8250_em485_handle_stop_tx, (unsigned long)p);
597 setup_timer(&p->em485->start_tx_timer,
598 serial8250_em485_handle_start_tx, (unsigned long)p);
599 p->em485->active_timer = NULL;
600
601 serial8250_em485_rts_after_send(p);
602
603 return 0;
604 }
605 EXPORT_SYMBOL_GPL(serial8250_em485_init);
606
607 /**
608 * serial8250_em485_destroy() - put uart_8250_port into normal state
609 * @p: uart_8250_port port instance
610 *
611 * The function is used to stop rs485 software emulating on the
612 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
613 * call it multiple times.
614 *
615 * The function is supposed to be called from .rs485_config callback
616 * or from any other callback protected with p->port.lock spinlock.
617 *
618 * See also serial8250_em485_init()
619 */
620 void serial8250_em485_destroy(struct uart_8250_port *p)
621 {
622 if (p->em485 == NULL)
623 return;
624
625 del_timer(&p->em485->start_tx_timer);
626 del_timer(&p->em485->stop_tx_timer);
627
628 kfree(p->em485);
629 p->em485 = NULL;
630 }
631 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
632
633 /*
634 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
635 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
636 * empty and the HW can idle again.
637 */
638 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
639 {
640 unsigned char rpm_active;
641
642 if (!(p->capabilities & UART_CAP_RPM))
643 return;
644
645 rpm_active = xchg(&p->rpm_tx_active, 1);
646 if (rpm_active)
647 return;
648 pm_runtime_get_sync(p->port.dev);
649 }
650
651 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
652 {
653 unsigned char rpm_active;
654
655 if (!(p->capabilities & UART_CAP_RPM))
656 return;
657
658 rpm_active = xchg(&p->rpm_tx_active, 0);
659 if (!rpm_active)
660 return;
661 pm_runtime_mark_last_busy(p->port.dev);
662 pm_runtime_put_autosuspend(p->port.dev);
663 }
664
665 /*
666 * IER sleep support. UARTs which have EFRs need the "extended
667 * capability" bit enabled. Note that on XR16C850s, we need to
668 * reset LCR to write to IER.
669 */
670 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
671 {
672 unsigned char lcr = 0, efr = 0;
673 /*
674 * Exar UARTs have a SLEEP register that enables or disables
675 * each UART to enter sleep mode separately. On the XR17V35x the
676 * register is accessible to each UART at the UART_EXAR_SLEEP
677 * offset but the UART channel may only write to the corresponding
678 * bit.
679 */
680 serial8250_rpm_get(p);
681 if ((p->port.type == PORT_XR17V35X) ||
682 (p->port.type == PORT_XR17D15X)) {
683 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
684 goto out;
685 }
686
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
689 lcr = serial_in(p, UART_LCR);
690 efr = serial_in(p, UART_EFR);
691 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
692 serial_out(p, UART_EFR, UART_EFR_ECB);
693 serial_out(p, UART_LCR, 0);
694 }
695 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
696 if (p->capabilities & UART_CAP_EFR) {
697 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
698 serial_out(p, UART_EFR, efr);
699 serial_out(p, UART_LCR, lcr);
700 }
701 }
702 out:
703 serial8250_rpm_put(p);
704 }
705
706 #ifdef CONFIG_SERIAL_8250_RSA
707 /*
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
710 */
711 static int __enable_rsa(struct uart_8250_port *up)
712 {
713 unsigned char mode;
714 int result;
715
716 mode = serial_in(up, UART_RSA_MSR);
717 result = mode & UART_RSA_MSR_FIFO;
718
719 if (!result) {
720 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
723 }
724
725 if (result)
726 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
727
728 return result;
729 }
730
731 static void enable_rsa(struct uart_8250_port *up)
732 {
733 if (up->port.type == PORT_RSA) {
734 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
735 spin_lock_irq(&up->port.lock);
736 __enable_rsa(up);
737 spin_unlock_irq(&up->port.lock);
738 }
739 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
740 serial_out(up, UART_RSA_FRR, 0);
741 }
742 }
743
744 /*
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
749 */
750 static void disable_rsa(struct uart_8250_port *up)
751 {
752 unsigned char mode;
753 int result;
754
755 if (up->port.type == PORT_RSA &&
756 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
757 spin_lock_irq(&up->port.lock);
758
759 mode = serial_in(up, UART_RSA_MSR);
760 result = !(mode & UART_RSA_MSR_FIFO);
761
762 if (!result) {
763 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
766 }
767
768 if (result)
769 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
770 spin_unlock_irq(&up->port.lock);
771 }
772 }
773 #endif /* CONFIG_SERIAL_8250_RSA */
774
775 /*
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
778 */
779 static int size_fifo(struct uart_8250_port *up)
780 {
781 unsigned char old_fcr, old_mcr, old_lcr;
782 unsigned short old_dl;
783 int count;
784
785 old_lcr = serial_in(up, UART_LCR);
786 serial_out(up, UART_LCR, 0);
787 old_fcr = serial_in(up, UART_FCR);
788 old_mcr = serial_in(up, UART_MCR);
789 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
790 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
791 serial_out(up, UART_MCR, UART_MCR_LOOP);
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 old_dl = serial_dl_read(up);
794 serial_dl_write(up, 0x0001);
795 serial_out(up, UART_LCR, 0x03);
796 for (count = 0; count < 256; count++)
797 serial_out(up, UART_TX, count);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
800 (count < 256); count++)
801 serial_in(up, UART_RX);
802 serial_out(up, UART_FCR, old_fcr);
803 serial_out(up, UART_MCR, old_mcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
805 serial_dl_write(up, old_dl);
806 serial_out(up, UART_LCR, old_lcr);
807
808 return count;
809 }
810
811 /*
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
815 */
816 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
817 {
818 unsigned char old_lcr;
819 unsigned int id, old_dl;
820
821 old_lcr = serial_in(p, UART_LCR);
822 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
823 old_dl = serial_dl_read(p);
824 serial_dl_write(p, 0);
825 id = serial_dl_read(p);
826 serial_dl_write(p, old_dl);
827
828 serial_out(p, UART_LCR, old_lcr);
829
830 return id;
831 }
832
833 /*
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
839 * existence.)
840 *
841 * What evil have men's minds wrought...
842 */
843 static void autoconfig_has_efr(struct uart_8250_port *up)
844 {
845 unsigned int id1, id2, id3, rev;
846
847 /*
848 * Everything with an EFR has SLEEP
849 */
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
851
852 /*
853 * First we check to see if it's an Oxford Semiconductor UART.
854 *
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
858 */
859
860 /*
861 * Check for Oxford Semiconductor 16C950.
862 *
863 * EFR [4] must be set else this test fails.
864 *
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
868 */
869 up->acr = 0;
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871 serial_out(up, UART_EFR, UART_EFR_ECB);
872 serial_out(up, UART_LCR, 0x00);
873 id1 = serial_icr_read(up, UART_ID1);
874 id2 = serial_icr_read(up, UART_ID2);
875 id3 = serial_icr_read(up, UART_ID3);
876 rev = serial_icr_read(up, UART_REV);
877
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
879
880 if (id1 == 0x16 && id2 == 0xC9 &&
881 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
882 up->port.type = PORT_16C950;
883
884 /*
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
887 * when DLL is 0.
888 */
889 if (id3 == 0x52 && rev == 0x01)
890 up->bugs |= UART_BUG_QUOT;
891 return;
892 }
893
894 /*
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
897 * value read back:
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
899 * 0x12 - XR16C2850.
900 * 0x14 - XR16C854.
901 */
902 id1 = autoconfig_read_divisor_id(up);
903 DEBUG_AUTOCONF("850id=%04x ", id1);
904
905 id2 = id1 >> 8;
906 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
907 up->port.type = PORT_16850;
908 return;
909 }
910
911 /*
912 * It wasn't an XR16C850.
913 *
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
919 */
920 if (size_fifo(up) == 64)
921 up->port.type = PORT_16654;
922 else
923 up->port.type = PORT_16650V2;
924 }
925
926 /*
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
930 */
931 static void autoconfig_8250(struct uart_8250_port *up)
932 {
933 unsigned char scratch, status1, status2;
934
935 up->port.type = PORT_8250;
936
937 scratch = serial_in(up, UART_SCR);
938 serial_out(up, UART_SCR, 0xa5);
939 status1 = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0x5a);
941 status2 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, scratch);
943
944 if (status1 == 0xa5 && status2 == 0x5a)
945 up->port.type = PORT_16450;
946 }
947
948 static int broken_efr(struct uart_8250_port *up)
949 {
950 /*
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
954 */
955 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
956 return 1;
957
958 return 0;
959 }
960
961 /*
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
966 */
967 static void autoconfig_16550a(struct uart_8250_port *up)
968 {
969 unsigned char status1, status2;
970 unsigned int iersave;
971
972 up->port.type = PORT_16550A;
973 up->capabilities |= UART_CAP_FIFO;
974
975 /*
976 * XR17V35x UARTs have an extra divisor register, DLD
977 * that gets enabled with when DLAB is set which will
978 * cause the device to incorrectly match and assign
979 * port type to PORT_16650. The EFR for this UART is
980 * found at offset 0x09. Instead check the Deice ID (DVID)
981 * register for a 2, 4 or 8 port UART.
982 */
983 if (up->port.flags & UPF_EXAR_EFR) {
984 status1 = serial_in(up, UART_EXAR_DVID);
985 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
986 DEBUG_AUTOCONF("Exar XR17V35x ");
987 up->port.type = PORT_XR17V35X;
988 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
989 UART_CAP_SLEEP;
990
991 return;
992 }
993
994 }
995
996 /*
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
999 */
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (serial_in(up, UART_EFR) == 0) {
1002 serial_out(up, UART_EFR, 0xA8);
1003 if (serial_in(up, UART_EFR) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up->port.type = PORT_16650;
1006 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1007 } else {
1008 serial_out(up, UART_LCR, 0);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1010 UART_FCR7_64BYTE);
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_out(up, UART_FCR, 0);
1013 serial_out(up, UART_LCR, 0);
1014
1015 if (status1 == 7)
1016 up->port.type = PORT_16550A_FSL64;
1017 else
1018 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1019 }
1020 serial_out(up, UART_EFR, 0);
1021 return;
1022 }
1023
1024 /*
1025 * Maybe it requires 0xbf to be written to the LCR.
1026 * (other ST16C650V2 UARTs, TI16C752A, etc)
1027 */
1028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1029 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1030 DEBUG_AUTOCONF("EFRv2 ");
1031 autoconfig_has_efr(up);
1032 return;
1033 }
1034
1035 /*
1036 * Check for a National Semiconductor SuperIO chip.
1037 * Attempt to switch to bank 2, read the value of the LOOP bit
1038 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1039 * switch back to bank 2, read it from EXCR1 again and check
1040 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1041 */
1042 serial_out(up, UART_LCR, 0);
1043 status1 = serial_in(up, UART_MCR);
1044 serial_out(up, UART_LCR, 0xE0);
1045 status2 = serial_in(up, 0x02); /* EXCR1 */
1046
1047 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1048 serial_out(up, UART_LCR, 0);
1049 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1050 serial_out(up, UART_LCR, 0xE0);
1051 status2 = serial_in(up, 0x02); /* EXCR1 */
1052 serial_out(up, UART_LCR, 0);
1053 serial_out(up, UART_MCR, status1);
1054
1055 if ((status2 ^ status1) & UART_MCR_LOOP) {
1056 unsigned short quot;
1057
1058 serial_out(up, UART_LCR, 0xE0);
1059
1060 quot = serial_dl_read(up);
1061 quot <<= 3;
1062
1063 if (ns16550a_goto_highspeed(up))
1064 serial_dl_write(up, quot);
1065
1066 serial_out(up, UART_LCR, 0);
1067
1068 up->port.uartclk = 921600*16;
1069 up->port.type = PORT_NS16550A;
1070 up->capabilities |= UART_NATSEMI;
1071 return;
1072 }
1073 }
1074
1075 /*
1076 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1077 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1078 * Try setting it with and without DLAB set. Cheap clones
1079 * set bit 5 without DLAB set.
1080 */
1081 serial_out(up, UART_LCR, 0);
1082 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1083 status1 = serial_in(up, UART_IIR) >> 5;
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1085 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1087 status2 = serial_in(up, UART_IIR) >> 5;
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 serial_out(up, UART_LCR, 0);
1090
1091 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1092
1093 if (status1 == 6 && status2 == 7) {
1094 up->port.type = PORT_16750;
1095 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1096 return;
1097 }
1098
1099 /*
1100 * Try writing and reading the UART_IER_UUE bit (b6).
1101 * If it works, this is probably one of the Xscale platform's
1102 * internal UARTs.
1103 * We're going to explicitly set the UUE bit to 0 before
1104 * trying to write and read a 1 just to make sure it's not
1105 * already a 1 and maybe locked there before we even start start.
1106 */
1107 iersave = serial_in(up, UART_IER);
1108 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1109 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1110 /*
1111 * OK it's in a known zero state, try writing and reading
1112 * without disturbing the current state of the other bits.
1113 */
1114 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1115 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1116 /*
1117 * It's an Xscale.
1118 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1119 */
1120 DEBUG_AUTOCONF("Xscale ");
1121 up->port.type = PORT_XSCALE;
1122 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1123 return;
1124 }
1125 } else {
1126 /*
1127 * If we got here we couldn't force the IER_UUE bit to 0.
1128 * Log it and continue.
1129 */
1130 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1131 }
1132 serial_out(up, UART_IER, iersave);
1133
1134 /*
1135 * Exar uarts have EFR in a weird location
1136 */
1137 if (up->port.flags & UPF_EXAR_EFR) {
1138 DEBUG_AUTOCONF("Exar XR17D15x ");
1139 up->port.type = PORT_XR17D15X;
1140 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1141 UART_CAP_SLEEP;
1142
1143 return;
1144 }
1145
1146 /*
1147 * We distinguish between 16550A and U6 16550A by counting
1148 * how many bytes are in the FIFO.
1149 */
1150 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1151 up->port.type = PORT_U6_16550A;
1152 up->capabilities |= UART_CAP_AFE;
1153 }
1154 }
1155
1156 /*
1157 * This routine is called by rs_init() to initialize a specific serial
1158 * port. It determines what type of UART chip this serial port is
1159 * using: 8250, 16450, 16550, 16550A. The important question is
1160 * whether or not this UART is a 16550A or not, since this will
1161 * determine whether or not we can use its FIFO features or not.
1162 */
1163 static void autoconfig(struct uart_8250_port *up)
1164 {
1165 unsigned char status1, scratch, scratch2, scratch3;
1166 unsigned char save_lcr, save_mcr;
1167 struct uart_port *port = &up->port;
1168 unsigned long flags;
1169 unsigned int old_capabilities;
1170
1171 if (!port->iobase && !port->mapbase && !port->membase)
1172 return;
1173
1174 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1175 serial_index(port), port->iobase, port->membase);
1176
1177 /*
1178 * We really do need global IRQs disabled here - we're going to
1179 * be frobbing the chips IRQ enable register to see if it exists.
1180 */
1181 spin_lock_irqsave(&port->lock, flags);
1182
1183 up->capabilities = 0;
1184 up->bugs = 0;
1185
1186 if (!(port->flags & UPF_BUGGY_UART)) {
1187 /*
1188 * Do a simple existence test first; if we fail this,
1189 * there's no point trying anything else.
1190 *
1191 * 0x80 is used as a nonsense port to prevent against
1192 * false positives due to ISA bus float. The
1193 * assumption is that 0x80 is a non-existent port;
1194 * which should be safe since include/asm/io.h also
1195 * makes this assumption.
1196 *
1197 * Note: this is safe as long as MCR bit 4 is clear
1198 * and the device is in "PC" mode.
1199 */
1200 scratch = serial_in(up, UART_IER);
1201 serial_out(up, UART_IER, 0);
1202 #ifdef __i386__
1203 outb(0xff, 0x080);
1204 #endif
1205 /*
1206 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1207 * 16C754B) allow only to modify them if an EFR bit is set.
1208 */
1209 scratch2 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, 0x0F);
1211 #ifdef __i386__
1212 outb(0, 0x080);
1213 #endif
1214 scratch3 = serial_in(up, UART_IER) & 0x0f;
1215 serial_out(up, UART_IER, scratch);
1216 if (scratch2 != 0 || scratch3 != 0x0F) {
1217 /*
1218 * We failed; there's nothing here
1219 */
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1222 scratch2, scratch3);
1223 goto out;
1224 }
1225 }
1226
1227 save_mcr = serial_in(up, UART_MCR);
1228 save_lcr = serial_in(up, UART_LCR);
1229
1230 /*
1231 * Check to see if a UART is really there. Certain broken
1232 * internal modems based on the Rockwell chipset fail this
1233 * test, because they apparently don't implement the loopback
1234 * test mode. So this test is skipped on the COM 1 through
1235 * COM 4 ports. This *should* be safe, since no board
1236 * manufacturer would be stupid enough to design a board
1237 * that conflicts with COM 1-4 --- we hope!
1238 */
1239 if (!(port->flags & UPF_SKIP_TEST)) {
1240 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1241 status1 = serial_in(up, UART_MSR) & 0xF0;
1242 serial_out(up, UART_MCR, save_mcr);
1243 if (status1 != 0x90) {
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1246 status1);
1247 goto out;
1248 }
1249 }
1250
1251 /*
1252 * We're pretty sure there's a port here. Lets find out what
1253 * type of port it is. The IIR top two bits allows us to find
1254 * out if it's 8250 or 16450, 16550, 16550A or later. This
1255 * determines what we test for next.
1256 *
1257 * We also initialise the EFR (if any) to zero for later. The
1258 * EFR occupies the same register location as the FCR and IIR.
1259 */
1260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1261 serial_out(up, UART_EFR, 0);
1262 serial_out(up, UART_LCR, 0);
1263
1264 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1265 scratch = serial_in(up, UART_IIR) >> 6;
1266
1267 switch (scratch) {
1268 case 0:
1269 autoconfig_8250(up);
1270 break;
1271 case 1:
1272 port->type = PORT_UNKNOWN;
1273 break;
1274 case 2:
1275 port->type = PORT_16550;
1276 break;
1277 case 3:
1278 autoconfig_16550a(up);
1279 break;
1280 }
1281
1282 #ifdef CONFIG_SERIAL_8250_RSA
1283 /*
1284 * Only probe for RSA ports if we got the region.
1285 */
1286 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1287 __enable_rsa(up))
1288 port->type = PORT_RSA;
1289 #endif
1290
1291 serial_out(up, UART_LCR, save_lcr);
1292
1293 port->fifosize = uart_config[up->port.type].fifo_size;
1294 old_capabilities = up->capabilities;
1295 up->capabilities = uart_config[port->type].flags;
1296 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1297
1298 if (port->type == PORT_UNKNOWN)
1299 goto out_lock;
1300
1301 /*
1302 * Reset the UART.
1303 */
1304 #ifdef CONFIG_SERIAL_8250_RSA
1305 if (port->type == PORT_RSA)
1306 serial_out(up, UART_RSA_FRR, 0);
1307 #endif
1308 serial_out(up, UART_MCR, save_mcr);
1309 serial8250_clear_fifos(up);
1310 serial_in(up, UART_RX);
1311 if (up->capabilities & UART_CAP_UUE)
1312 serial_out(up, UART_IER, UART_IER_UUE);
1313 else
1314 serial_out(up, UART_IER, 0);
1315
1316 out_lock:
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 if (up->capabilities != old_capabilities) {
1319 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1320 serial_index(port), old_capabilities,
1321 up->capabilities);
1322 }
1323 out:
1324 DEBUG_AUTOCONF("iir=%d ", scratch);
1325 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1326 }
1327
1328 static void autoconfig_irq(struct uart_8250_port *up)
1329 {
1330 struct uart_port *port = &up->port;
1331 unsigned char save_mcr, save_ier;
1332 unsigned char save_ICP = 0;
1333 unsigned int ICP = 0;
1334 unsigned long irqs;
1335 int irq;
1336
1337 if (port->flags & UPF_FOURPORT) {
1338 ICP = (port->iobase & 0xfe0) | 0x1f;
1339 save_ICP = inb_p(ICP);
1340 outb_p(0x80, ICP);
1341 inb_p(ICP);
1342 }
1343
1344 if (uart_console(port))
1345 console_lock();
1346
1347 /* forget possible initially masked and pending IRQ */
1348 probe_irq_off(probe_irq_on());
1349 save_mcr = serial_in(up, UART_MCR);
1350 save_ier = serial_in(up, UART_IER);
1351 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1352
1353 irqs = probe_irq_on();
1354 serial_out(up, UART_MCR, 0);
1355 udelay(10);
1356 if (port->flags & UPF_FOURPORT) {
1357 serial_out(up, UART_MCR,
1358 UART_MCR_DTR | UART_MCR_RTS);
1359 } else {
1360 serial_out(up, UART_MCR,
1361 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1362 }
1363 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1364 serial_in(up, UART_LSR);
1365 serial_in(up, UART_RX);
1366 serial_in(up, UART_IIR);
1367 serial_in(up, UART_MSR);
1368 serial_out(up, UART_TX, 0xFF);
1369 udelay(20);
1370 irq = probe_irq_off(irqs);
1371
1372 serial_out(up, UART_MCR, save_mcr);
1373 serial_out(up, UART_IER, save_ier);
1374
1375 if (port->flags & UPF_FOURPORT)
1376 outb_p(save_ICP, ICP);
1377
1378 if (uart_console(port))
1379 console_unlock();
1380
1381 port->irq = (irq > 0) ? irq : 0;
1382 }
1383
1384 static void serial8250_stop_rx(struct uart_port *port)
1385 {
1386 struct uart_8250_port *up = up_to_u8250p(port);
1387
1388 serial8250_rpm_get(up);
1389
1390 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1391 up->port.read_status_mask &= ~UART_LSR_DR;
1392 serial_port_out(port, UART_IER, up->ier);
1393
1394 serial8250_rpm_put(up);
1395 }
1396
1397 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1398 {
1399 if (!p->em485)
1400 return;
1401
1402 serial8250_em485_rts_after_send(p);
1403 /*
1404 * Empty the RX FIFO, we are not interested in anything
1405 * received during the half-duplex transmission.
1406 * Enable previously disabled RX interrupts.
1407 */
1408 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1409 serial8250_clear_fifos(p);
1410
1411 serial8250_rpm_get(p);
1412
1413 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1414 serial_port_out(&p->port, UART_IER, p->ier);
1415
1416 serial8250_rpm_put(p);
1417 }
1418 }
1419
1420 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1421 {
1422 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1423 struct uart_8250_em485 *em485 = p->em485;
1424 unsigned long flags;
1425
1426 spin_lock_irqsave(&p->port.lock, flags);
1427 if (em485 &&
1428 em485->active_timer == &em485->stop_tx_timer) {
1429 __do_stop_tx_rs485(p);
1430 em485->active_timer = NULL;
1431 }
1432 spin_unlock_irqrestore(&p->port.lock, flags);
1433 }
1434
1435 static void __stop_tx_rs485(struct uart_8250_port *p)
1436 {
1437 struct uart_8250_em485 *em485 = p->em485;
1438
1439 if (!em485)
1440 return;
1441
1442 /*
1443 * __do_stop_tx_rs485 is going to set RTS according to config
1444 * AND flush RX FIFO if required.
1445 */
1446 if (p->port.rs485.delay_rts_after_send > 0) {
1447 em485->active_timer = &em485->stop_tx_timer;
1448 mod_timer(&em485->stop_tx_timer, jiffies +
1449 p->port.rs485.delay_rts_after_send * HZ / 1000);
1450 } else {
1451 __do_stop_tx_rs485(p);
1452 }
1453 }
1454
1455 static inline void __do_stop_tx(struct uart_8250_port *p)
1456 {
1457 if (p->ier & UART_IER_THRI) {
1458 p->ier &= ~UART_IER_THRI;
1459 serial_out(p, UART_IER, p->ier);
1460 serial8250_rpm_put_tx(p);
1461 }
1462 }
1463
1464 static inline void __stop_tx(struct uart_8250_port *p)
1465 {
1466 struct uart_8250_em485 *em485 = p->em485;
1467
1468 if (em485) {
1469 unsigned char lsr = serial_in(p, UART_LSR);
1470 /*
1471 * To provide required timeing and allow FIFO transfer,
1472 * __stop_tx_rs485 must be called only when both FIFO and
1473 * shift register are empty. It is for device driver to enable
1474 * interrupt on TEMT.
1475 */
1476 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1477 return;
1478
1479 del_timer(&em485->start_tx_timer);
1480 em485->active_timer = NULL;
1481 }
1482 __do_stop_tx(p);
1483 __stop_tx_rs485(p);
1484 }
1485
1486 static void serial8250_stop_tx(struct uart_port *port)
1487 {
1488 struct uart_8250_port *up = up_to_u8250p(port);
1489
1490 serial8250_rpm_get(up);
1491 __stop_tx(up);
1492
1493 /*
1494 * We really want to stop the transmitter from sending.
1495 */
1496 if (port->type == PORT_16C950) {
1497 up->acr |= UART_ACR_TXDIS;
1498 serial_icr_write(up, UART_ACR, up->acr);
1499 }
1500 serial8250_rpm_put(up);
1501 }
1502
1503 static inline void __start_tx(struct uart_port *port)
1504 {
1505 struct uart_8250_port *up = up_to_u8250p(port);
1506
1507 if (up->dma && !up->dma->tx_dma(up))
1508 return;
1509
1510 if (!(up->ier & UART_IER_THRI)) {
1511 up->ier |= UART_IER_THRI;
1512 serial_port_out(port, UART_IER, up->ier);
1513
1514 if (up->bugs & UART_BUG_TXEN) {
1515 unsigned char lsr;
1516
1517 lsr = serial_in(up, UART_LSR);
1518 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1519 if (lsr & UART_LSR_THRE)
1520 serial8250_tx_chars(up);
1521 }
1522 }
1523
1524 /*
1525 * Re-enable the transmitter if we disabled it.
1526 */
1527 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1528 up->acr &= ~UART_ACR_TXDIS;
1529 serial_icr_write(up, UART_ACR, up->acr);
1530 }
1531 }
1532
1533 static inline void start_tx_rs485(struct uart_port *port)
1534 {
1535 struct uart_8250_port *up = up_to_u8250p(port);
1536 struct uart_8250_em485 *em485 = up->em485;
1537 unsigned char mcr;
1538
1539 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1540 serial8250_stop_rx(&up->port);
1541
1542 del_timer(&em485->stop_tx_timer);
1543 em485->active_timer = NULL;
1544
1545 mcr = serial_in(up, UART_MCR);
1546 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1547 !!(mcr & UART_MCR_RTS)) {
1548 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1549 mcr |= UART_MCR_RTS;
1550 else
1551 mcr &= ~UART_MCR_RTS;
1552 serial_out(up, UART_MCR, mcr);
1553
1554 if (up->port.rs485.delay_rts_before_send > 0) {
1555 em485->active_timer = &em485->start_tx_timer;
1556 mod_timer(&em485->start_tx_timer, jiffies +
1557 up->port.rs485.delay_rts_before_send * HZ / 1000);
1558 return;
1559 }
1560 }
1561
1562 __start_tx(port);
1563 }
1564
1565 static void serial8250_em485_handle_start_tx(unsigned long arg)
1566 {
1567 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1568 struct uart_8250_em485 *em485 = p->em485;
1569 unsigned long flags;
1570
1571 spin_lock_irqsave(&p->port.lock, flags);
1572 if (em485 &&
1573 em485->active_timer == &em485->start_tx_timer) {
1574 __start_tx(&p->port);
1575 em485->active_timer = NULL;
1576 }
1577 spin_unlock_irqrestore(&p->port.lock, flags);
1578 }
1579
1580 static void serial8250_start_tx(struct uart_port *port)
1581 {
1582 struct uart_8250_port *up = up_to_u8250p(port);
1583 struct uart_8250_em485 *em485 = up->em485;
1584
1585 serial8250_rpm_get_tx(up);
1586
1587 if (em485 &&
1588 em485->active_timer == &em485->start_tx_timer)
1589 return;
1590
1591 if (em485)
1592 start_tx_rs485(port);
1593 else
1594 __start_tx(port);
1595 }
1596
1597 static void serial8250_throttle(struct uart_port *port)
1598 {
1599 port->throttle(port);
1600 }
1601
1602 static void serial8250_unthrottle(struct uart_port *port)
1603 {
1604 port->unthrottle(port);
1605 }
1606
1607 static void serial8250_disable_ms(struct uart_port *port)
1608 {
1609 struct uart_8250_port *up = up_to_u8250p(port);
1610
1611 /* no MSR capabilities */
1612 if (up->bugs & UART_BUG_NOMSR)
1613 return;
1614
1615 up->ier &= ~UART_IER_MSI;
1616 serial_port_out(port, UART_IER, up->ier);
1617 }
1618
1619 static void serial8250_enable_ms(struct uart_port *port)
1620 {
1621 struct uart_8250_port *up = up_to_u8250p(port);
1622
1623 /* no MSR capabilities */
1624 if (up->bugs & UART_BUG_NOMSR)
1625 return;
1626
1627 up->ier |= UART_IER_MSI;
1628
1629 serial8250_rpm_get(up);
1630 serial_port_out(port, UART_IER, up->ier);
1631 serial8250_rpm_put(up);
1632 }
1633
1634 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1635 {
1636 struct uart_port *port = &up->port;
1637 unsigned char ch;
1638 char flag = TTY_NORMAL;
1639
1640 if (likely(lsr & UART_LSR_DR))
1641 ch = serial_in(up, UART_RX);
1642 else
1643 /*
1644 * Intel 82571 has a Serial Over Lan device that will
1645 * set UART_LSR_BI without setting UART_LSR_DR when
1646 * it receives a break. To avoid reading from the
1647 * receive buffer without UART_LSR_DR bit set, we
1648 * just force the read character to be 0
1649 */
1650 ch = 0;
1651
1652 port->icount.rx++;
1653
1654 lsr |= up->lsr_saved_flags;
1655 up->lsr_saved_flags = 0;
1656
1657 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1658 if (lsr & UART_LSR_BI) {
1659 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1660 port->icount.brk++;
1661 /*
1662 * We do the SysRQ and SAK checking
1663 * here because otherwise the break
1664 * may get masked by ignore_status_mask
1665 * or read_status_mask.
1666 */
1667 if (uart_handle_break(port))
1668 return;
1669 } else if (lsr & UART_LSR_PE)
1670 port->icount.parity++;
1671 else if (lsr & UART_LSR_FE)
1672 port->icount.frame++;
1673 if (lsr & UART_LSR_OE)
1674 port->icount.overrun++;
1675
1676 /*
1677 * Mask off conditions which should be ignored.
1678 */
1679 lsr &= port->read_status_mask;
1680
1681 if (lsr & UART_LSR_BI) {
1682 DEBUG_INTR("handling break....");
1683 flag = TTY_BREAK;
1684 } else if (lsr & UART_LSR_PE)
1685 flag = TTY_PARITY;
1686 else if (lsr & UART_LSR_FE)
1687 flag = TTY_FRAME;
1688 }
1689 if (uart_handle_sysrq_char(port, ch))
1690 return;
1691
1692 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1693 }
1694
1695 /*
1696 * serial8250_rx_chars: processes according to the passed in LSR
1697 * value, and returns the remaining LSR bits not handled
1698 * by this Rx routine.
1699 */
1700 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1701 {
1702 struct uart_port *port = &up->port;
1703 int max_count = 256;
1704
1705 do {
1706 serial8250_read_char(up, lsr);
1707 if (--max_count == 0)
1708 break;
1709 lsr = serial_in(up, UART_LSR);
1710 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1711
1712 tty_flip_buffer_push(&port->state->port);
1713 return lsr;
1714 }
1715 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1716
1717 void serial8250_tx_chars(struct uart_8250_port *up)
1718 {
1719 struct uart_port *port = &up->port;
1720 struct circ_buf *xmit = &port->state->xmit;
1721 int count;
1722
1723 if (port->x_char) {
1724 serial_out(up, UART_TX, port->x_char);
1725 port->icount.tx++;
1726 port->x_char = 0;
1727 return;
1728 }
1729 if (uart_tx_stopped(port)) {
1730 serial8250_stop_tx(port);
1731 return;
1732 }
1733 if (uart_circ_empty(xmit)) {
1734 __stop_tx(up);
1735 return;
1736 }
1737
1738 count = up->tx_loadsz;
1739 do {
1740 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1741 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1742 port->icount.tx++;
1743 if (uart_circ_empty(xmit))
1744 break;
1745 if ((up->capabilities & UART_CAP_HFIFO) &&
1746 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1747 break;
1748 } while (--count > 0);
1749
1750 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1751 uart_write_wakeup(port);
1752
1753 DEBUG_INTR("THRE...");
1754
1755 /*
1756 * With RPM enabled, we have to wait until the FIFO is empty before the
1757 * HW can go idle. So we get here once again with empty FIFO and disable
1758 * the interrupt and RPM in __stop_tx()
1759 */
1760 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1761 __stop_tx(up);
1762 }
1763 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1764
1765 /* Caller holds uart port lock */
1766 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1767 {
1768 struct uart_port *port = &up->port;
1769 unsigned int status = serial_in(up, UART_MSR);
1770
1771 status |= up->msr_saved_flags;
1772 up->msr_saved_flags = 0;
1773 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1774 port->state != NULL) {
1775 if (status & UART_MSR_TERI)
1776 port->icount.rng++;
1777 if (status & UART_MSR_DDSR)
1778 port->icount.dsr++;
1779 if (status & UART_MSR_DDCD)
1780 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1781 if (status & UART_MSR_DCTS)
1782 uart_handle_cts_change(port, status & UART_MSR_CTS);
1783
1784 wake_up_interruptible(&port->state->port.delta_msr_wait);
1785 }
1786
1787 return status;
1788 }
1789 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1790
1791 /*
1792 * This handles the interrupt from one port.
1793 */
1794 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1795 {
1796 unsigned char status;
1797 unsigned long flags;
1798 struct uart_8250_port *up = up_to_u8250p(port);
1799 int dma_err = 0;
1800
1801 if (iir & UART_IIR_NO_INT)
1802 return 0;
1803
1804 spin_lock_irqsave(&port->lock, flags);
1805
1806 status = serial_port_in(port, UART_LSR);
1807
1808 DEBUG_INTR("status = %x...", status);
1809
1810 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1811 if (up->dma)
1812 dma_err = up->dma->rx_dma(up, iir);
1813
1814 if (!up->dma || dma_err)
1815 status = serial8250_rx_chars(up, status);
1816 }
1817 serial8250_modem_status(up);
1818 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1819 (status & UART_LSR_THRE))
1820 serial8250_tx_chars(up);
1821
1822 spin_unlock_irqrestore(&port->lock, flags);
1823 return 1;
1824 }
1825 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1826
1827 static int serial8250_default_handle_irq(struct uart_port *port)
1828 {
1829 struct uart_8250_port *up = up_to_u8250p(port);
1830 unsigned int iir;
1831 int ret;
1832
1833 serial8250_rpm_get(up);
1834
1835 iir = serial_port_in(port, UART_IIR);
1836 ret = serial8250_handle_irq(port, iir);
1837
1838 serial8250_rpm_put(up);
1839 return ret;
1840 }
1841
1842 /*
1843 * These Exar UARTs have an extra interrupt indicator that could
1844 * fire for a few unimplemented interrupts. One of which is a
1845 * wakeup event when coming out of sleep. Put this here just
1846 * to be on the safe side that these interrupts don't go unhandled.
1847 */
1848 static int exar_handle_irq(struct uart_port *port)
1849 {
1850 unsigned char int0, int1, int2, int3;
1851 unsigned int iir = serial_port_in(port, UART_IIR);
1852 int ret;
1853
1854 ret = serial8250_handle_irq(port, iir);
1855
1856 if ((port->type == PORT_XR17V35X) ||
1857 (port->type == PORT_XR17D15X)) {
1858 int0 = serial_port_in(port, 0x80);
1859 int1 = serial_port_in(port, 0x81);
1860 int2 = serial_port_in(port, 0x82);
1861 int3 = serial_port_in(port, 0x83);
1862 }
1863
1864 return ret;
1865 }
1866
1867 static unsigned int serial8250_tx_empty(struct uart_port *port)
1868 {
1869 struct uart_8250_port *up = up_to_u8250p(port);
1870 unsigned long flags;
1871 unsigned int lsr;
1872
1873 serial8250_rpm_get(up);
1874
1875 spin_lock_irqsave(&port->lock, flags);
1876 lsr = serial_port_in(port, UART_LSR);
1877 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1878 spin_unlock_irqrestore(&port->lock, flags);
1879
1880 serial8250_rpm_put(up);
1881
1882 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1883 }
1884
1885 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1886 {
1887 struct uart_8250_port *up = up_to_u8250p(port);
1888 unsigned int status;
1889 unsigned int ret;
1890
1891 serial8250_rpm_get(up);
1892 status = serial8250_modem_status(up);
1893 serial8250_rpm_put(up);
1894
1895 ret = 0;
1896 if (status & UART_MSR_DCD)
1897 ret |= TIOCM_CAR;
1898 if (status & UART_MSR_RI)
1899 ret |= TIOCM_RNG;
1900 if (status & UART_MSR_DSR)
1901 ret |= TIOCM_DSR;
1902 if (status & UART_MSR_CTS)
1903 ret |= TIOCM_CTS;
1904 return ret;
1905 }
1906
1907 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1908 {
1909 struct uart_8250_port *up = up_to_u8250p(port);
1910 unsigned char mcr = 0;
1911
1912 if (mctrl & TIOCM_RTS)
1913 mcr |= UART_MCR_RTS;
1914 if (mctrl & TIOCM_DTR)
1915 mcr |= UART_MCR_DTR;
1916 if (mctrl & TIOCM_OUT1)
1917 mcr |= UART_MCR_OUT1;
1918 if (mctrl & TIOCM_OUT2)
1919 mcr |= UART_MCR_OUT2;
1920 if (mctrl & TIOCM_LOOP)
1921 mcr |= UART_MCR_LOOP;
1922
1923 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1924
1925 serial_port_out(port, UART_MCR, mcr);
1926 }
1927 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1928
1929 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1930 {
1931 if (port->set_mctrl)
1932 port->set_mctrl(port, mctrl);
1933 else
1934 serial8250_do_set_mctrl(port, mctrl);
1935 }
1936
1937 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1938 {
1939 struct uart_8250_port *up = up_to_u8250p(port);
1940 unsigned long flags;
1941
1942 serial8250_rpm_get(up);
1943 spin_lock_irqsave(&port->lock, flags);
1944 if (break_state == -1)
1945 up->lcr |= UART_LCR_SBC;
1946 else
1947 up->lcr &= ~UART_LCR_SBC;
1948 serial_port_out(port, UART_LCR, up->lcr);
1949 spin_unlock_irqrestore(&port->lock, flags);
1950 serial8250_rpm_put(up);
1951 }
1952
1953 /*
1954 * Wait for transmitter & holding register to empty
1955 */
1956 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1957 {
1958 unsigned int status, tmout = 10000;
1959
1960 /* Wait up to 10ms for the character(s) to be sent. */
1961 for (;;) {
1962 status = serial_in(up, UART_LSR);
1963
1964 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1965
1966 if ((status & bits) == bits)
1967 break;
1968 if (--tmout == 0)
1969 break;
1970 udelay(1);
1971 }
1972
1973 /* Wait up to 1s for flow control if necessary */
1974 if (up->port.flags & UPF_CONS_FLOW) {
1975 unsigned int tmout;
1976
1977 for (tmout = 1000000; tmout; tmout--) {
1978 unsigned int msr = serial_in(up, UART_MSR);
1979 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1980 if (msr & UART_MSR_CTS)
1981 break;
1982 udelay(1);
1983 touch_nmi_watchdog();
1984 }
1985 }
1986 }
1987
1988 #ifdef CONFIG_CONSOLE_POLL
1989 /*
1990 * Console polling routines for writing and reading from the uart while
1991 * in an interrupt or debug context.
1992 */
1993
1994 static int serial8250_get_poll_char(struct uart_port *port)
1995 {
1996 struct uart_8250_port *up = up_to_u8250p(port);
1997 unsigned char lsr;
1998 int status;
1999
2000 serial8250_rpm_get(up);
2001
2002 lsr = serial_port_in(port, UART_LSR);
2003
2004 if (!(lsr & UART_LSR_DR)) {
2005 status = NO_POLL_CHAR;
2006 goto out;
2007 }
2008
2009 status = serial_port_in(port, UART_RX);
2010 out:
2011 serial8250_rpm_put(up);
2012 return status;
2013 }
2014
2015
2016 static void serial8250_put_poll_char(struct uart_port *port,
2017 unsigned char c)
2018 {
2019 unsigned int ier;
2020 struct uart_8250_port *up = up_to_u8250p(port);
2021
2022 serial8250_rpm_get(up);
2023 /*
2024 * First save the IER then disable the interrupts
2025 */
2026 ier = serial_port_in(port, UART_IER);
2027 if (up->capabilities & UART_CAP_UUE)
2028 serial_port_out(port, UART_IER, UART_IER_UUE);
2029 else
2030 serial_port_out(port, UART_IER, 0);
2031
2032 wait_for_xmitr(up, BOTH_EMPTY);
2033 /*
2034 * Send the character out.
2035 */
2036 serial_port_out(port, UART_TX, c);
2037
2038 /*
2039 * Finally, wait for transmitter to become empty
2040 * and restore the IER
2041 */
2042 wait_for_xmitr(up, BOTH_EMPTY);
2043 serial_port_out(port, UART_IER, ier);
2044 serial8250_rpm_put(up);
2045 }
2046
2047 #endif /* CONFIG_CONSOLE_POLL */
2048
2049 int serial8250_do_startup(struct uart_port *port)
2050 {
2051 struct uart_8250_port *up = up_to_u8250p(port);
2052 unsigned long flags;
2053 unsigned char lsr, iir;
2054 int retval;
2055
2056 if (!port->fifosize)
2057 port->fifosize = uart_config[port->type].fifo_size;
2058 if (!up->tx_loadsz)
2059 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2060 if (!up->capabilities)
2061 up->capabilities = uart_config[port->type].flags;
2062 up->mcr = 0;
2063
2064 if (port->iotype != up->cur_iotype)
2065 set_io_from_upio(port);
2066
2067 serial8250_rpm_get(up);
2068 if (port->type == PORT_16C950) {
2069 /* Wake up and initialize UART */
2070 up->acr = 0;
2071 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2072 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2073 serial_port_out(port, UART_IER, 0);
2074 serial_port_out(port, UART_LCR, 0);
2075 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2076 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2077 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2078 serial_port_out(port, UART_LCR, 0);
2079 }
2080
2081 #ifdef CONFIG_SERIAL_8250_RSA
2082 /*
2083 * If this is an RSA port, see if we can kick it up to the
2084 * higher speed clock.
2085 */
2086 enable_rsa(up);
2087 #endif
2088
2089 if (port->type == PORT_XR17V35X) {
2090 /*
2091 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2092 * MCR [7:5] and MSR [7:0]
2093 */
2094 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2095
2096 /*
2097 * Make sure all interrups are masked until initialization is
2098 * complete and the FIFOs are cleared
2099 */
2100 serial_port_out(port, UART_IER, 0);
2101 }
2102
2103 /*
2104 * Clear the FIFO buffers and disable them.
2105 * (they will be reenabled in set_termios())
2106 */
2107 serial8250_clear_fifos(up);
2108
2109 /*
2110 * Clear the interrupt registers.
2111 */
2112 serial_port_in(port, UART_LSR);
2113 serial_port_in(port, UART_RX);
2114 serial_port_in(port, UART_IIR);
2115 serial_port_in(port, UART_MSR);
2116
2117 /*
2118 * At this point, there's no way the LSR could still be 0xff;
2119 * if it is, then bail out, because there's likely no UART
2120 * here.
2121 */
2122 if (!(port->flags & UPF_BUGGY_UART) &&
2123 (serial_port_in(port, UART_LSR) == 0xff)) {
2124 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2125 serial_index(port));
2126 retval = -ENODEV;
2127 goto out;
2128 }
2129
2130 /*
2131 * For a XR16C850, we need to set the trigger levels
2132 */
2133 if (port->type == PORT_16850) {
2134 unsigned char fctr;
2135
2136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2137
2138 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2139 serial_port_out(port, UART_FCTR,
2140 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2141 serial_port_out(port, UART_TRG, UART_TRG_96);
2142 serial_port_out(port, UART_FCTR,
2143 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2144 serial_port_out(port, UART_TRG, UART_TRG_96);
2145
2146 serial_port_out(port, UART_LCR, 0);
2147 }
2148
2149 if (port->irq) {
2150 unsigned char iir1;
2151 /*
2152 * Test for UARTs that do not reassert THRE when the
2153 * transmitter is idle and the interrupt has already
2154 * been cleared. Real 16550s should always reassert
2155 * this interrupt whenever the transmitter is idle and
2156 * the interrupt is enabled. Delays are necessary to
2157 * allow register changes to become visible.
2158 */
2159 spin_lock_irqsave(&port->lock, flags);
2160 if (up->port.irqflags & IRQF_SHARED)
2161 disable_irq_nosync(port->irq);
2162
2163 wait_for_xmitr(up, UART_LSR_THRE);
2164 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2165 udelay(1); /* allow THRE to set */
2166 iir1 = serial_port_in(port, UART_IIR);
2167 serial_port_out(port, UART_IER, 0);
2168 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2169 udelay(1); /* allow a working UART time to re-assert THRE */
2170 iir = serial_port_in(port, UART_IIR);
2171 serial_port_out(port, UART_IER, 0);
2172
2173 if (port->irqflags & IRQF_SHARED)
2174 enable_irq(port->irq);
2175 spin_unlock_irqrestore(&port->lock, flags);
2176
2177 /*
2178 * If the interrupt is not reasserted, or we otherwise
2179 * don't trust the iir, setup a timer to kick the UART
2180 * on a regular basis.
2181 */
2182 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2183 up->port.flags & UPF_BUG_THRE) {
2184 up->bugs |= UART_BUG_THRE;
2185 }
2186 }
2187
2188 retval = up->ops->setup_irq(up);
2189 if (retval)
2190 goto out;
2191
2192 /*
2193 * Now, initialize the UART
2194 */
2195 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2196
2197 spin_lock_irqsave(&port->lock, flags);
2198 if (up->port.flags & UPF_FOURPORT) {
2199 if (!up->port.irq)
2200 up->port.mctrl |= TIOCM_OUT1;
2201 } else
2202 /*
2203 * Most PC uarts need OUT2 raised to enable interrupts.
2204 */
2205 if (port->irq)
2206 up->port.mctrl |= TIOCM_OUT2;
2207
2208 serial8250_set_mctrl(port, port->mctrl);
2209
2210 /*
2211 * Serial over Lan (SoL) hack:
2212 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2213 * used for Serial Over Lan. Those chips take a longer time than a
2214 * normal serial device to signalize that a transmission data was
2215 * queued. Due to that, the above test generally fails. One solution
2216 * would be to delay the reading of iir. However, this is not
2217 * reliable, since the timeout is variable. So, let's just don't
2218 * test if we receive TX irq. This way, we'll never enable
2219 * UART_BUG_TXEN.
2220 */
2221 if (up->port.flags & UPF_NO_TXEN_TEST)
2222 goto dont_test_tx_en;
2223
2224 /*
2225 * Do a quick test to see if we receive an interrupt when we enable
2226 * the TX irq.
2227 */
2228 serial_port_out(port, UART_IER, UART_IER_THRI);
2229 lsr = serial_port_in(port, UART_LSR);
2230 iir = serial_port_in(port, UART_IIR);
2231 serial_port_out(port, UART_IER, 0);
2232
2233 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2234 if (!(up->bugs & UART_BUG_TXEN)) {
2235 up->bugs |= UART_BUG_TXEN;
2236 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2237 serial_index(port));
2238 }
2239 } else {
2240 up->bugs &= ~UART_BUG_TXEN;
2241 }
2242
2243 dont_test_tx_en:
2244 spin_unlock_irqrestore(&port->lock, flags);
2245
2246 /*
2247 * Clear the interrupt registers again for luck, and clear the
2248 * saved flags to avoid getting false values from polling
2249 * routines or the previous session.
2250 */
2251 serial_port_in(port, UART_LSR);
2252 serial_port_in(port, UART_RX);
2253 serial_port_in(port, UART_IIR);
2254 serial_port_in(port, UART_MSR);
2255 up->lsr_saved_flags = 0;
2256 up->msr_saved_flags = 0;
2257
2258 /*
2259 * Request DMA channels for both RX and TX.
2260 */
2261 if (up->dma) {
2262 retval = serial8250_request_dma(up);
2263 if (retval) {
2264 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2265 serial_index(port));
2266 up->dma = NULL;
2267 }
2268 }
2269
2270 /*
2271 * Set the IER shadow for rx interrupts but defer actual interrupt
2272 * enable until after the FIFOs are enabled; otherwise, an already-
2273 * active sender can swamp the interrupt handler with "too much work".
2274 */
2275 up->ier = UART_IER_RLSI | UART_IER_RDI;
2276
2277 if (port->flags & UPF_FOURPORT) {
2278 unsigned int icp;
2279 /*
2280 * Enable interrupts on the AST Fourport board
2281 */
2282 icp = (port->iobase & 0xfe0) | 0x01f;
2283 outb_p(0x80, icp);
2284 inb_p(icp);
2285 }
2286 retval = 0;
2287 out:
2288 serial8250_rpm_put(up);
2289 return retval;
2290 }
2291 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2292
2293 static int serial8250_startup(struct uart_port *port)
2294 {
2295 if (port->startup)
2296 return port->startup(port);
2297 return serial8250_do_startup(port);
2298 }
2299
2300 void serial8250_do_shutdown(struct uart_port *port)
2301 {
2302 struct uart_8250_port *up = up_to_u8250p(port);
2303 unsigned long flags;
2304
2305 serial8250_rpm_get(up);
2306 /*
2307 * Disable interrupts from this port
2308 */
2309 spin_lock_irqsave(&port->lock, flags);
2310 up->ier = 0;
2311 serial_port_out(port, UART_IER, 0);
2312 spin_unlock_irqrestore(&port->lock, flags);
2313
2314 synchronize_irq(port->irq);
2315
2316 if (up->dma)
2317 serial8250_release_dma(up);
2318
2319 spin_lock_irqsave(&port->lock, flags);
2320 if (port->flags & UPF_FOURPORT) {
2321 /* reset interrupts on the AST Fourport board */
2322 inb((port->iobase & 0xfe0) | 0x1f);
2323 port->mctrl |= TIOCM_OUT1;
2324 } else
2325 port->mctrl &= ~TIOCM_OUT2;
2326
2327 serial8250_set_mctrl(port, port->mctrl);
2328 spin_unlock_irqrestore(&port->lock, flags);
2329
2330 /*
2331 * Disable break condition and FIFOs
2332 */
2333 serial_port_out(port, UART_LCR,
2334 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2335 serial8250_clear_fifos(up);
2336
2337 #ifdef CONFIG_SERIAL_8250_RSA
2338 /*
2339 * Reset the RSA board back to 115kbps compat mode.
2340 */
2341 disable_rsa(up);
2342 #endif
2343
2344 /*
2345 * Read data port to reset things, and then unlink from
2346 * the IRQ chain.
2347 */
2348 serial_port_in(port, UART_RX);
2349 serial8250_rpm_put(up);
2350
2351 up->ops->release_irq(up);
2352 }
2353 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2354
2355 static void serial8250_shutdown(struct uart_port *port)
2356 {
2357 if (port->shutdown)
2358 port->shutdown(port);
2359 else
2360 serial8250_do_shutdown(port);
2361 }
2362
2363 /*
2364 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2365 * Calculate divisor with extra 4-bit fractional portion
2366 */
2367 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2368 unsigned int baud,
2369 unsigned int *frac)
2370 {
2371 struct uart_port *port = &up->port;
2372 unsigned int quot_16;
2373
2374 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2375 *frac = quot_16 & 0x0f;
2376
2377 return quot_16 >> 4;
2378 }
2379
2380 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2381 unsigned int baud,
2382 unsigned int *frac)
2383 {
2384 struct uart_port *port = &up->port;
2385 unsigned int quot;
2386
2387 /*
2388 * Handle magic divisors for baud rates above baud_base on
2389 * SMSC SuperIO chips.
2390 *
2391 */
2392 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2393 baud == (port->uartclk/4))
2394 quot = 0x8001;
2395 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2396 baud == (port->uartclk/8))
2397 quot = 0x8002;
2398 else if (up->port.type == PORT_XR17V35X)
2399 quot = xr17v35x_get_divisor(up, baud, frac);
2400 else
2401 quot = uart_get_divisor(port, baud);
2402
2403 /*
2404 * Oxford Semi 952 rev B workaround
2405 */
2406 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2407 quot++;
2408
2409 return quot;
2410 }
2411
2412 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2413 tcflag_t c_cflag)
2414 {
2415 unsigned char cval;
2416
2417 switch (c_cflag & CSIZE) {
2418 case CS5:
2419 cval = UART_LCR_WLEN5;
2420 break;
2421 case CS6:
2422 cval = UART_LCR_WLEN6;
2423 break;
2424 case CS7:
2425 cval = UART_LCR_WLEN7;
2426 break;
2427 default:
2428 case CS8:
2429 cval = UART_LCR_WLEN8;
2430 break;
2431 }
2432
2433 if (c_cflag & CSTOPB)
2434 cval |= UART_LCR_STOP;
2435 if (c_cflag & PARENB) {
2436 cval |= UART_LCR_PARITY;
2437 if (up->bugs & UART_BUG_PARITY)
2438 up->fifo_bug = true;
2439 }
2440 if (!(c_cflag & PARODD))
2441 cval |= UART_LCR_EPAR;
2442 #ifdef CMSPAR
2443 if (c_cflag & CMSPAR)
2444 cval |= UART_LCR_SPAR;
2445 #endif
2446
2447 return cval;
2448 }
2449
2450 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2451 unsigned int quot, unsigned int quot_frac)
2452 {
2453 struct uart_8250_port *up = up_to_u8250p(port);
2454
2455 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2456 if (is_omap1510_8250(up)) {
2457 if (baud == 115200) {
2458 quot = 1;
2459 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2460 } else
2461 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2462 }
2463
2464 /*
2465 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2466 * otherwise just set DLAB
2467 */
2468 if (up->capabilities & UART_NATSEMI)
2469 serial_port_out(port, UART_LCR, 0xe0);
2470 else
2471 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2472
2473 serial_dl_write(up, quot);
2474
2475 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2476 if (up->port.type == PORT_XR17V35X)
2477 serial_port_out(port, 0x2, quot_frac);
2478 }
2479
2480 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2481 struct ktermios *termios,
2482 struct ktermios *old)
2483 {
2484 unsigned int tolerance = port->uartclk / 100;
2485
2486 /*
2487 * Ask the core to calculate the divisor for us.
2488 * Allow 1% tolerance at the upper limit so uart clks marginally
2489 * slower than nominal still match standard baud rates without
2490 * causing transmission errors.
2491 */
2492 return uart_get_baud_rate(port, termios, old,
2493 port->uartclk / 16 / 0xffff,
2494 (port->uartclk + tolerance) / 16);
2495 }
2496
2497 void
2498 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2499 struct ktermios *old)
2500 {
2501 struct uart_8250_port *up = up_to_u8250p(port);
2502 unsigned char cval;
2503 unsigned long flags;
2504 unsigned int baud, quot, frac = 0;
2505
2506 cval = serial8250_compute_lcr(up, termios->c_cflag);
2507
2508 baud = serial8250_get_baud_rate(port, termios, old);
2509 quot = serial8250_get_divisor(up, baud, &frac);
2510
2511 /*
2512 * Ok, we're now changing the port state. Do it with
2513 * interrupts disabled.
2514 */
2515 serial8250_rpm_get(up);
2516 spin_lock_irqsave(&port->lock, flags);
2517
2518 up->lcr = cval; /* Save computed LCR */
2519
2520 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2521 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2522 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2523 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2524 up->fcr |= UART_FCR_TRIGGER_1;
2525 }
2526 }
2527
2528 /*
2529 * MCR-based auto flow control. When AFE is enabled, RTS will be
2530 * deasserted when the receive FIFO contains more characters than
2531 * the trigger, or the MCR RTS bit is cleared. In the case where
2532 * the remote UART is not using CTS auto flow control, we must
2533 * have sufficient FIFO entries for the latency of the remote
2534 * UART to respond. IOW, at least 32 bytes of FIFO.
2535 */
2536 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2537 up->mcr &= ~UART_MCR_AFE;
2538 if (termios->c_cflag & CRTSCTS)
2539 up->mcr |= UART_MCR_AFE;
2540 }
2541
2542 /*
2543 * Update the per-port timeout.
2544 */
2545 uart_update_timeout(port, termios->c_cflag, baud);
2546
2547 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2548 if (termios->c_iflag & INPCK)
2549 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2550 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2551 port->read_status_mask |= UART_LSR_BI;
2552
2553 /*
2554 * Characteres to ignore
2555 */
2556 port->ignore_status_mask = 0;
2557 if (termios->c_iflag & IGNPAR)
2558 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2559 if (termios->c_iflag & IGNBRK) {
2560 port->ignore_status_mask |= UART_LSR_BI;
2561 /*
2562 * If we're ignoring parity and break indicators,
2563 * ignore overruns too (for real raw support).
2564 */
2565 if (termios->c_iflag & IGNPAR)
2566 port->ignore_status_mask |= UART_LSR_OE;
2567 }
2568
2569 /*
2570 * ignore all characters if CREAD is not set
2571 */
2572 if ((termios->c_cflag & CREAD) == 0)
2573 port->ignore_status_mask |= UART_LSR_DR;
2574
2575 /*
2576 * CTS flow control flag and modem status interrupts
2577 */
2578 up->ier &= ~UART_IER_MSI;
2579 if (!(up->bugs & UART_BUG_NOMSR) &&
2580 UART_ENABLE_MS(&up->port, termios->c_cflag))
2581 up->ier |= UART_IER_MSI;
2582 if (up->capabilities & UART_CAP_UUE)
2583 up->ier |= UART_IER_UUE;
2584 if (up->capabilities & UART_CAP_RTOIE)
2585 up->ier |= UART_IER_RTOIE;
2586
2587 serial_port_out(port, UART_IER, up->ier);
2588
2589 if (up->capabilities & UART_CAP_EFR) {
2590 unsigned char efr = 0;
2591 /*
2592 * TI16C752/Startech hardware flow control. FIXME:
2593 * - TI16C752 requires control thresholds to be set.
2594 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2595 */
2596 if (termios->c_cflag & CRTSCTS)
2597 efr |= UART_EFR_CTS;
2598
2599 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2600 if (port->flags & UPF_EXAR_EFR)
2601 serial_port_out(port, UART_XR_EFR, efr);
2602 else
2603 serial_port_out(port, UART_EFR, efr);
2604 }
2605
2606 serial8250_set_divisor(port, baud, quot, frac);
2607
2608 /*
2609 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2610 * is written without DLAB set, this mode will be disabled.
2611 */
2612 if (port->type == PORT_16750)
2613 serial_port_out(port, UART_FCR, up->fcr);
2614
2615 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2616 if (port->type != PORT_16750) {
2617 /* emulated UARTs (Lucent Venus 167x) need two steps */
2618 if (up->fcr & UART_FCR_ENABLE_FIFO)
2619 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2620 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2621 }
2622 serial8250_set_mctrl(port, port->mctrl);
2623 spin_unlock_irqrestore(&port->lock, flags);
2624 serial8250_rpm_put(up);
2625
2626 /* Don't rewrite B0 */
2627 if (tty_termios_baud_rate(termios))
2628 tty_termios_encode_baud_rate(termios, baud, baud);
2629 }
2630 EXPORT_SYMBOL(serial8250_do_set_termios);
2631
2632 static void
2633 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2634 struct ktermios *old)
2635 {
2636 if (port->set_termios)
2637 port->set_termios(port, termios, old);
2638 else
2639 serial8250_do_set_termios(port, termios, old);
2640 }
2641
2642 static void
2643 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2644 {
2645 if (termios->c_line == N_PPS) {
2646 port->flags |= UPF_HARDPPS_CD;
2647 spin_lock_irq(&port->lock);
2648 serial8250_enable_ms(port);
2649 spin_unlock_irq(&port->lock);
2650 } else {
2651 port->flags &= ~UPF_HARDPPS_CD;
2652 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2653 spin_lock_irq(&port->lock);
2654 serial8250_disable_ms(port);
2655 spin_unlock_irq(&port->lock);
2656 }
2657 }
2658 }
2659
2660
2661 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2662 unsigned int oldstate)
2663 {
2664 struct uart_8250_port *p = up_to_u8250p(port);
2665
2666 serial8250_set_sleep(p, state != 0);
2667 }
2668 EXPORT_SYMBOL(serial8250_do_pm);
2669
2670 static void
2671 serial8250_pm(struct uart_port *port, unsigned int state,
2672 unsigned int oldstate)
2673 {
2674 if (port->pm)
2675 port->pm(port, state, oldstate);
2676 else
2677 serial8250_do_pm(port, state, oldstate);
2678 }
2679
2680 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2681 {
2682 if (pt->port.mapsize)
2683 return pt->port.mapsize;
2684 if (pt->port.iotype == UPIO_AU) {
2685 if (pt->port.type == PORT_RT2880)
2686 return 0x100;
2687 return 0x1000;
2688 }
2689 if (is_omap1_8250(pt))
2690 return 0x16 << pt->port.regshift;
2691
2692 return 8 << pt->port.regshift;
2693 }
2694
2695 /*
2696 * Resource handling.
2697 */
2698 static int serial8250_request_std_resource(struct uart_8250_port *up)
2699 {
2700 unsigned int size = serial8250_port_size(up);
2701 struct uart_port *port = &up->port;
2702 int ret = 0;
2703
2704 switch (port->iotype) {
2705 case UPIO_AU:
2706 case UPIO_TSI:
2707 case UPIO_MEM32:
2708 case UPIO_MEM32BE:
2709 case UPIO_MEM16:
2710 case UPIO_MEM:
2711 if (!port->mapbase)
2712 break;
2713
2714 if (!request_mem_region(port->mapbase, size, "serial")) {
2715 ret = -EBUSY;
2716 break;
2717 }
2718
2719 if (port->flags & UPF_IOREMAP) {
2720 port->membase = ioremap_nocache(port->mapbase, size);
2721 if (!port->membase) {
2722 release_mem_region(port->mapbase, size);
2723 ret = -ENOMEM;
2724 }
2725 }
2726 break;
2727
2728 case UPIO_HUB6:
2729 case UPIO_PORT:
2730 if (!request_region(port->iobase, size, "serial"))
2731 ret = -EBUSY;
2732 break;
2733 }
2734 return ret;
2735 }
2736
2737 static void serial8250_release_std_resource(struct uart_8250_port *up)
2738 {
2739 unsigned int size = serial8250_port_size(up);
2740 struct uart_port *port = &up->port;
2741
2742 switch (port->iotype) {
2743 case UPIO_AU:
2744 case UPIO_TSI:
2745 case UPIO_MEM32:
2746 case UPIO_MEM32BE:
2747 case UPIO_MEM16:
2748 case UPIO_MEM:
2749 if (!port->mapbase)
2750 break;
2751
2752 if (port->flags & UPF_IOREMAP) {
2753 iounmap(port->membase);
2754 port->membase = NULL;
2755 }
2756
2757 release_mem_region(port->mapbase, size);
2758 break;
2759
2760 case UPIO_HUB6:
2761 case UPIO_PORT:
2762 release_region(port->iobase, size);
2763 break;
2764 }
2765 }
2766
2767 static void serial8250_release_port(struct uart_port *port)
2768 {
2769 struct uart_8250_port *up = up_to_u8250p(port);
2770
2771 serial8250_release_std_resource(up);
2772 }
2773
2774 static int serial8250_request_port(struct uart_port *port)
2775 {
2776 struct uart_8250_port *up = up_to_u8250p(port);
2777
2778 return serial8250_request_std_resource(up);
2779 }
2780
2781 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2782 {
2783 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2784 unsigned char bytes;
2785
2786 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2787
2788 return bytes ? bytes : -EOPNOTSUPP;
2789 }
2790
2791 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2792 {
2793 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2794 int i;
2795
2796 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2797 return -EOPNOTSUPP;
2798
2799 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2800 if (bytes < conf_type->rxtrig_bytes[i])
2801 /* Use the nearest lower value */
2802 return (--i) << UART_FCR_R_TRIG_SHIFT;
2803 }
2804
2805 return UART_FCR_R_TRIG_11;
2806 }
2807
2808 static int do_get_rxtrig(struct tty_port *port)
2809 {
2810 struct uart_state *state = container_of(port, struct uart_state, port);
2811 struct uart_port *uport = state->uart_port;
2812 struct uart_8250_port *up = up_to_u8250p(uport);
2813
2814 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2815 return -EINVAL;
2816
2817 return fcr_get_rxtrig_bytes(up);
2818 }
2819
2820 static int do_serial8250_get_rxtrig(struct tty_port *port)
2821 {
2822 int rxtrig_bytes;
2823
2824 mutex_lock(&port->mutex);
2825 rxtrig_bytes = do_get_rxtrig(port);
2826 mutex_unlock(&port->mutex);
2827
2828 return rxtrig_bytes;
2829 }
2830
2831 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2832 struct device_attribute *attr, char *buf)
2833 {
2834 struct tty_port *port = dev_get_drvdata(dev);
2835 int rxtrig_bytes;
2836
2837 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2838 if (rxtrig_bytes < 0)
2839 return rxtrig_bytes;
2840
2841 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2842 }
2843
2844 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2845 {
2846 struct uart_state *state = container_of(port, struct uart_state, port);
2847 struct uart_port *uport = state->uart_port;
2848 struct uart_8250_port *up = up_to_u8250p(uport);
2849 int rxtrig;
2850
2851 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2852 up->fifo_bug)
2853 return -EINVAL;
2854
2855 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2856 if (rxtrig < 0)
2857 return rxtrig;
2858
2859 serial8250_clear_fifos(up);
2860 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2861 up->fcr |= (unsigned char)rxtrig;
2862 serial_out(up, UART_FCR, up->fcr);
2863 return 0;
2864 }
2865
2866 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2867 {
2868 int ret;
2869
2870 mutex_lock(&port->mutex);
2871 ret = do_set_rxtrig(port, bytes);
2872 mutex_unlock(&port->mutex);
2873
2874 return ret;
2875 }
2876
2877 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2878 struct device_attribute *attr, const char *buf, size_t count)
2879 {
2880 struct tty_port *port = dev_get_drvdata(dev);
2881 unsigned char bytes;
2882 int ret;
2883
2884 if (!count)
2885 return -EINVAL;
2886
2887 ret = kstrtou8(buf, 10, &bytes);
2888 if (ret < 0)
2889 return ret;
2890
2891 ret = do_serial8250_set_rxtrig(port, bytes);
2892 if (ret < 0)
2893 return ret;
2894
2895 return count;
2896 }
2897
2898 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2899 serial8250_get_attr_rx_trig_bytes,
2900 serial8250_set_attr_rx_trig_bytes);
2901
2902 static struct attribute *serial8250_dev_attrs[] = {
2903 &dev_attr_rx_trig_bytes.attr,
2904 NULL,
2905 };
2906
2907 static struct attribute_group serial8250_dev_attr_group = {
2908 .attrs = serial8250_dev_attrs,
2909 };
2910
2911 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2912 {
2913 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2914
2915 if (conf_type->rxtrig_bytes[0])
2916 up->port.attr_group = &serial8250_dev_attr_group;
2917 }
2918
2919 static void serial8250_config_port(struct uart_port *port, int flags)
2920 {
2921 struct uart_8250_port *up = up_to_u8250p(port);
2922 int ret;
2923
2924 /*
2925 * Find the region that we can probe for. This in turn
2926 * tells us whether we can probe for the type of port.
2927 */
2928 ret = serial8250_request_std_resource(up);
2929 if (ret < 0)
2930 return;
2931
2932 if (port->iotype != up->cur_iotype)
2933 set_io_from_upio(port);
2934
2935 if (flags & UART_CONFIG_TYPE)
2936 autoconfig(up);
2937
2938 /* if access method is AU, it is a 16550 with a quirk */
2939 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2940 up->bugs |= UART_BUG_NOMSR;
2941
2942 /* HW bugs may trigger IRQ while IIR == NO_INT */
2943 if (port->type == PORT_TEGRA)
2944 up->bugs |= UART_BUG_NOMSR;
2945
2946 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2947 autoconfig_irq(up);
2948
2949 if (port->type == PORT_UNKNOWN)
2950 serial8250_release_std_resource(up);
2951
2952 /* Fixme: probably not the best place for this */
2953 if ((port->type == PORT_XR17V35X) ||
2954 (port->type == PORT_XR17D15X))
2955 port->handle_irq = exar_handle_irq;
2956
2957 register_dev_spec_attr_grp(up);
2958 up->fcr = uart_config[up->port.type].fcr;
2959 }
2960
2961 static int
2962 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2963 {
2964 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2965 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2966 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2967 ser->type == PORT_STARTECH)
2968 return -EINVAL;
2969 return 0;
2970 }
2971
2972 static const char *serial8250_type(struct uart_port *port)
2973 {
2974 int type = port->type;
2975
2976 if (type >= ARRAY_SIZE(uart_config))
2977 type = 0;
2978 return uart_config[type].name;
2979 }
2980
2981 static const struct uart_ops serial8250_pops = {
2982 .tx_empty = serial8250_tx_empty,
2983 .set_mctrl = serial8250_set_mctrl,
2984 .get_mctrl = serial8250_get_mctrl,
2985 .stop_tx = serial8250_stop_tx,
2986 .start_tx = serial8250_start_tx,
2987 .throttle = serial8250_throttle,
2988 .unthrottle = serial8250_unthrottle,
2989 .stop_rx = serial8250_stop_rx,
2990 .enable_ms = serial8250_enable_ms,
2991 .break_ctl = serial8250_break_ctl,
2992 .startup = serial8250_startup,
2993 .shutdown = serial8250_shutdown,
2994 .set_termios = serial8250_set_termios,
2995 .set_ldisc = serial8250_set_ldisc,
2996 .pm = serial8250_pm,
2997 .type = serial8250_type,
2998 .release_port = serial8250_release_port,
2999 .request_port = serial8250_request_port,
3000 .config_port = serial8250_config_port,
3001 .verify_port = serial8250_verify_port,
3002 #ifdef CONFIG_CONSOLE_POLL
3003 .poll_get_char = serial8250_get_poll_char,
3004 .poll_put_char = serial8250_put_poll_char,
3005 #endif
3006 };
3007
3008 void serial8250_init_port(struct uart_8250_port *up)
3009 {
3010 struct uart_port *port = &up->port;
3011
3012 spin_lock_init(&port->lock);
3013 port->ops = &serial8250_pops;
3014
3015 up->cur_iotype = 0xFF;
3016 }
3017 EXPORT_SYMBOL_GPL(serial8250_init_port);
3018
3019 void serial8250_set_defaults(struct uart_8250_port *up)
3020 {
3021 struct uart_port *port = &up->port;
3022
3023 if (up->port.flags & UPF_FIXED_TYPE) {
3024 unsigned int type = up->port.type;
3025
3026 if (!up->port.fifosize)
3027 up->port.fifosize = uart_config[type].fifo_size;
3028 if (!up->tx_loadsz)
3029 up->tx_loadsz = uart_config[type].tx_loadsz;
3030 if (!up->capabilities)
3031 up->capabilities = uart_config[type].flags;
3032 }
3033
3034 set_io_from_upio(port);
3035
3036 /* default dma handlers */
3037 if (up->dma) {
3038 if (!up->dma->tx_dma)
3039 up->dma->tx_dma = serial8250_tx_dma;
3040 if (!up->dma->rx_dma)
3041 up->dma->rx_dma = serial8250_rx_dma;
3042 }
3043 }
3044 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3045
3046 #ifdef CONFIG_SERIAL_8250_CONSOLE
3047
3048 static void serial8250_console_putchar(struct uart_port *port, int ch)
3049 {
3050 struct uart_8250_port *up = up_to_u8250p(port);
3051
3052 wait_for_xmitr(up, UART_LSR_THRE);
3053 serial_port_out(port, UART_TX, ch);
3054 }
3055
3056 /*
3057 * Restore serial console when h/w power-off detected
3058 */
3059 static void serial8250_console_restore(struct uart_8250_port *up)
3060 {
3061 struct uart_port *port = &up->port;
3062 struct ktermios termios;
3063 unsigned int baud, quot, frac = 0;
3064
3065 termios.c_cflag = port->cons->cflag;
3066 if (port->state->port.tty && termios.c_cflag == 0)
3067 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3068
3069 baud = serial8250_get_baud_rate(port, &termios, NULL);
3070 quot = serial8250_get_divisor(up, baud, &frac);
3071
3072 serial8250_set_divisor(port, baud, quot, frac);
3073 serial_port_out(port, UART_LCR, up->lcr);
3074 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
3075 }
3076
3077 /*
3078 * Print a string to the serial port trying not to disturb
3079 * any possible real use of the port...
3080 *
3081 * The console_lock must be held when we get here.
3082 */
3083 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3084 unsigned int count)
3085 {
3086 struct uart_port *port = &up->port;
3087 unsigned long flags;
3088 unsigned int ier;
3089 int locked = 1;
3090
3091 touch_nmi_watchdog();
3092
3093 serial8250_rpm_get(up);
3094
3095 if (port->sysrq)
3096 locked = 0;
3097 else if (oops_in_progress)
3098 locked = spin_trylock_irqsave(&port->lock, flags);
3099 else
3100 spin_lock_irqsave(&port->lock, flags);
3101
3102 /*
3103 * First save the IER then disable the interrupts
3104 */
3105 ier = serial_port_in(port, UART_IER);
3106
3107 if (up->capabilities & UART_CAP_UUE)
3108 serial_port_out(port, UART_IER, UART_IER_UUE);
3109 else
3110 serial_port_out(port, UART_IER, 0);
3111
3112 /* check scratch reg to see if port powered off during system sleep */
3113 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3114 serial8250_console_restore(up);
3115 up->canary = 0;
3116 }
3117
3118 uart_console_write(port, s, count, serial8250_console_putchar);
3119
3120 /*
3121 * Finally, wait for transmitter to become empty
3122 * and restore the IER
3123 */
3124 wait_for_xmitr(up, BOTH_EMPTY);
3125 serial_port_out(port, UART_IER, ier);
3126
3127 /*
3128 * The receive handling will happen properly because the
3129 * receive ready bit will still be set; it is not cleared
3130 * on read. However, modem control will not, we must
3131 * call it if we have saved something in the saved flags
3132 * while processing with interrupts off.
3133 */
3134 if (up->msr_saved_flags)
3135 serial8250_modem_status(up);
3136
3137 if (locked)
3138 spin_unlock_irqrestore(&port->lock, flags);
3139 serial8250_rpm_put(up);
3140 }
3141
3142 static unsigned int probe_baud(struct uart_port *port)
3143 {
3144 unsigned char lcr, dll, dlm;
3145 unsigned int quot;
3146
3147 lcr = serial_port_in(port, UART_LCR);
3148 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3149 dll = serial_port_in(port, UART_DLL);
3150 dlm = serial_port_in(port, UART_DLM);
3151 serial_port_out(port, UART_LCR, lcr);
3152
3153 quot = (dlm << 8) | dll;
3154 return (port->uartclk / 16) / quot;
3155 }
3156
3157 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3158 {
3159 int baud = 9600;
3160 int bits = 8;
3161 int parity = 'n';
3162 int flow = 'n';
3163
3164 if (!port->iobase && !port->membase)
3165 return -ENODEV;
3166
3167 if (options)
3168 uart_parse_options(options, &baud, &parity, &bits, &flow);
3169 else if (probe)
3170 baud = probe_baud(port);
3171
3172 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3173 }
3174
3175 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3176
3177 MODULE_LICENSE("GPL");
Linux with added FPC-III support