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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / tty / synclink.c
blobf5476e270734b24a030a2b20db04628209a25994
1 /*
2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 *
14 * Original release 01/11/99
15 *
16 * This code is released under the GNU General Public License (GPL)
17 *
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
20 *
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
25 *
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
30 *
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
33 *
34 * 2000/02/16
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
40 *
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
52 */
53
54 #if defined(__i386__)
55 # define BREAKPOINT() asm(" int $3");
56 #else
57 # define BREAKPOINT() { }
58 #endif
59
60 #define MAX_ISA_DEVICES 10
61 #define MAX_PCI_DEVICES 10
62 #define MAX_TOTAL_DEVICES 20
63
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/signal.h>
67 #include <linux/sched.h>
68 #include <linux/timer.h>
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/tty.h>
72 #include <linux/tty_flip.h>
73 #include <linux/serial.h>
74 #include <linux/major.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
79 #include <linux/mm.h>
80 #include <linux/seq_file.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/vmalloc.h>
85 #include <linux/init.h>
86 #include <linux/ioctl.h>
87 #include <linux/synclink.h>
88
89 #include <asm/io.h>
90 #include <asm/irq.h>
91 #include <asm/dma.h>
92 #include <linux/bitops.h>
93 #include <asm/types.h>
94 #include <linux/termios.h>
95 #include <linux/workqueue.h>
96 #include <linux/hdlc.h>
97 #include <linux/dma-mapping.h>
98
99 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100 #define SYNCLINK_GENERIC_HDLC 1
101 #else
102 #define SYNCLINK_GENERIC_HDLC 0
103 #endif
104
105 #define GET_USER(error,value,addr) error = get_user(value,addr)
106 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107 #define PUT_USER(error,value,addr) error = put_user(value,addr)
108 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110 #include <asm/uaccess.h>
111
112 #define RCLRVALUE 0xffff
113
114 static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE /* unsigned char parity; */
128 };
129
130 #define SHARED_MEM_ADDRESS_SIZE 0x40000
131 #define BUFFERLISTSIZE 4096
132 #define DMABUFFERSIZE 4096
133 #define MAXRXFRAMES 7
134
135 typedef struct _DMABUFFERENTRY
136 {
137 u32 phys_addr; /* 32-bit flat physical address of data buffer */
138 volatile u16 count; /* buffer size/data count */
139 volatile u16 status; /* Control/status field */
140 volatile u16 rcc; /* character count field */
141 u16 reserved; /* padding required by 16C32 */
142 u32 link; /* 32-bit flat link to next buffer entry */
143 char *virt_addr; /* virtual address of data buffer */
144 u32 phys_entry; /* physical address of this buffer entry */
145 dma_addr_t dma_addr;
146 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148 /* The queue of BH actions to be performed */
149
150 #define BH_RECEIVE 1
151 #define BH_TRANSMIT 2
152 #define BH_STATUS 4
153
154 #define IO_PIN_SHUTDOWN_LIMIT 100
155
156 struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165 };
166
167 /* transmit holding buffer definitions*/
168 #define MAX_TX_HOLDING_BUFFERS 5
169 struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172 };
173
174
175 /*
176 * Device instance data structure
177 */
178
179 struct mgsl_struct {
180 int magic;
181 struct tty_port port;
182 int line;
183 int hw_version;
184
185 struct mgsl_icount icount;
186
187 int timeout;
188 int x_char; /* xon/xoff character */
189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer; /* HDLC transmit timeout timer */
199 struct mgsl_struct *next_device; /* device list link */
200
201 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
202 struct work_struct task; /* task structure for scheduling bh */
203
204 u32 EventMask; /* event trigger mask */
205 u32 RecordedEvents; /* pending events */
206
207 u32 max_frame_size; /* as set by device config */
208
209 u32 pending_bh;
210
211 bool bh_running; /* Protection from multiple */
212 int isr_overflow;
213 bool bh_requested;
214
215 int dcd_chkcount; /* check counts to prevent */
216 int cts_chkcount; /* too many IRQs if a signal */
217 int dsr_chkcount; /* is floating */
218 int ri_chkcount;
219
220 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
223
224 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers; /* number of tx dma frames required */
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
232 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer; /* next tx dma buffer to be loaded */
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
238 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index; /* next tx holding buffer to store user request */
240 int tx_holding_count; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
246
247 bool tx_enabled;
248 bool tx_active;
249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25]; /* device instance name */
255
256 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus; /* expansion bus number (zero based) */
258 unsigned char function; /* PCI device number */
259
260 unsigned int io_base; /* base I/O address of adapter */
261 unsigned int io_addr_size; /* size of the I/O address range */
262 bool io_addr_requested; /* true if I/O address requested */
263
264 unsigned int irq_level; /* interrupt level */
265 unsigned long irq_flags;
266 bool irq_requested; /* true if IRQ requested */
267
268 unsigned int dma_level; /* DMA channel */
269 bool dma_requested; /* true if dma channel requested */
270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params; /* communications parameters */
276
277 unsigned char serial_signals; /* current serial signal states */
278
279 bool irq_occurred; /* for diagnostics use */
280 unsigned int init_error; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base; /* shared memory address (PCI only) */
285 u32 phys_memory_base;
286 bool shared_mem_requested;
287
288 unsigned char* lcr_base; /* local config registers (PCI only) */
289 u32 phys_lcr_base;
290 u32 lcr_offset;
291 bool lcr_mem_requested;
292
293 u32 misc_ctrl_value;
294 char *flag_buf;
295 bool drop_rts_on_tx_done;
296
297 bool loopmode_insert_requested;
298 bool loopmode_send_done_requested;
299
300 struct _input_signal_events input_signal_events;
301
302 /* generic HDLC device parts */
303 int netcount;
304 spinlock_t netlock;
305
306 #if SYNCLINK_GENERIC_HDLC
307 struct net_device *netdev;
308 #endif
309 };
310
311 #define MGSL_MAGIC 0x5401
312
313 /*
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
315 */
316 #ifndef SERIAL_XMIT_SIZE
317 #define SERIAL_XMIT_SIZE 4096
318 #endif
319
320 /*
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
323 */
324
325
326 #define DCPIN 2 /* Bit 1 of I/O address */
327 #define SDPIN 4 /* Bit 2 of I/O address */
328
329 #define DCAR 0 /* DMA command/address register */
330 #define CCAR SDPIN /* channel command/address register */
331 #define DATAREG DCPIN + SDPIN /* serial data register */
332 #define MSBONLY 0x41
333 #define LSBONLY 0x40
334
335 /*
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
338 */
339
340 #define CMR 0x02 /* Channel mode Register */
341 #define CCSR 0x04 /* Channel Command/status Register */
342 #define CCR 0x06 /* Channel Control Register */
343 #define PSR 0x08 /* Port status Register */
344 #define PCR 0x0a /* Port Control Register */
345 #define TMDR 0x0c /* Test mode Data Register */
346 #define TMCR 0x0e /* Test mode Control Register */
347 #define CMCR 0x10 /* Clock mode Control Register */
348 #define HCR 0x12 /* Hardware Configuration Register */
349 #define IVR 0x14 /* Interrupt Vector Register */
350 #define IOCR 0x16 /* Input/Output Control Register */
351 #define ICR 0x18 /* Interrupt Control Register */
352 #define DCCR 0x1a /* Daisy Chain Control Register */
353 #define MISR 0x1c /* Misc Interrupt status Register */
354 #define SICR 0x1e /* status Interrupt Control Register */
355 #define RDR 0x20 /* Receive Data Register */
356 #define RMR 0x22 /* Receive mode Register */
357 #define RCSR 0x24 /* Receive Command/status Register */
358 #define RICR 0x26 /* Receive Interrupt Control Register */
359 #define RSR 0x28 /* Receive Sync Register */
360 #define RCLR 0x2a /* Receive count Limit Register */
361 #define RCCR 0x2c /* Receive Character count Register */
362 #define TC0R 0x2e /* Time Constant 0 Register */
363 #define TDR 0x30 /* Transmit Data Register */
364 #define TMR 0x32 /* Transmit mode Register */
365 #define TCSR 0x34 /* Transmit Command/status Register */
366 #define TICR 0x36 /* Transmit Interrupt Control Register */
367 #define TSR 0x38 /* Transmit Sync Register */
368 #define TCLR 0x3a /* Transmit count Limit Register */
369 #define TCCR 0x3c /* Transmit Character count Register */
370 #define TC1R 0x3e /* Time Constant 1 Register */
371
372
373 /*
374 * MACRO DEFINITIONS FOR DMA REGISTERS
375 */
376
377 #define DCR 0x06 /* DMA Control Register (shared) */
378 #define DACR 0x08 /* DMA Array count Register (shared) */
379 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
384
385 #define TDMR 0x02 /* Transmit DMA mode Register */
386 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387 #define TBCR 0x2a /* Transmit Byte count Register */
388 #define TARL 0x2c /* Transmit Address Register (low) */
389 #define TARU 0x2e /* Transmit Address Register (high) */
390 #define NTBCR 0x3a /* Next Transmit Byte count Register */
391 #define NTARL 0x3c /* Next Transmit Address Register (low) */
392 #define NTARU 0x3e /* Next Transmit Address Register (high) */
393
394 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396 #define RBCR 0xaa /* Receive Byte count Register */
397 #define RARL 0xac /* Receive Address Register (low) */
398 #define RARU 0xae /* Receive Address Register (high) */
399 #define NRBCR 0xba /* Next Receive Byte count Register */
400 #define NRARL 0xbc /* Next Receive Address Register (low) */
401 #define NRARU 0xbe /* Next Receive Address Register (high) */
402
403
404 /*
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
406 */
407
408 #define MODEMSTATUS_DTR 0x80
409 #define MODEMSTATUS_DSR 0x40
410 #define MODEMSTATUS_RTS 0x20
411 #define MODEMSTATUS_CTS 0x10
412 #define MODEMSTATUS_RI 0x04
413 #define MODEMSTATUS_DCD 0x01
414
415
416 /*
417 * Channel Command/Address Register (CCAR) Command Codes
418 */
419
420 #define RTCmd_Null 0x0000
421 #define RTCmd_ResetHighestIus 0x1000
422 #define RTCmd_TriggerChannelLoadDma 0x2000
423 #define RTCmd_TriggerRxDma 0x2800
424 #define RTCmd_TriggerTxDma 0x3000
425 #define RTCmd_TriggerRxAndTxDma 0x3800
426 #define RTCmd_PurgeRxFifo 0x4800
427 #define RTCmd_PurgeTxFifo 0x5000
428 #define RTCmd_PurgeRxAndTxFifo 0x5800
429 #define RTCmd_LoadRcc 0x6800
430 #define RTCmd_LoadTcc 0x7000
431 #define RTCmd_LoadRccAndTcc 0x7800
432 #define RTCmd_LoadTC0 0x8800
433 #define RTCmd_LoadTC1 0x9000
434 #define RTCmd_LoadTC0AndTC1 0x9800
435 #define RTCmd_SerialDataLSBFirst 0xa000
436 #define RTCmd_SerialDataMSBFirst 0xa800
437 #define RTCmd_SelectBigEndian 0xb000
438 #define RTCmd_SelectLittleEndian 0xb800
439
440
441 /*
442 * DMA Command/Address Register (DCAR) Command Codes
443 */
444
445 #define DmaCmd_Null 0x0000
446 #define DmaCmd_ResetTxChannel 0x1000
447 #define DmaCmd_ResetRxChannel 0x1200
448 #define DmaCmd_StartTxChannel 0x2000
449 #define DmaCmd_StartRxChannel 0x2200
450 #define DmaCmd_ContinueTxChannel 0x3000
451 #define DmaCmd_ContinueRxChannel 0x3200
452 #define DmaCmd_PauseTxChannel 0x4000
453 #define DmaCmd_PauseRxChannel 0x4200
454 #define DmaCmd_AbortTxChannel 0x5000
455 #define DmaCmd_AbortRxChannel 0x5200
456 #define DmaCmd_InitTxChannel 0x7000
457 #define DmaCmd_InitRxChannel 0x7200
458 #define DmaCmd_ResetHighestDmaIus 0x8000
459 #define DmaCmd_ResetAllChannels 0x9000
460 #define DmaCmd_StartAllChannels 0xa000
461 #define DmaCmd_ContinueAllChannels 0xb000
462 #define DmaCmd_PauseAllChannels 0xc000
463 #define DmaCmd_AbortAllChannels 0xd000
464 #define DmaCmd_InitAllChannels 0xf000
465
466 #define TCmd_Null 0x0000
467 #define TCmd_ClearTxCRC 0x2000
468 #define TCmd_SelectTicrTtsaData 0x4000
469 #define TCmd_SelectTicrTxFifostatus 0x5000
470 #define TCmd_SelectTicrIntLevel 0x6000
471 #define TCmd_SelectTicrdma_level 0x7000
472 #define TCmd_SendFrame 0x8000
473 #define TCmd_SendAbort 0x9000
474 #define TCmd_EnableDleInsertion 0xc000
475 #define TCmd_DisableDleInsertion 0xd000
476 #define TCmd_ClearEofEom 0xe000
477 #define TCmd_SetEofEom 0xf000
478
479 #define RCmd_Null 0x0000
480 #define RCmd_ClearRxCRC 0x2000
481 #define RCmd_EnterHuntmode 0x3000
482 #define RCmd_SelectRicrRtsaData 0x4000
483 #define RCmd_SelectRicrRxFifostatus 0x5000
484 #define RCmd_SelectRicrIntLevel 0x6000
485 #define RCmd_SelectRicrdma_level 0x7000
486
487 /*
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
489 */
490
491 #define RECEIVE_STATUS BIT5
492 #define RECEIVE_DATA BIT4
493 #define TRANSMIT_STATUS BIT3
494 #define TRANSMIT_DATA BIT2
495 #define IO_PIN BIT1
496 #define MISC BIT0
497
498
499 /*
500 * Receive status Bits in Receive Command/status Register RCSR
501 */
502
503 #define RXSTATUS_SHORT_FRAME BIT8
504 #define RXSTATUS_CODE_VIOLATION BIT8
505 #define RXSTATUS_EXITED_HUNT BIT7
506 #define RXSTATUS_IDLE_RECEIVED BIT6
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
509 #define RXSTATUS_RXBOUND BIT4
510 #define RXSTATUS_CRC_ERROR BIT3
511 #define RXSTATUS_FRAMING_ERROR BIT3
512 #define RXSTATUS_ABORT BIT2
513 #define RXSTATUS_PARITY_ERROR BIT2
514 #define RXSTATUS_OVERRUN BIT1
515 #define RXSTATUS_DATA_AVAILABLE BIT0
516 #define RXSTATUS_ALL 0x01f6
517 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
518
519 /*
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
522 */
523 #define IDLEMODE_FLAGS 0x0000
524 #define IDLEMODE_ALT_ONE_ZERO 0x0100
525 #define IDLEMODE_ZERO 0x0200
526 #define IDLEMODE_ONE 0x0300
527 #define IDLEMODE_ALT_MARK_SPACE 0x0500
528 #define IDLEMODE_SPACE 0x0600
529 #define IDLEMODE_MARK 0x0700
530 #define IDLEMODE_MASK 0x0700
531
532 /*
533 * IUSC revision identifiers
534 */
535 #define IUSC_SL1660 0x4d44
536 #define IUSC_PRE_SL1660 0x4553
537
538 /*
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
540 */
541
542 #define TCSR_PRESERVE 0x0F00
543
544 #define TCSR_UNDERWAIT BIT11
545 #define TXSTATUS_PREAMBLE_SENT BIT7
546 #define TXSTATUS_IDLE_SENT BIT6
547 #define TXSTATUS_ABORT_SENT BIT5
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
550 #define TXSTATUS_CRC_SENT BIT3
551 #define TXSTATUS_ALL_SENT BIT2
552 #define TXSTATUS_UNDERRUN BIT1
553 #define TXSTATUS_FIFO_EMPTY BIT0
554 #define TXSTATUS_ALL 0x00fa
555 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
556
557
558 #define MISCSTATUS_RXC_LATCHED BIT15
559 #define MISCSTATUS_RXC BIT14
560 #define MISCSTATUS_TXC_LATCHED BIT13
561 #define MISCSTATUS_TXC BIT12
562 #define MISCSTATUS_RI_LATCHED BIT11
563 #define MISCSTATUS_RI BIT10
564 #define MISCSTATUS_DSR_LATCHED BIT9
565 #define MISCSTATUS_DSR BIT8
566 #define MISCSTATUS_DCD_LATCHED BIT7
567 #define MISCSTATUS_DCD BIT6
568 #define MISCSTATUS_CTS_LATCHED BIT5
569 #define MISCSTATUS_CTS BIT4
570 #define MISCSTATUS_RCC_UNDERRUN BIT3
571 #define MISCSTATUS_DPLL_NO_SYNC BIT2
572 #define MISCSTATUS_BRG1_ZERO BIT1
573 #define MISCSTATUS_BRG0_ZERO BIT0
574
575 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
577
578 #define SICR_RXC_ACTIVE BIT15
579 #define SICR_RXC_INACTIVE BIT14
580 #define SICR_RXC (BIT15|BIT14)
581 #define SICR_TXC_ACTIVE BIT13
582 #define SICR_TXC_INACTIVE BIT12
583 #define SICR_TXC (BIT13|BIT12)
584 #define SICR_RI_ACTIVE BIT11
585 #define SICR_RI_INACTIVE BIT10
586 #define SICR_RI (BIT11|BIT10)
587 #define SICR_DSR_ACTIVE BIT9
588 #define SICR_DSR_INACTIVE BIT8
589 #define SICR_DSR (BIT9|BIT8)
590 #define SICR_DCD_ACTIVE BIT7
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
593 #define SICR_CTS_ACTIVE BIT5
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5|BIT4)
596 #define SICR_RCC_UNDERFLOW BIT3
597 #define SICR_DPLL_NO_SYNC BIT2
598 #define SICR_BRG1_ZERO BIT1
599 #define SICR_BRG0_ZERO BIT0
600
601 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
602 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
603 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
604 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
606
607 #define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609
610 #define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612
613 #define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615
616 #define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
618
619 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
620
621 /*
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
624 */
625
626 #define TXSTATUS_PREAMBLE_SENT BIT7
627 #define TXSTATUS_IDLE_SENT BIT6
628 #define TXSTATUS_ABORT_SENT BIT5
629 #define TXSTATUS_EOF BIT4
630 #define TXSTATUS_CRC_SENT BIT3
631 #define TXSTATUS_ALL_SENT BIT2
632 #define TXSTATUS_UNDERRUN BIT1
633 #define TXSTATUS_FIFO_EMPTY BIT0
634
635 #define DICR_MASTER BIT15
636 #define DICR_TRANSMIT BIT0
637 #define DICR_RECEIVE BIT1
638
639 #define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
641
642 #define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
644
645 #define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647
648 #define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
650
651 /* Transmit status Bits in Transmit Control status Register (TCSR) */
652 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
653
654
655 #define DISABLE_UNCONDITIONAL 0
656 #define DISABLE_END_OF_FRAME 1
657 #define ENABLE_UNCONDITIONAL 2
658 #define ENABLE_AUTO_CTS 3
659 #define ENABLE_AUTO_DCD 3
660 #define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662 #define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
664
665 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
666 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
667 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
668
669 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
670 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
671 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
672 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
673 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
674
675 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
677
678 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
679
680 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
681 static void usc_start_receiver( struct mgsl_struct *info );
682 static void usc_stop_receiver( struct mgsl_struct *info );
683
684 static void usc_start_transmitter( struct mgsl_struct *info );
685 static void usc_stop_transmitter( struct mgsl_struct *info );
686 static void usc_set_txidle( struct mgsl_struct *info );
687 static void usc_load_txfifo( struct mgsl_struct *info );
688
689 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
690 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
691
692 static void usc_get_serial_signals( struct mgsl_struct *info );
693 static void usc_set_serial_signals( struct mgsl_struct *info );
694
695 static void usc_reset( struct mgsl_struct *info );
696
697 static void usc_set_sync_mode( struct mgsl_struct *info );
698 static void usc_set_sdlc_mode( struct mgsl_struct *info );
699 static void usc_set_async_mode( struct mgsl_struct *info );
700 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
701
702 static void usc_loopback_frame( struct mgsl_struct *info );
703
704 static void mgsl_tx_timeout(unsigned long context);
705
706
707 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
708 static void usc_loopmode_insert_request( struct mgsl_struct * info );
709 static int usc_loopmode_active( struct mgsl_struct * info);
710 static void usc_loopmode_send_done( struct mgsl_struct * info );
711
712 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
713
714 #if SYNCLINK_GENERIC_HDLC
715 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
716 static void hdlcdev_tx_done(struct mgsl_struct *info);
717 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
718 static int hdlcdev_init(struct mgsl_struct *info);
719 static void hdlcdev_exit(struct mgsl_struct *info);
720 #endif
721
722 /*
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
725 */
726
727 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
728 (0x00400020 + \
729 ((WrHold) << 30) + \
730 ((WrDly) << 28) + \
731 ((RdDly) << 26) + \
732 ((Nwdd) << 20) + \
733 ((Nwad) << 15) + \
734 ((Nxda) << 13) + \
735 ((Nrdd) << 11) + \
736 ((Nrad) << 6) )
737
738 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
739
740 /*
741 * Adapter diagnostic routines
742 */
743 static bool mgsl_register_test( struct mgsl_struct *info );
744 static bool mgsl_irq_test( struct mgsl_struct *info );
745 static bool mgsl_dma_test( struct mgsl_struct *info );
746 static bool mgsl_memory_test( struct mgsl_struct *info );
747 static int mgsl_adapter_test( struct mgsl_struct *info );
748
749 /*
750 * device and resource management routines
751 */
752 static int mgsl_claim_resources(struct mgsl_struct *info);
753 static void mgsl_release_resources(struct mgsl_struct *info);
754 static void mgsl_add_device(struct mgsl_struct *info);
755 static struct mgsl_struct* mgsl_allocate_device(void);
756
757 /*
758 * DMA buffer manupulation functions.
759 */
760 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
761 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
762 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
763 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
764 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
765 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
766 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
767 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
768
769 /*
770 * DMA and Shared Memory buffer allocation and formatting
771 */
772 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
773 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
774 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
775 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
777 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
778 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
779 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
781 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
782 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
783 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
784
785 /*
786 * Bottom half interrupt handlers
787 */
788 static void mgsl_bh_handler(struct work_struct *work);
789 static void mgsl_bh_receive(struct mgsl_struct *info);
790 static void mgsl_bh_transmit(struct mgsl_struct *info);
791 static void mgsl_bh_status(struct mgsl_struct *info);
792
793 /*
794 * Interrupt handler routines and dispatch table.
795 */
796 static void mgsl_isr_null( struct mgsl_struct *info );
797 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
798 static void mgsl_isr_receive_data( struct mgsl_struct *info );
799 static void mgsl_isr_receive_status( struct mgsl_struct *info );
800 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
801 static void mgsl_isr_io_pin( struct mgsl_struct *info );
802 static void mgsl_isr_misc( struct mgsl_struct *info );
803 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
804 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
805
806 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
807
808 static isr_dispatch_func UscIsrTable[7] =
809 {
810 mgsl_isr_null,
811 mgsl_isr_misc,
812 mgsl_isr_io_pin,
813 mgsl_isr_transmit_data,
814 mgsl_isr_transmit_status,
815 mgsl_isr_receive_data,
816 mgsl_isr_receive_status
817 };
818
819 /*
820 * ioctl call handlers
821 */
822 static int tiocmget(struct tty_struct *tty);
823 static int tiocmset(struct tty_struct *tty,
824 unsigned int set, unsigned int clear);
825 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
826 __user *user_icount);
827 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
828 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
829 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
830 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
831 static int mgsl_txenable(struct mgsl_struct * info, int enable);
832 static int mgsl_txabort(struct mgsl_struct * info);
833 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
834 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
835 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
836
837 /* set non-zero on successful registration with PCI subsystem */
838 static bool pci_registered;
839
840 /*
841 * Global linked list of SyncLink devices
842 */
843 static struct mgsl_struct *mgsl_device_list;
844 static int mgsl_device_count;
845
846 /*
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
850 */
851 static bool break_on_load;
852
853 /*
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
856 */
857 static int ttymajor;
858
859 /*
860 * Array of user specified options for ISA adapters.
861 */
862 static int io[MAX_ISA_DEVICES];
863 static int irq[MAX_ISA_DEVICES];
864 static int dma[MAX_ISA_DEVICES];
865 static int debug_level;
866 static int maxframe[MAX_TOTAL_DEVICES];
867 static int txdmabufs[MAX_TOTAL_DEVICES];
868 static int txholdbufs[MAX_TOTAL_DEVICES];
869
870 module_param(break_on_load, bool, 0);
871 module_param(ttymajor, int, 0);
872 module_param_array(io, int, NULL, 0);
873 module_param_array(irq, int, NULL, 0);
874 module_param_array(dma, int, NULL, 0);
875 module_param(debug_level, int, 0);
876 module_param_array(maxframe, int, NULL, 0);
877 module_param_array(txdmabufs, int, NULL, 0);
878 module_param_array(txholdbufs, int, NULL, 0);
879
880 static char *driver_name = "SyncLink serial driver";
881 static char *driver_version = "$Revision: 4.38 $";
882
883 static int synclink_init_one (struct pci_dev *dev,
884 const struct pci_device_id *ent);
885 static void synclink_remove_one (struct pci_dev *dev);
886
887 static struct pci_device_id synclink_pci_tbl[] = {
888 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
889 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
890 { 0, }, /* terminate list */
891 };
892 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
893
894 MODULE_LICENSE("GPL");
895
896 static struct pci_driver synclink_pci_driver = {
897 .name = "synclink",
898 .id_table = synclink_pci_tbl,
899 .probe = synclink_init_one,
900 .remove = synclink_remove_one,
901 };
902
903 static struct tty_driver *serial_driver;
904
905 /* number of characters left in xmit buffer before we ask for more */
906 #define WAKEUP_CHARS 256
907
908
909 static void mgsl_change_params(struct mgsl_struct *info);
910 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
911
912 /*
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
917 */
918 static void* mgsl_get_text_ptr(void)
919 {
920 return mgsl_get_text_ptr;
921 }
922
923 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
924 char *name, const char *routine)
925 {
926 #ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic =
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo =
930 "Warning: null mgsl_struct for (%s) in %s\n";
931
932 if (!info) {
933 printk(badinfo, name, routine);
934 return 1;
935 }
936 if (info->magic != MGSL_MAGIC) {
937 printk(badmagic, name, routine);
938 return 1;
939 }
940 #else
941 if (!info)
942 return 1;
943 #endif
944 return 0;
945 }
946
947 /**
948 * line discipline callback wrappers
949 *
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
952 *
953 * ldisc_receive_buf - pass receive data to line discipline
954 */
955
956 static void ldisc_receive_buf(struct tty_struct *tty,
957 const __u8 *data, char *flags, int count)
958 {
959 struct tty_ldisc *ld;
960 if (!tty)
961 return;
962 ld = tty_ldisc_ref(tty);
963 if (ld) {
964 if (ld->ops->receive_buf)
965 ld->ops->receive_buf(tty, data, flags, count);
966 tty_ldisc_deref(ld);
967 }
968 }
969
970 /* mgsl_stop() throttle (stop) transmitter
971 *
972 * Arguments: tty pointer to tty info structure
973 * Return Value: None
974 */
975 static void mgsl_stop(struct tty_struct *tty)
976 {
977 struct mgsl_struct *info = tty->driver_data;
978 unsigned long flags;
979
980 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
981 return;
982
983 if ( debug_level >= DEBUG_LEVEL_INFO )
984 printk("mgsl_stop(%s)\n",info->device_name);
985
986 spin_lock_irqsave(&info->irq_spinlock,flags);
987 if (info->tx_enabled)
988 usc_stop_transmitter(info);
989 spin_unlock_irqrestore(&info->irq_spinlock,flags);
990
991 } /* end of mgsl_stop() */
992
993 /* mgsl_start() release (start) transmitter
994 *
995 * Arguments: tty pointer to tty info structure
996 * Return Value: None
997 */
998 static void mgsl_start(struct tty_struct *tty)
999 {
1000 struct mgsl_struct *info = tty->driver_data;
1001 unsigned long flags;
1002
1003 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004 return;
1005
1006 if ( debug_level >= DEBUG_LEVEL_INFO )
1007 printk("mgsl_start(%s)\n",info->device_name);
1008
1009 spin_lock_irqsave(&info->irq_spinlock,flags);
1010 if (!info->tx_enabled)
1011 usc_start_transmitter(info);
1012 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013
1014 } /* end of mgsl_start() */
1015
1016 /*
1017 * Bottom half work queue access functions
1018 */
1019
1020 /* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1022 */
1023 static int mgsl_bh_action(struct mgsl_struct *info)
1024 {
1025 unsigned long flags;
1026 int rc = 0;
1027
1028 spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030 if (info->pending_bh & BH_RECEIVE) {
1031 info->pending_bh &= ~BH_RECEIVE;
1032 rc = BH_RECEIVE;
1033 } else if (info->pending_bh & BH_TRANSMIT) {
1034 info->pending_bh &= ~BH_TRANSMIT;
1035 rc = BH_TRANSMIT;
1036 } else if (info->pending_bh & BH_STATUS) {
1037 info->pending_bh &= ~BH_STATUS;
1038 rc = BH_STATUS;
1039 }
1040
1041 if (!rc) {
1042 /* Mark BH routine as complete */
1043 info->bh_running = false;
1044 info->bh_requested = false;
1045 }
1046
1047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048
1049 return rc;
1050 }
1051
1052 /*
1053 * Perform bottom half processing of work items queued by ISR.
1054 */
1055 static void mgsl_bh_handler(struct work_struct *work)
1056 {
1057 struct mgsl_struct *info =
1058 container_of(work, struct mgsl_struct, task);
1059 int action;
1060
1061 if ( debug_level >= DEBUG_LEVEL_BH )
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__,__LINE__,info->device_name);
1064
1065 info->bh_running = true;
1066
1067 while((action = mgsl_bh_action(info)) != 0) {
1068
1069 /* Process work item */
1070 if ( debug_level >= DEBUG_LEVEL_BH )
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__,__LINE__,action);
1073
1074 switch (action) {
1075
1076 case BH_RECEIVE:
1077 mgsl_bh_receive(info);
1078 break;
1079 case BH_TRANSMIT:
1080 mgsl_bh_transmit(info);
1081 break;
1082 case BH_STATUS:
1083 mgsl_bh_status(info);
1084 break;
1085 default:
1086 /* unknown work item ID */
1087 printk("Unknown work item ID=%08X!\n", action);
1088 break;
1089 }
1090 }
1091
1092 if ( debug_level >= DEBUG_LEVEL_BH )
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__,__LINE__,info->device_name);
1095 }
1096
1097 static void mgsl_bh_receive(struct mgsl_struct *info)
1098 {
1099 bool (*get_rx_frame)(struct mgsl_struct *info) =
1100 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1101
1102 if ( debug_level >= DEBUG_LEVEL_BH )
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__,__LINE__,info->device_name);
1105
1106 do
1107 {
1108 if (info->rx_rcc_underrun) {
1109 unsigned long flags;
1110 spin_lock_irqsave(&info->irq_spinlock,flags);
1111 usc_start_receiver(info);
1112 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1113 return;
1114 }
1115 } while(get_rx_frame(info));
1116 }
1117
1118 static void mgsl_bh_transmit(struct mgsl_struct *info)
1119 {
1120 struct tty_struct *tty = info->port.tty;
1121 unsigned long flags;
1122
1123 if ( debug_level >= DEBUG_LEVEL_BH )
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__,__LINE__,info->device_name);
1126
1127 if (tty)
1128 tty_wakeup(tty);
1129
1130 /* if transmitter idle and loopmode_send_done_requested
1131 * then start echoing RxD to TxD
1132 */
1133 spin_lock_irqsave(&info->irq_spinlock,flags);
1134 if ( !info->tx_active && info->loopmode_send_done_requested )
1135 usc_loopmode_send_done( info );
1136 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1137 }
1138
1139 static void mgsl_bh_status(struct mgsl_struct *info)
1140 {
1141 if ( debug_level >= DEBUG_LEVEL_BH )
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__,__LINE__,info->device_name);
1144
1145 info->ri_chkcount = 0;
1146 info->dsr_chkcount = 0;
1147 info->dcd_chkcount = 0;
1148 info->cts_chkcount = 0;
1149 }
1150
1151 /* mgsl_isr_receive_status()
1152 *
1153 * Service a receive status interrupt. The type of status
1154 * interrupt is indicated by the state of the RCSR.
1155 * This is only used for HDLC mode.
1156 *
1157 * Arguments: info pointer to device instance data
1158 * Return Value: None
1159 */
1160 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1161 {
1162 u16 status = usc_InReg( info, RCSR );
1163
1164 if ( debug_level >= DEBUG_LEVEL_ISR )
1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__,__LINE__,status);
1167
1168 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1169 info->loopmode_insert_requested &&
1170 usc_loopmode_active(info) )
1171 {
1172 ++info->icount.rxabort;
1173 info->loopmode_insert_requested = false;
1174
1175 /* clear CMR:13 to start echoing RxD to TxD */
1176 info->cmr_value &= ~BIT13;
1177 usc_OutReg(info, CMR, info->cmr_value);
1178
1179 /* disable received abort irq (no longer required) */
1180 usc_OutReg(info, RICR,
1181 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1182 }
1183
1184 if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
1185 if (status & RXSTATUS_EXITED_HUNT)
1186 info->icount.exithunt++;
1187 if (status & RXSTATUS_IDLE_RECEIVED)
1188 info->icount.rxidle++;
1189 wake_up_interruptible(&info->event_wait_q);
1190 }
1191
1192 if (status & RXSTATUS_OVERRUN){
1193 info->icount.rxover++;
1194 usc_process_rxoverrun_sync( info );
1195 }
1196
1197 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1198 usc_UnlatchRxstatusBits( info, status );
1199
1200 } /* end of mgsl_isr_receive_status() */
1201
1202 /* mgsl_isr_transmit_status()
1203 *
1204 * Service a transmit status interrupt
1205 * HDLC mode :end of transmit frame
1206 * Async mode:all data is sent
1207 * transmit status is indicated by bits in the TCSR.
1208 *
1209 * Arguments: info pointer to device instance data
1210 * Return Value: None
1211 */
1212 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1213 {
1214 u16 status = usc_InReg( info, TCSR );
1215
1216 if ( debug_level >= DEBUG_LEVEL_ISR )
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__,__LINE__,status);
1219
1220 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1221 usc_UnlatchTxstatusBits( info, status );
1222
1223 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1224 {
1225 /* finished sending HDLC abort. This may leave */
1226 /* the TxFifo with data from the aborted frame */
1227 /* so purge the TxFifo. Also shutdown the DMA */
1228 /* channel in case there is data remaining in */
1229 /* the DMA buffer */
1230 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1231 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1232 }
1233
1234 if ( status & TXSTATUS_EOF_SENT )
1235 info->icount.txok++;
1236 else if ( status & TXSTATUS_UNDERRUN )
1237 info->icount.txunder++;
1238 else if ( status & TXSTATUS_ABORT_SENT )
1239 info->icount.txabort++;
1240 else
1241 info->icount.txunder++;
1242
1243 info->tx_active = false;
1244 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1245 del_timer(&info->tx_timer);
1246
1247 if ( info->drop_rts_on_tx_done ) {
1248 usc_get_serial_signals( info );
1249 if ( info->serial_signals & SerialSignal_RTS ) {
1250 info->serial_signals &= ~SerialSignal_RTS;
1251 usc_set_serial_signals( info );
1252 }
1253 info->drop_rts_on_tx_done = false;
1254 }
1255
1256 #if SYNCLINK_GENERIC_HDLC
1257 if (info->netcount)
1258 hdlcdev_tx_done(info);
1259 else
1260 #endif
1261 {
1262 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1263 usc_stop_transmitter(info);
1264 return;
1265 }
1266 info->pending_bh |= BH_TRANSMIT;
1267 }
1268
1269 } /* end of mgsl_isr_transmit_status() */
1270
1271 /* mgsl_isr_io_pin()
1272 *
1273 * Service an Input/Output pin interrupt. The type of
1274 * interrupt is indicated by bits in the MISR
1275 *
1276 * Arguments: info pointer to device instance data
1277 * Return Value: None
1278 */
1279 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1280 {
1281 struct mgsl_icount *icount;
1282 u16 status = usc_InReg( info, MISR );
1283
1284 if ( debug_level >= DEBUG_LEVEL_ISR )
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__,__LINE__,status);
1287
1288 usc_ClearIrqPendingBits( info, IO_PIN );
1289 usc_UnlatchIostatusBits( info, status );
1290
1291 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1292 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1293 icount = &info->icount;
1294 /* update input line counters */
1295 if (status & MISCSTATUS_RI_LATCHED) {
1296 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1297 usc_DisablestatusIrqs(info,SICR_RI);
1298 icount->rng++;
1299 if ( status & MISCSTATUS_RI )
1300 info->input_signal_events.ri_up++;
1301 else
1302 info->input_signal_events.ri_down++;
1303 }
1304 if (status & MISCSTATUS_DSR_LATCHED) {
1305 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306 usc_DisablestatusIrqs(info,SICR_DSR);
1307 icount->dsr++;
1308 if ( status & MISCSTATUS_DSR )
1309 info->input_signal_events.dsr_up++;
1310 else
1311 info->input_signal_events.dsr_down++;
1312 }
1313 if (status & MISCSTATUS_DCD_LATCHED) {
1314 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315 usc_DisablestatusIrqs(info,SICR_DCD);
1316 icount->dcd++;
1317 if (status & MISCSTATUS_DCD) {
1318 info->input_signal_events.dcd_up++;
1319 } else
1320 info->input_signal_events.dcd_down++;
1321 #if SYNCLINK_GENERIC_HDLC
1322 if (info->netcount) {
1323 if (status & MISCSTATUS_DCD)
1324 netif_carrier_on(info->netdev);
1325 else
1326 netif_carrier_off(info->netdev);
1327 }
1328 #endif
1329 }
1330 if (status & MISCSTATUS_CTS_LATCHED)
1331 {
1332 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1333 usc_DisablestatusIrqs(info,SICR_CTS);
1334 icount->cts++;
1335 if ( status & MISCSTATUS_CTS )
1336 info->input_signal_events.cts_up++;
1337 else
1338 info->input_signal_events.cts_down++;
1339 }
1340 wake_up_interruptible(&info->status_event_wait_q);
1341 wake_up_interruptible(&info->event_wait_q);
1342
1343 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1344 (status & MISCSTATUS_DCD_LATCHED) ) {
1345 if ( debug_level >= DEBUG_LEVEL_ISR )
1346 printk("%s CD now %s...", info->device_name,
1347 (status & MISCSTATUS_DCD) ? "on" : "off");
1348 if (status & MISCSTATUS_DCD)
1349 wake_up_interruptible(&info->port.open_wait);
1350 else {
1351 if ( debug_level >= DEBUG_LEVEL_ISR )
1352 printk("doing serial hangup...");
1353 if (info->port.tty)
1354 tty_hangup(info->port.tty);
1355 }
1356 }
1357
1358 if (tty_port_cts_enabled(&info->port) &&
1359 (status & MISCSTATUS_CTS_LATCHED) ) {
1360 if (info->port.tty->hw_stopped) {
1361 if (status & MISCSTATUS_CTS) {
1362 if ( debug_level >= DEBUG_LEVEL_ISR )
1363 printk("CTS tx start...");
1364 if (info->port.tty)
1365 info->port.tty->hw_stopped = 0;
1366 usc_start_transmitter(info);
1367 info->pending_bh |= BH_TRANSMIT;
1368 return;
1369 }
1370 } else {
1371 if (!(status & MISCSTATUS_CTS)) {
1372 if ( debug_level >= DEBUG_LEVEL_ISR )
1373 printk("CTS tx stop...");
1374 if (info->port.tty)
1375 info->port.tty->hw_stopped = 1;
1376 usc_stop_transmitter(info);
1377 }
1378 }
1379 }
1380 }
1381
1382 info->pending_bh |= BH_STATUS;
1383
1384 /* for diagnostics set IRQ flag */
1385 if ( status & MISCSTATUS_TXC_LATCHED ){
1386 usc_OutReg( info, SICR,
1387 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1388 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1389 info->irq_occurred = true;
1390 }
1391
1392 } /* end of mgsl_isr_io_pin() */
1393
1394 /* mgsl_isr_transmit_data()
1395 *
1396 * Service a transmit data interrupt (async mode only).
1397 *
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1400 */
1401 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1402 {
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__,__LINE__,info->xmit_cnt);
1406
1407 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1408
1409 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1410 usc_stop_transmitter(info);
1411 return;
1412 }
1413
1414 if ( info->xmit_cnt )
1415 usc_load_txfifo( info );
1416 else
1417 info->tx_active = false;
1418
1419 if (info->xmit_cnt < WAKEUP_CHARS)
1420 info->pending_bh |= BH_TRANSMIT;
1421
1422 } /* end of mgsl_isr_transmit_data() */
1423
1424 /* mgsl_isr_receive_data()
1425 *
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1429 *
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1432 */
1433 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1434 {
1435 int Fifocount;
1436 u16 status;
1437 int work = 0;
1438 unsigned char DataByte;
1439 struct mgsl_icount *icount = &info->icount;
1440
1441 if ( debug_level >= DEBUG_LEVEL_ISR )
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1443 __FILE__,__LINE__);
1444
1445 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1446
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1449
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1453
1454 /* flush the receive FIFO */
1455
1456 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1457 int flag;
1458
1459 /* read one byte from RxFIFO */
1460 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1461 info->io_base + CCAR );
1462 DataByte = inb( info->io_base + CCAR );
1463
1464 /* get the status of the received byte */
1465 status = usc_InReg(info, RCSR);
1466 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1467 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
1468 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1469
1470 icount->rx++;
1471
1472 flag = 0;
1473 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1474 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
1475 printk("rxerr=%04X\n",status);
1476 /* update error statistics */
1477 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1478 status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
1479 icount->brk++;
1480 } else if (status & RXSTATUS_PARITY_ERROR)
1481 icount->parity++;
1482 else if (status & RXSTATUS_FRAMING_ERROR)
1483 icount->frame++;
1484 else if (status & RXSTATUS_OVERRUN) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1488 icount->overrun++;
1489 }
1490
1491 /* discard char if tty control flags say so */
1492 if (status & info->ignore_status_mask)
1493 continue;
1494
1495 status &= info->read_status_mask;
1496
1497 if (status & RXSTATUS_BREAK_RECEIVED) {
1498 flag = TTY_BREAK;
1499 if (info->port.flags & ASYNC_SAK)
1500 do_SAK(info->port.tty);
1501 } else if (status & RXSTATUS_PARITY_ERROR)
1502 flag = TTY_PARITY;
1503 else if (status & RXSTATUS_FRAMING_ERROR)
1504 flag = TTY_FRAME;
1505 } /* end of if (error) */
1506 tty_insert_flip_char(&info->port, DataByte, flag);
1507 if (status & RXSTATUS_OVERRUN) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1511 */
1512 work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1513 }
1514 }
1515
1516 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__,__LINE__,icount->rx,icount->brk,
1519 icount->parity,icount->frame,icount->overrun);
1520 }
1521
1522 if(work)
1523 tty_flip_buffer_push(&info->port);
1524 }
1525
1526 /* mgsl_isr_misc()
1527 *
1528 * Service a miscellaneous interrupt source.
1529 *
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1532 */
1533 static void mgsl_isr_misc( struct mgsl_struct *info )
1534 {
1535 u16 status = usc_InReg( info, MISR );
1536
1537 if ( debug_level >= DEBUG_LEVEL_ISR )
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__,__LINE__,status);
1540
1541 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1542 (info->params.mode == MGSL_MODE_HDLC)) {
1543
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1546 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1547 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1548 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1549 usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
1550
1551 /* schedule BH handler to restart receiver */
1552 info->pending_bh |= BH_RECEIVE;
1553 info->rx_rcc_underrun = true;
1554 }
1555
1556 usc_ClearIrqPendingBits( info, MISC );
1557 usc_UnlatchMiscstatusBits( info, status );
1558
1559 } /* end of mgsl_isr_misc() */
1560
1561 /* mgsl_isr_null()
1562 *
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1565 *
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1568 */
1569 static void mgsl_isr_null( struct mgsl_struct *info )
1570 {
1571
1572 } /* end of mgsl_isr_null() */
1573
1574 /* mgsl_isr_receive_dma()
1575 *
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1579 *
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1583 *
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1589 *
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1592 */
1593 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1594 {
1595 u16 status;
1596
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
1599
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status = usc_InDmaReg( info, RDMR );
1603
1604 if ( debug_level >= DEBUG_LEVEL_ISR )
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__,__LINE__,info->device_name,status);
1607
1608 info->pending_bh |= BH_RECEIVE;
1609
1610 if ( status & BIT3 ) {
1611 info->rx_overflow = true;
1612 info->icount.buf_overrun++;
1613 }
1614
1615 } /* end of mgsl_isr_receive_dma() */
1616
1617 /* mgsl_isr_transmit_dma()
1618 *
1619 * This function services a transmit DMA channel interrupt.
1620 *
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1623 *
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1626 *
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1633 *
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1636 */
1637 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1638 {
1639 u16 status;
1640
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
1643
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1646
1647 status = usc_InDmaReg( info, TDMR );
1648
1649 if ( debug_level >= DEBUG_LEVEL_ISR )
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__,__LINE__,info->device_name,status);
1652
1653 if ( status & BIT2 ) {
1654 --info->tx_dma_buffers_used;
1655
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1658 */
1659 if ( load_next_tx_holding_buffer(info) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1662 */
1663 info->pending_bh |= BH_TRANSMIT;
1664 }
1665 }
1666
1667 } /* end of mgsl_isr_transmit_dma() */
1668
1669 /* mgsl_interrupt()
1670 *
1671 * Interrupt service routine entry point.
1672 *
1673 * Arguments:
1674 *
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1677 *
1678 * Return Value: None
1679 */
1680 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1681 {
1682 struct mgsl_struct *info = dev_id;
1683 u16 UscVector;
1684 u16 DmaVector;
1685
1686 if ( debug_level >= DEBUG_LEVEL_ISR )
1687 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__, __LINE__, info->irq_level);
1689
1690 spin_lock(&info->irq_spinlock);
1691
1692 for(;;) {
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector = usc_InReg(info, IVR) >> 9;
1695 DmaVector = usc_InDmaReg(info, DIVR);
1696
1697 if ( debug_level >= DEBUG_LEVEL_ISR )
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1700
1701 if ( !UscVector && !DmaVector )
1702 break;
1703
1704 /* Dispatch interrupt vector */
1705 if ( UscVector )
1706 (*UscIsrTable[UscVector])(info);
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1708 mgsl_isr_transmit_dma(info);
1709 else
1710 mgsl_isr_receive_dma(info);
1711
1712 if ( info->isr_overflow ) {
1713 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__, __LINE__, info->device_name, info->irq_level);
1715 usc_DisableMasterIrqBit(info);
1716 usc_DisableDmaInterrupts(info,DICR_MASTER);
1717 break;
1718 }
1719 }
1720
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1723 */
1724
1725 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1726 if ( debug_level >= DEBUG_LEVEL_ISR )
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__,__LINE__,info->device_name);
1729 schedule_work(&info->task);
1730 info->bh_requested = true;
1731 }
1732
1733 spin_unlock(&info->irq_spinlock);
1734
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
1736 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__, __LINE__, info->irq_level);
1738
1739 return IRQ_HANDLED;
1740 } /* end of mgsl_interrupt() */
1741
1742 /* startup()
1743 *
1744 * Initialize and start device.
1745 *
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1748 */
1749 static int startup(struct mgsl_struct * info)
1750 {
1751 int retval = 0;
1752
1753 if ( debug_level >= DEBUG_LEVEL_INFO )
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1755
1756 if (info->port.flags & ASYNC_INITIALIZED)
1757 return 0;
1758
1759 if (!info->xmit_buf) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1762 if (!info->xmit_buf) {
1763 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__,__LINE__,info->device_name);
1765 return -ENOMEM;
1766 }
1767 }
1768
1769 info->pending_bh = 0;
1770
1771 memset(&info->icount, 0, sizeof(info->icount));
1772
1773 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1774
1775 /* Allocate and claim adapter resources */
1776 retval = mgsl_claim_resources(info);
1777
1778 /* perform existence check and diagnostics */
1779 if ( !retval )
1780 retval = mgsl_adapter_test(info);
1781
1782 if ( retval ) {
1783 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1784 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1785 mgsl_release_resources(info);
1786 return retval;
1787 }
1788
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info);
1791
1792 if (info->port.tty)
1793 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1794
1795 info->port.flags |= ASYNC_INITIALIZED;
1796
1797 return 0;
1798
1799 } /* end of startup() */
1800
1801 /* shutdown()
1802 *
1803 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1804 *
1805 * Arguments: info pointer to device instance data
1806 * Return Value: None
1807 */
1808 static void shutdown(struct mgsl_struct * info)
1809 {
1810 unsigned long flags;
1811
1812 if (!(info->port.flags & ASYNC_INITIALIZED))
1813 return;
1814
1815 if (debug_level >= DEBUG_LEVEL_INFO)
1816 printk("%s(%d):mgsl_shutdown(%s)\n",
1817 __FILE__,__LINE__, info->device_name );
1818
1819 /* clear status wait queue because status changes */
1820 /* can't happen after shutting down the hardware */
1821 wake_up_interruptible(&info->status_event_wait_q);
1822 wake_up_interruptible(&info->event_wait_q);
1823
1824 del_timer_sync(&info->tx_timer);
1825
1826 if (info->xmit_buf) {
1827 free_page((unsigned long) info->xmit_buf);
1828 info->xmit_buf = NULL;
1829 }
1830
1831 spin_lock_irqsave(&info->irq_spinlock,flags);
1832 usc_DisableMasterIrqBit(info);
1833 usc_stop_receiver(info);
1834 usc_stop_transmitter(info);
1835 usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
1836 TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
1837 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1838
1839 /* Disable DMAEN (Port 7, Bit 14) */
1840 /* This disconnects the DMA request signal from the ISA bus */
1841 /* on the ISA adapter. This has no effect for the PCI adapter */
1842 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1843
1844 /* Disable INTEN (Port 6, Bit12) */
1845 /* This disconnects the IRQ request signal to the ISA bus */
1846 /* on the ISA adapter. This has no effect for the PCI adapter */
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1848
1849 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1850 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1851 usc_set_serial_signals(info);
1852 }
1853
1854 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1855
1856 mgsl_release_resources(info);
1857
1858 if (info->port.tty)
1859 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1860
1861 info->port.flags &= ~ASYNC_INITIALIZED;
1862
1863 } /* end of shutdown() */
1864
1865 static void mgsl_program_hw(struct mgsl_struct *info)
1866 {
1867 unsigned long flags;
1868
1869 spin_lock_irqsave(&info->irq_spinlock,flags);
1870
1871 usc_stop_receiver(info);
1872 usc_stop_transmitter(info);
1873 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1874
1875 if (info->params.mode == MGSL_MODE_HDLC ||
1876 info->params.mode == MGSL_MODE_RAW ||
1877 info->netcount)
1878 usc_set_sync_mode(info);
1879 else
1880 usc_set_async_mode(info);
1881
1882 usc_set_serial_signals(info);
1883
1884 info->dcd_chkcount = 0;
1885 info->cts_chkcount = 0;
1886 info->ri_chkcount = 0;
1887 info->dsr_chkcount = 0;
1888
1889 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1890 usc_EnableInterrupts(info, IO_PIN);
1891 usc_get_serial_signals(info);
1892
1893 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1894 usc_start_receiver(info);
1895
1896 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1897 }
1898
1899 /* Reconfigure adapter based on new parameters
1900 */
1901 static void mgsl_change_params(struct mgsl_struct *info)
1902 {
1903 unsigned cflag;
1904 int bits_per_char;
1905
1906 if (!info->port.tty)
1907 return;
1908
1909 if (debug_level >= DEBUG_LEVEL_INFO)
1910 printk("%s(%d):mgsl_change_params(%s)\n",
1911 __FILE__,__LINE__, info->device_name );
1912
1913 cflag = info->port.tty->termios.c_cflag;
1914
1915 /* if B0 rate (hangup) specified then negate RTS and DTR */
1916 /* otherwise assert RTS and DTR */
1917 if (cflag & CBAUD)
1918 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1919 else
1920 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1921
1922 /* byte size and parity */
1923
1924 switch (cflag & CSIZE) {
1925 case CS5: info->params.data_bits = 5; break;
1926 case CS6: info->params.data_bits = 6; break;
1927 case CS7: info->params.data_bits = 7; break;
1928 case CS8: info->params.data_bits = 8; break;
1929 /* Never happens, but GCC is too dumb to figure it out */
1930 default: info->params.data_bits = 7; break;
1931 }
1932
1933 if (cflag & CSTOPB)
1934 info->params.stop_bits = 2;
1935 else
1936 info->params.stop_bits = 1;
1937
1938 info->params.parity = ASYNC_PARITY_NONE;
1939 if (cflag & PARENB) {
1940 if (cflag & PARODD)
1941 info->params.parity = ASYNC_PARITY_ODD;
1942 else
1943 info->params.parity = ASYNC_PARITY_EVEN;
1944 #ifdef CMSPAR
1945 if (cflag & CMSPAR)
1946 info->params.parity = ASYNC_PARITY_SPACE;
1947 #endif
1948 }
1949
1950 /* calculate number of jiffies to transmit a full
1951 * FIFO (32 bytes) at specified data rate
1952 */
1953 bits_per_char = info->params.data_bits +
1954 info->params.stop_bits + 1;
1955
1956 /* if port data rate is set to 460800 or less then
1957 * allow tty settings to override, otherwise keep the
1958 * current data rate.
1959 */
1960 if (info->params.data_rate <= 460800)
1961 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1962
1963 if ( info->params.data_rate ) {
1964 info->timeout = (32*HZ*bits_per_char) /
1965 info->params.data_rate;
1966 }
1967 info->timeout += HZ/50; /* Add .02 seconds of slop */
1968
1969 if (cflag & CRTSCTS)
1970 info->port.flags |= ASYNC_CTS_FLOW;
1971 else
1972 info->port.flags &= ~ASYNC_CTS_FLOW;
1973
1974 if (cflag & CLOCAL)
1975 info->port.flags &= ~ASYNC_CHECK_CD;
1976 else
1977 info->port.flags |= ASYNC_CHECK_CD;
1978
1979 /* process tty input control flags */
1980
1981 info->read_status_mask = RXSTATUS_OVERRUN;
1982 if (I_INPCK(info->port.tty))
1983 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1984 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1985 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1986
1987 if (I_IGNPAR(info->port.tty))
1988 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1989 if (I_IGNBRK(info->port.tty)) {
1990 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991 /* If ignoring parity and break indicators, ignore
1992 * overruns too. (For real raw support).
1993 */
1994 if (I_IGNPAR(info->port.tty))
1995 info->ignore_status_mask |= RXSTATUS_OVERRUN;
1996 }
1997
1998 mgsl_program_hw(info);
1999
2000 } /* end of mgsl_change_params() */
2001
2002 /* mgsl_put_char()
2003 *
2004 * Add a character to the transmit buffer.
2005 *
2006 * Arguments: tty pointer to tty information structure
2007 * ch character to add to transmit buffer
2008 *
2009 * Return Value: None
2010 */
2011 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2012 {
2013 struct mgsl_struct *info = tty->driver_data;
2014 unsigned long flags;
2015 int ret = 0;
2016
2017 if (debug_level >= DEBUG_LEVEL_INFO) {
2018 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2019 __FILE__, __LINE__, ch, info->device_name);
2020 }
2021
2022 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2023 return 0;
2024
2025 if (!info->xmit_buf)
2026 return 0;
2027
2028 spin_lock_irqsave(&info->irq_spinlock, flags);
2029
2030 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2031 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2032 info->xmit_buf[info->xmit_head++] = ch;
2033 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2034 info->xmit_cnt++;
2035 ret = 1;
2036 }
2037 }
2038 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2039 return ret;
2040
2041 } /* end of mgsl_put_char() */
2042
2043 /* mgsl_flush_chars()
2044 *
2045 * Enable transmitter so remaining characters in the
2046 * transmit buffer are sent.
2047 *
2048 * Arguments: tty pointer to tty information structure
2049 * Return Value: None
2050 */
2051 static void mgsl_flush_chars(struct tty_struct *tty)
2052 {
2053 struct mgsl_struct *info = tty->driver_data;
2054 unsigned long flags;
2055
2056 if ( debug_level >= DEBUG_LEVEL_INFO )
2057 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2058 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2059
2060 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2061 return;
2062
2063 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2064 !info->xmit_buf)
2065 return;
2066
2067 if ( debug_level >= DEBUG_LEVEL_INFO )
2068 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2069 __FILE__,__LINE__,info->device_name );
2070
2071 spin_lock_irqsave(&info->irq_spinlock,flags);
2072
2073 if (!info->tx_active) {
2074 if ( (info->params.mode == MGSL_MODE_HDLC ||
2075 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2076 /* operating in synchronous (frame oriented) mode */
2077 /* copy data from circular xmit_buf to */
2078 /* transmit DMA buffer. */
2079 mgsl_load_tx_dma_buffer(info,
2080 info->xmit_buf,info->xmit_cnt);
2081 }
2082 usc_start_transmitter(info);
2083 }
2084
2085 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086
2087 } /* end of mgsl_flush_chars() */
2088
2089 /* mgsl_write()
2090 *
2091 * Send a block of data
2092 *
2093 * Arguments:
2094 *
2095 * tty pointer to tty information structure
2096 * buf pointer to buffer containing send data
2097 * count size of send data in bytes
2098 *
2099 * Return Value: number of characters written
2100 */
2101 static int mgsl_write(struct tty_struct * tty,
2102 const unsigned char *buf, int count)
2103 {
2104 int c, ret = 0;
2105 struct mgsl_struct *info = tty->driver_data;
2106 unsigned long flags;
2107
2108 if ( debug_level >= DEBUG_LEVEL_INFO )
2109 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2110 __FILE__,__LINE__,info->device_name,count);
2111
2112 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2113 goto cleanup;
2114
2115 if (!info->xmit_buf)
2116 goto cleanup;
2117
2118 if ( info->params.mode == MGSL_MODE_HDLC ||
2119 info->params.mode == MGSL_MODE_RAW ) {
2120 /* operating in synchronous (frame oriented) mode */
2121 if (info->tx_active) {
2122
2123 if ( info->params.mode == MGSL_MODE_HDLC ) {
2124 ret = 0;
2125 goto cleanup;
2126 }
2127 /* transmitter is actively sending data -
2128 * if we have multiple transmit dma and
2129 * holding buffers, attempt to queue this
2130 * frame for transmission at a later time.
2131 */
2132 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2133 /* no tx holding buffers available */
2134 ret = 0;
2135 goto cleanup;
2136 }
2137
2138 /* queue transmit frame request */
2139 ret = count;
2140 save_tx_buffer_request(info,buf,count);
2141
2142 /* if we have sufficient tx dma buffers,
2143 * load the next buffered tx request
2144 */
2145 spin_lock_irqsave(&info->irq_spinlock,flags);
2146 load_next_tx_holding_buffer(info);
2147 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2148 goto cleanup;
2149 }
2150
2151 /* if operating in HDLC LoopMode and the adapter */
2152 /* has yet to be inserted into the loop, we can't */
2153 /* transmit */
2154
2155 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2156 !usc_loopmode_active(info) )
2157 {
2158 ret = 0;
2159 goto cleanup;
2160 }
2161
2162 if ( info->xmit_cnt ) {
2163 /* Send accumulated from send_char() calls */
2164 /* as frame and wait before accepting more data. */
2165 ret = 0;
2166
2167 /* copy data from circular xmit_buf to */
2168 /* transmit DMA buffer. */
2169 mgsl_load_tx_dma_buffer(info,
2170 info->xmit_buf,info->xmit_cnt);
2171 if ( debug_level >= DEBUG_LEVEL_INFO )
2172 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2173 __FILE__,__LINE__,info->device_name);
2174 } else {
2175 if ( debug_level >= DEBUG_LEVEL_INFO )
2176 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2177 __FILE__,__LINE__,info->device_name);
2178 ret = count;
2179 info->xmit_cnt = count;
2180 mgsl_load_tx_dma_buffer(info,buf,count);
2181 }
2182 } else {
2183 while (1) {
2184 spin_lock_irqsave(&info->irq_spinlock,flags);
2185 c = min_t(int, count,
2186 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2187 SERIAL_XMIT_SIZE - info->xmit_head));
2188 if (c <= 0) {
2189 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2190 break;
2191 }
2192 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2193 info->xmit_head = ((info->xmit_head + c) &
2194 (SERIAL_XMIT_SIZE-1));
2195 info->xmit_cnt += c;
2196 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197 buf += c;
2198 count -= c;
2199 ret += c;
2200 }
2201 }
2202
2203 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2204 spin_lock_irqsave(&info->irq_spinlock,flags);
2205 if (!info->tx_active)
2206 usc_start_transmitter(info);
2207 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208 }
2209 cleanup:
2210 if ( debug_level >= DEBUG_LEVEL_INFO )
2211 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2212 __FILE__,__LINE__,info->device_name,ret);
2213
2214 return ret;
2215
2216 } /* end of mgsl_write() */
2217
2218 /* mgsl_write_room()
2219 *
2220 * Return the count of free bytes in transmit buffer
2221 *
2222 * Arguments: tty pointer to tty info structure
2223 * Return Value: None
2224 */
2225 static int mgsl_write_room(struct tty_struct *tty)
2226 {
2227 struct mgsl_struct *info = tty->driver_data;
2228 int ret;
2229
2230 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2231 return 0;
2232 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2233 if (ret < 0)
2234 ret = 0;
2235
2236 if (debug_level >= DEBUG_LEVEL_INFO)
2237 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2238 __FILE__,__LINE__, info->device_name,ret );
2239
2240 if ( info->params.mode == MGSL_MODE_HDLC ||
2241 info->params.mode == MGSL_MODE_RAW ) {
2242 /* operating in synchronous (frame oriented) mode */
2243 if ( info->tx_active )
2244 return 0;
2245 else
2246 return HDLC_MAX_FRAME_SIZE;
2247 }
2248
2249 return ret;
2250
2251 } /* end of mgsl_write_room() */
2252
2253 /* mgsl_chars_in_buffer()
2254 *
2255 * Return the count of bytes in transmit buffer
2256 *
2257 * Arguments: tty pointer to tty info structure
2258 * Return Value: None
2259 */
2260 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2261 {
2262 struct mgsl_struct *info = tty->driver_data;
2263
2264 if (debug_level >= DEBUG_LEVEL_INFO)
2265 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2266 __FILE__,__LINE__, info->device_name );
2267
2268 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2269 return 0;
2270
2271 if (debug_level >= DEBUG_LEVEL_INFO)
2272 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2273 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2274
2275 if ( info->params.mode == MGSL_MODE_HDLC ||
2276 info->params.mode == MGSL_MODE_RAW ) {
2277 /* operating in synchronous (frame oriented) mode */
2278 if ( info->tx_active )
2279 return info->max_frame_size;
2280 else
2281 return 0;
2282 }
2283
2284 return info->xmit_cnt;
2285 } /* end of mgsl_chars_in_buffer() */
2286
2287 /* mgsl_flush_buffer()
2288 *
2289 * Discard all data in the send buffer
2290 *
2291 * Arguments: tty pointer to tty info structure
2292 * Return Value: None
2293 */
2294 static void mgsl_flush_buffer(struct tty_struct *tty)
2295 {
2296 struct mgsl_struct *info = tty->driver_data;
2297 unsigned long flags;
2298
2299 if (debug_level >= DEBUG_LEVEL_INFO)
2300 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2301 __FILE__,__LINE__, info->device_name );
2302
2303 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2304 return;
2305
2306 spin_lock_irqsave(&info->irq_spinlock,flags);
2307 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2308 del_timer(&info->tx_timer);
2309 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2310
2311 tty_wakeup(tty);
2312 }
2313
2314 /* mgsl_send_xchar()
2315 *
2316 * Send a high-priority XON/XOFF character
2317 *
2318 * Arguments: tty pointer to tty info structure
2319 * ch character to send
2320 * Return Value: None
2321 */
2322 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2323 {
2324 struct mgsl_struct *info = tty->driver_data;
2325 unsigned long flags;
2326
2327 if (debug_level >= DEBUG_LEVEL_INFO)
2328 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2329 __FILE__,__LINE__, info->device_name, ch );
2330
2331 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2332 return;
2333
2334 info->x_char = ch;
2335 if (ch) {
2336 /* Make sure transmit interrupts are on */
2337 spin_lock_irqsave(&info->irq_spinlock,flags);
2338 if (!info->tx_enabled)
2339 usc_start_transmitter(info);
2340 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2341 }
2342 } /* end of mgsl_send_xchar() */
2343
2344 /* mgsl_throttle()
2345 *
2346 * Signal remote device to throttle send data (our receive data)
2347 *
2348 * Arguments: tty pointer to tty info structure
2349 * Return Value: None
2350 */
2351 static void mgsl_throttle(struct tty_struct * tty)
2352 {
2353 struct mgsl_struct *info = tty->driver_data;
2354 unsigned long flags;
2355
2356 if (debug_level >= DEBUG_LEVEL_INFO)
2357 printk("%s(%d):mgsl_throttle(%s) entry\n",
2358 __FILE__,__LINE__, info->device_name );
2359
2360 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2361 return;
2362
2363 if (I_IXOFF(tty))
2364 mgsl_send_xchar(tty, STOP_CHAR(tty));
2365
2366 if (C_CRTSCTS(tty)) {
2367 spin_lock_irqsave(&info->irq_spinlock,flags);
2368 info->serial_signals &= ~SerialSignal_RTS;
2369 usc_set_serial_signals(info);
2370 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2371 }
2372 } /* end of mgsl_throttle() */
2373
2374 /* mgsl_unthrottle()
2375 *
2376 * Signal remote device to stop throttling send data (our receive data)
2377 *
2378 * Arguments: tty pointer to tty info structure
2379 * Return Value: None
2380 */
2381 static void mgsl_unthrottle(struct tty_struct * tty)
2382 {
2383 struct mgsl_struct *info = tty->driver_data;
2384 unsigned long flags;
2385
2386 if (debug_level >= DEBUG_LEVEL_INFO)
2387 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2388 __FILE__,__LINE__, info->device_name );
2389
2390 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2391 return;
2392
2393 if (I_IXOFF(tty)) {
2394 if (info->x_char)
2395 info->x_char = 0;
2396 else
2397 mgsl_send_xchar(tty, START_CHAR(tty));
2398 }
2399
2400 if (C_CRTSCTS(tty)) {
2401 spin_lock_irqsave(&info->irq_spinlock,flags);
2402 info->serial_signals |= SerialSignal_RTS;
2403 usc_set_serial_signals(info);
2404 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2405 }
2406
2407 } /* end of mgsl_unthrottle() */
2408
2409 /* mgsl_get_stats()
2410 *
2411 * get the current serial parameters information
2412 *
2413 * Arguments: info pointer to device instance data
2414 * user_icount pointer to buffer to hold returned stats
2415 *
2416 * Return Value: 0 if success, otherwise error code
2417 */
2418 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2419 {
2420 int err;
2421
2422 if (debug_level >= DEBUG_LEVEL_INFO)
2423 printk("%s(%d):mgsl_get_params(%s)\n",
2424 __FILE__,__LINE__, info->device_name);
2425
2426 if (!user_icount) {
2427 memset(&info->icount, 0, sizeof(info->icount));
2428 } else {
2429 mutex_lock(&info->port.mutex);
2430 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2431 mutex_unlock(&info->port.mutex);
2432 if (err)
2433 return -EFAULT;
2434 }
2435
2436 return 0;
2437
2438 } /* end of mgsl_get_stats() */
2439
2440 /* mgsl_get_params()
2441 *
2442 * get the current serial parameters information
2443 *
2444 * Arguments: info pointer to device instance data
2445 * user_params pointer to buffer to hold returned params
2446 *
2447 * Return Value: 0 if success, otherwise error code
2448 */
2449 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2450 {
2451 int err;
2452 if (debug_level >= DEBUG_LEVEL_INFO)
2453 printk("%s(%d):mgsl_get_params(%s)\n",
2454 __FILE__,__LINE__, info->device_name);
2455
2456 mutex_lock(&info->port.mutex);
2457 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2458 mutex_unlock(&info->port.mutex);
2459 if (err) {
2460 if ( debug_level >= DEBUG_LEVEL_INFO )
2461 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2462 __FILE__,__LINE__,info->device_name);
2463 return -EFAULT;
2464 }
2465
2466 return 0;
2467
2468 } /* end of mgsl_get_params() */
2469
2470 /* mgsl_set_params()
2471 *
2472 * set the serial parameters
2473 *
2474 * Arguments:
2475 *
2476 * info pointer to device instance data
2477 * new_params user buffer containing new serial params
2478 *
2479 * Return Value: 0 if success, otherwise error code
2480 */
2481 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2482 {
2483 unsigned long flags;
2484 MGSL_PARAMS tmp_params;
2485 int err;
2486
2487 if (debug_level >= DEBUG_LEVEL_INFO)
2488 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2489 info->device_name );
2490 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2491 if (err) {
2492 if ( debug_level >= DEBUG_LEVEL_INFO )
2493 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2494 __FILE__,__LINE__,info->device_name);
2495 return -EFAULT;
2496 }
2497
2498 mutex_lock(&info->port.mutex);
2499 spin_lock_irqsave(&info->irq_spinlock,flags);
2500 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2501 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2502
2503 mgsl_change_params(info);
2504 mutex_unlock(&info->port.mutex);
2505
2506 return 0;
2507
2508 } /* end of mgsl_set_params() */
2509
2510 /* mgsl_get_txidle()
2511 *
2512 * get the current transmit idle mode
2513 *
2514 * Arguments: info pointer to device instance data
2515 * idle_mode pointer to buffer to hold returned idle mode
2516 *
2517 * Return Value: 0 if success, otherwise error code
2518 */
2519 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2520 {
2521 int err;
2522
2523 if (debug_level >= DEBUG_LEVEL_INFO)
2524 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2525 __FILE__,__LINE__, info->device_name, info->idle_mode);
2526
2527 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2528 if (err) {
2529 if ( debug_level >= DEBUG_LEVEL_INFO )
2530 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2531 __FILE__,__LINE__,info->device_name);
2532 return -EFAULT;
2533 }
2534
2535 return 0;
2536
2537 } /* end of mgsl_get_txidle() */
2538
2539 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2540 *
2541 * Arguments: info pointer to device instance data
2542 * idle_mode new idle mode
2543 *
2544 * Return Value: 0 if success, otherwise error code
2545 */
2546 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2547 {
2548 unsigned long flags;
2549
2550 if (debug_level >= DEBUG_LEVEL_INFO)
2551 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2552 info->device_name, idle_mode );
2553
2554 spin_lock_irqsave(&info->irq_spinlock,flags);
2555 info->idle_mode = idle_mode;
2556 usc_set_txidle( info );
2557 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2558 return 0;
2559
2560 } /* end of mgsl_set_txidle() */
2561
2562 /* mgsl_txenable()
2563 *
2564 * enable or disable the transmitter
2565 *
2566 * Arguments:
2567 *
2568 * info pointer to device instance data
2569 * enable 1 = enable, 0 = disable
2570 *
2571 * Return Value: 0 if success, otherwise error code
2572 */
2573 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2574 {
2575 unsigned long flags;
2576
2577 if (debug_level >= DEBUG_LEVEL_INFO)
2578 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2579 info->device_name, enable);
2580
2581 spin_lock_irqsave(&info->irq_spinlock,flags);
2582 if ( enable ) {
2583 if ( !info->tx_enabled ) {
2584
2585 usc_start_transmitter(info);
2586 /*--------------------------------------------------
2587 * if HDLC/SDLC Loop mode, attempt to insert the
2588 * station in the 'loop' by setting CMR:13. Upon
2589 * receipt of the next GoAhead (RxAbort) sequence,
2590 * the OnLoop indicator (CCSR:7) should go active
2591 * to indicate that we are on the loop
2592 *--------------------------------------------------*/
2593 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2594 usc_loopmode_insert_request( info );
2595 }
2596 } else {
2597 if ( info->tx_enabled )
2598 usc_stop_transmitter(info);
2599 }
2600 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2601 return 0;
2602
2603 } /* end of mgsl_txenable() */
2604
2605 /* mgsl_txabort() abort send HDLC frame
2606 *
2607 * Arguments: info pointer to device instance data
2608 * Return Value: 0 if success, otherwise error code
2609 */
2610 static int mgsl_txabort(struct mgsl_struct * info)
2611 {
2612 unsigned long flags;
2613
2614 if (debug_level >= DEBUG_LEVEL_INFO)
2615 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2616 info->device_name);
2617
2618 spin_lock_irqsave(&info->irq_spinlock,flags);
2619 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2620 {
2621 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2622 usc_loopmode_cancel_transmit( info );
2623 else
2624 usc_TCmd(info,TCmd_SendAbort);
2625 }
2626 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2627 return 0;
2628
2629 } /* end of mgsl_txabort() */
2630
2631 /* mgsl_rxenable() enable or disable the receiver
2632 *
2633 * Arguments: info pointer to device instance data
2634 * enable 1 = enable, 0 = disable
2635 * Return Value: 0 if success, otherwise error code
2636 */
2637 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2638 {
2639 unsigned long flags;
2640
2641 if (debug_level >= DEBUG_LEVEL_INFO)
2642 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2643 info->device_name, enable);
2644
2645 spin_lock_irqsave(&info->irq_spinlock,flags);
2646 if ( enable ) {
2647 if ( !info->rx_enabled )
2648 usc_start_receiver(info);
2649 } else {
2650 if ( info->rx_enabled )
2651 usc_stop_receiver(info);
2652 }
2653 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2654 return 0;
2655
2656 } /* end of mgsl_rxenable() */
2657
2658 /* mgsl_wait_event() wait for specified event to occur
2659 *
2660 * Arguments: info pointer to device instance data
2661 * mask pointer to bitmask of events to wait for
2662 * Return Value: 0 if successful and bit mask updated with
2663 * of events triggerred,
2664 * otherwise error code
2665 */
2666 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2667 {
2668 unsigned long flags;
2669 int s;
2670 int rc=0;
2671 struct mgsl_icount cprev, cnow;
2672 int events;
2673 int mask;
2674 struct _input_signal_events oldsigs, newsigs;
2675 DECLARE_WAITQUEUE(wait, current);
2676
2677 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2678 if (rc) {
2679 return -EFAULT;
2680 }
2681
2682 if (debug_level >= DEBUG_LEVEL_INFO)
2683 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2684 info->device_name, mask);
2685
2686 spin_lock_irqsave(&info->irq_spinlock,flags);
2687
2688 /* return immediately if state matches requested events */
2689 usc_get_serial_signals(info);
2690 s = info->serial_signals;
2691 events = mask &
2692 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2693 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2694 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2695 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2696 if (events) {
2697 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2698 goto exit;
2699 }
2700
2701 /* save current irq counts */
2702 cprev = info->icount;
2703 oldsigs = info->input_signal_events;
2704
2705 /* enable hunt and idle irqs if needed */
2706 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2707 u16 oldreg = usc_InReg(info,RICR);
2708 u16 newreg = oldreg +
2709 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2710 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2711 if (oldreg != newreg)
2712 usc_OutReg(info, RICR, newreg);
2713 }
2714
2715 set_current_state(TASK_INTERRUPTIBLE);
2716 add_wait_queue(&info->event_wait_q, &wait);
2717
2718 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2719
2720
2721 for(;;) {
2722 schedule();
2723 if (signal_pending(current)) {
2724 rc = -ERESTARTSYS;
2725 break;
2726 }
2727
2728 /* get current irq counts */
2729 spin_lock_irqsave(&info->irq_spinlock,flags);
2730 cnow = info->icount;
2731 newsigs = info->input_signal_events;
2732 set_current_state(TASK_INTERRUPTIBLE);
2733 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2734
2735 /* if no change, wait aborted for some reason */
2736 if (newsigs.dsr_up == oldsigs.dsr_up &&
2737 newsigs.dsr_down == oldsigs.dsr_down &&
2738 newsigs.dcd_up == oldsigs.dcd_up &&
2739 newsigs.dcd_down == oldsigs.dcd_down &&
2740 newsigs.cts_up == oldsigs.cts_up &&
2741 newsigs.cts_down == oldsigs.cts_down &&
2742 newsigs.ri_up == oldsigs.ri_up &&
2743 newsigs.ri_down == oldsigs.ri_down &&
2744 cnow.exithunt == cprev.exithunt &&
2745 cnow.rxidle == cprev.rxidle) {
2746 rc = -EIO;
2747 break;
2748 }
2749
2750 events = mask &
2751 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2752 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2753 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2754 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2755 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2756 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2757 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2758 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2759 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2760 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2761 if (events)
2762 break;
2763
2764 cprev = cnow;
2765 oldsigs = newsigs;
2766 }
2767
2768 remove_wait_queue(&info->event_wait_q, &wait);
2769 set_current_state(TASK_RUNNING);
2770
2771 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2772 spin_lock_irqsave(&info->irq_spinlock,flags);
2773 if (!waitqueue_active(&info->event_wait_q)) {
2774 /* disable enable exit hunt mode/idle rcvd IRQs */
2775 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2776 ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
2777 }
2778 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2779 }
2780 exit:
2781 if ( rc == 0 )
2782 PUT_USER(rc, events, mask_ptr);
2783
2784 return rc;
2785
2786 } /* end of mgsl_wait_event() */
2787
2788 static int modem_input_wait(struct mgsl_struct *info,int arg)
2789 {
2790 unsigned long flags;
2791 int rc;
2792 struct mgsl_icount cprev, cnow;
2793 DECLARE_WAITQUEUE(wait, current);
2794
2795 /* save current irq counts */
2796 spin_lock_irqsave(&info->irq_spinlock,flags);
2797 cprev = info->icount;
2798 add_wait_queue(&info->status_event_wait_q, &wait);
2799 set_current_state(TASK_INTERRUPTIBLE);
2800 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2801
2802 for(;;) {
2803 schedule();
2804 if (signal_pending(current)) {
2805 rc = -ERESTARTSYS;
2806 break;
2807 }
2808
2809 /* get new irq counts */
2810 spin_lock_irqsave(&info->irq_spinlock,flags);
2811 cnow = info->icount;
2812 set_current_state(TASK_INTERRUPTIBLE);
2813 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2814
2815 /* if no change, wait aborted for some reason */
2816 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2817 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2818 rc = -EIO;
2819 break;
2820 }
2821
2822 /* check for change in caller specified modem input */
2823 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2824 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2825 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2826 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2827 rc = 0;
2828 break;
2829 }
2830
2831 cprev = cnow;
2832 }
2833 remove_wait_queue(&info->status_event_wait_q, &wait);
2834 set_current_state(TASK_RUNNING);
2835 return rc;
2836 }
2837
2838 /* return the state of the serial control and status signals
2839 */
2840 static int tiocmget(struct tty_struct *tty)
2841 {
2842 struct mgsl_struct *info = tty->driver_data;
2843 unsigned int result;
2844 unsigned long flags;
2845
2846 spin_lock_irqsave(&info->irq_spinlock,flags);
2847 usc_get_serial_signals(info);
2848 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2849
2850 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2851 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2852 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2853 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2854 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2855 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2856
2857 if (debug_level >= DEBUG_LEVEL_INFO)
2858 printk("%s(%d):%s tiocmget() value=%08X\n",
2859 __FILE__,__LINE__, info->device_name, result );
2860 return result;
2861 }
2862
2863 /* set modem control signals (DTR/RTS)
2864 */
2865 static int tiocmset(struct tty_struct *tty,
2866 unsigned int set, unsigned int clear)
2867 {
2868 struct mgsl_struct *info = tty->driver_data;
2869 unsigned long flags;
2870
2871 if (debug_level >= DEBUG_LEVEL_INFO)
2872 printk("%s(%d):%s tiocmset(%x,%x)\n",
2873 __FILE__,__LINE__,info->device_name, set, clear);
2874
2875 if (set & TIOCM_RTS)
2876 info->serial_signals |= SerialSignal_RTS;
2877 if (set & TIOCM_DTR)
2878 info->serial_signals |= SerialSignal_DTR;
2879 if (clear & TIOCM_RTS)
2880 info->serial_signals &= ~SerialSignal_RTS;
2881 if (clear & TIOCM_DTR)
2882 info->serial_signals &= ~SerialSignal_DTR;
2883
2884 spin_lock_irqsave(&info->irq_spinlock,flags);
2885 usc_set_serial_signals(info);
2886 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2887
2888 return 0;
2889 }
2890
2891 /* mgsl_break() Set or clear transmit break condition
2892 *
2893 * Arguments: tty pointer to tty instance data
2894 * break_state -1=set break condition, 0=clear
2895 * Return Value: error code
2896 */
2897 static int mgsl_break(struct tty_struct *tty, int break_state)
2898 {
2899 struct mgsl_struct * info = tty->driver_data;
2900 unsigned long flags;
2901
2902 if (debug_level >= DEBUG_LEVEL_INFO)
2903 printk("%s(%d):mgsl_break(%s,%d)\n",
2904 __FILE__,__LINE__, info->device_name, break_state);
2905
2906 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2907 return -EINVAL;
2908
2909 spin_lock_irqsave(&info->irq_spinlock,flags);
2910 if (break_state == -1)
2911 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2912 else
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2915 return 0;
2916
2917 } /* end of mgsl_break() */
2918
2919 /*
2920 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2921 * Return: write counters to the user passed counter struct
2922 * NB: both 1->0 and 0->1 transitions are counted except for
2923 * RI where only 0->1 is counted.
2924 */
2925 static int msgl_get_icount(struct tty_struct *tty,
2926 struct serial_icounter_struct *icount)
2927
2928 {
2929 struct mgsl_struct * info = tty->driver_data;
2930 struct mgsl_icount cnow; /* kernel counter temps */
2931 unsigned long flags;
2932
2933 spin_lock_irqsave(&info->irq_spinlock,flags);
2934 cnow = info->icount;
2935 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2936
2937 icount->cts = cnow.cts;
2938 icount->dsr = cnow.dsr;
2939 icount->rng = cnow.rng;
2940 icount->dcd = cnow.dcd;
2941 icount->rx = cnow.rx;
2942 icount->tx = cnow.tx;
2943 icount->frame = cnow.frame;
2944 icount->overrun = cnow.overrun;
2945 icount->parity = cnow.parity;
2946 icount->brk = cnow.brk;
2947 icount->buf_overrun = cnow.buf_overrun;
2948 return 0;
2949 }
2950
2951 /* mgsl_ioctl() Service an IOCTL request
2952 *
2953 * Arguments:
2954 *
2955 * tty pointer to tty instance data
2956 * cmd IOCTL command code
2957 * arg command argument/context
2958 *
2959 * Return Value: 0 if success, otherwise error code
2960 */
2961 static int mgsl_ioctl(struct tty_struct *tty,
2962 unsigned int cmd, unsigned long arg)
2963 {
2964 struct mgsl_struct * info = tty->driver_data;
2965
2966 if (debug_level >= DEBUG_LEVEL_INFO)
2967 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2968 info->device_name, cmd );
2969
2970 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2971 return -ENODEV;
2972
2973 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2974 (cmd != TIOCMIWAIT)) {
2975 if (tty->flags & (1 << TTY_IO_ERROR))
2976 return -EIO;
2977 }
2978
2979 return mgsl_ioctl_common(info, cmd, arg);
2980 }
2981
2982 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2983 {
2984 void __user *argp = (void __user *)arg;
2985
2986 switch (cmd) {
2987 case MGSL_IOCGPARAMS:
2988 return mgsl_get_params(info, argp);
2989 case MGSL_IOCSPARAMS:
2990 return mgsl_set_params(info, argp);
2991 case MGSL_IOCGTXIDLE:
2992 return mgsl_get_txidle(info, argp);
2993 case MGSL_IOCSTXIDLE:
2994 return mgsl_set_txidle(info,(int)arg);
2995 case MGSL_IOCTXENABLE:
2996 return mgsl_txenable(info,(int)arg);
2997 case MGSL_IOCRXENABLE:
2998 return mgsl_rxenable(info,(int)arg);
2999 case MGSL_IOCTXABORT:
3000 return mgsl_txabort(info);
3001 case MGSL_IOCGSTATS:
3002 return mgsl_get_stats(info, argp);
3003 case MGSL_IOCWAITEVENT:
3004 return mgsl_wait_event(info, argp);
3005 case MGSL_IOCLOOPTXDONE:
3006 return mgsl_loopmode_send_done(info);
3007 /* Wait for modem input (DCD,RI,DSR,CTS) change
3008 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3009 */
3010 case TIOCMIWAIT:
3011 return modem_input_wait(info,(int)arg);
3012
3013 default:
3014 return -ENOIOCTLCMD;
3015 }
3016 return 0;
3017 }
3018
3019 /* mgsl_set_termios()
3020 *
3021 * Set new termios settings
3022 *
3023 * Arguments:
3024 *
3025 * tty pointer to tty structure
3026 * termios pointer to buffer to hold returned old termios
3027 *
3028 * Return Value: None
3029 */
3030 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3031 {
3032 struct mgsl_struct *info = tty->driver_data;
3033 unsigned long flags;
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3037 tty->driver->name );
3038
3039 mgsl_change_params(info);
3040
3041 /* Handle transition to B0 status */
3042 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
3043 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3044 spin_lock_irqsave(&info->irq_spinlock,flags);
3045 usc_set_serial_signals(info);
3046 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3047 }
3048
3049 /* Handle transition away from B0 status */
3050 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
3051 info->serial_signals |= SerialSignal_DTR;
3052 if (!C_CRTSCTS(tty) || !test_bit(TTY_THROTTLED, &tty->flags))
3053 info->serial_signals |= SerialSignal_RTS;
3054 spin_lock_irqsave(&info->irq_spinlock,flags);
3055 usc_set_serial_signals(info);
3056 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3057 }
3058
3059 /* Handle turning off CRTSCTS */
3060 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
3061 tty->hw_stopped = 0;
3062 mgsl_start(tty);
3063 }
3064
3065 } /* end of mgsl_set_termios() */
3066
3067 /* mgsl_close()
3068 *
3069 * Called when port is closed. Wait for remaining data to be
3070 * sent. Disable port and free resources.
3071 *
3072 * Arguments:
3073 *
3074 * tty pointer to open tty structure
3075 * filp pointer to open file object
3076 *
3077 * Return Value: None
3078 */
3079 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3080 {
3081 struct mgsl_struct * info = tty->driver_data;
3082
3083 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3084 return;
3085
3086 if (debug_level >= DEBUG_LEVEL_INFO)
3087 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3088 __FILE__,__LINE__, info->device_name, info->port.count);
3089
3090 if (tty_port_close_start(&info->port, tty, filp) == 0)
3091 goto cleanup;
3092
3093 mutex_lock(&info->port.mutex);
3094 if (info->port.flags & ASYNC_INITIALIZED)
3095 mgsl_wait_until_sent(tty, info->timeout);
3096 mgsl_flush_buffer(tty);
3097 tty_ldisc_flush(tty);
3098 shutdown(info);
3099 mutex_unlock(&info->port.mutex);
3100
3101 tty_port_close_end(&info->port, tty);
3102 info->port.tty = NULL;
3103 cleanup:
3104 if (debug_level >= DEBUG_LEVEL_INFO)
3105 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3106 tty->driver->name, info->port.count);
3107
3108 } /* end of mgsl_close() */
3109
3110 /* mgsl_wait_until_sent()
3111 *
3112 * Wait until the transmitter is empty.
3113 *
3114 * Arguments:
3115 *
3116 * tty pointer to tty info structure
3117 * timeout time to wait for send completion
3118 *
3119 * Return Value: None
3120 */
3121 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3122 {
3123 struct mgsl_struct * info = tty->driver_data;
3124 unsigned long orig_jiffies, char_time;
3125
3126 if (!info )
3127 return;
3128
3129 if (debug_level >= DEBUG_LEVEL_INFO)
3130 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3131 __FILE__,__LINE__, info->device_name );
3132
3133 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3134 return;
3135
3136 if (!(info->port.flags & ASYNC_INITIALIZED))
3137 goto exit;
3138
3139 orig_jiffies = jiffies;
3140
3141 /* Set check interval to 1/5 of estimated time to
3142 * send a character, and make it at least 1. The check
3143 * interval should also be less than the timeout.
3144 * Note: use tight timings here to satisfy the NIST-PCTS.
3145 */
3146
3147 if ( info->params.data_rate ) {
3148 char_time = info->timeout/(32 * 5);
3149 if (!char_time)
3150 char_time++;
3151 } else
3152 char_time = 1;
3153
3154 if (timeout)
3155 char_time = min_t(unsigned long, char_time, timeout);
3156
3157 if ( info->params.mode == MGSL_MODE_HDLC ||
3158 info->params.mode == MGSL_MODE_RAW ) {
3159 while (info->tx_active) {
3160 msleep_interruptible(jiffies_to_msecs(char_time));
3161 if (signal_pending(current))
3162 break;
3163 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3164 break;
3165 }
3166 } else {
3167 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3168 info->tx_enabled) {
3169 msleep_interruptible(jiffies_to_msecs(char_time));
3170 if (signal_pending(current))
3171 break;
3172 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3173 break;
3174 }
3175 }
3176
3177 exit:
3178 if (debug_level >= DEBUG_LEVEL_INFO)
3179 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3180 __FILE__,__LINE__, info->device_name );
3181
3182 } /* end of mgsl_wait_until_sent() */
3183
3184 /* mgsl_hangup()
3185 *
3186 * Called by tty_hangup() when a hangup is signaled.
3187 * This is the same as to closing all open files for the port.
3188 *
3189 * Arguments: tty pointer to associated tty object
3190 * Return Value: None
3191 */
3192 static void mgsl_hangup(struct tty_struct *tty)
3193 {
3194 struct mgsl_struct * info = tty->driver_data;
3195
3196 if (debug_level >= DEBUG_LEVEL_INFO)
3197 printk("%s(%d):mgsl_hangup(%s)\n",
3198 __FILE__,__LINE__, info->device_name );
3199
3200 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3201 return;
3202
3203 mgsl_flush_buffer(tty);
3204 shutdown(info);
3205
3206 info->port.count = 0;
3207 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3208 info->port.tty = NULL;
3209
3210 wake_up_interruptible(&info->port.open_wait);
3211
3212 } /* end of mgsl_hangup() */
3213
3214 /*
3215 * carrier_raised()
3216 *
3217 * Return true if carrier is raised
3218 */
3219
3220 static int carrier_raised(struct tty_port *port)
3221 {
3222 unsigned long flags;
3223 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3224
3225 spin_lock_irqsave(&info->irq_spinlock, flags);
3226 usc_get_serial_signals(info);
3227 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3228 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3229 }
3230
3231 static void dtr_rts(struct tty_port *port, int on)
3232 {
3233 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3234 unsigned long flags;
3235
3236 spin_lock_irqsave(&info->irq_spinlock,flags);
3237 if (on)
3238 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3239 else
3240 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3241 usc_set_serial_signals(info);
3242 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3243 }
3244
3245
3246 /* block_til_ready()
3247 *
3248 * Block the current process until the specified port
3249 * is ready to be opened.
3250 *
3251 * Arguments:
3252 *
3253 * tty pointer to tty info structure
3254 * filp pointer to open file object
3255 * info pointer to device instance data
3256 *
3257 * Return Value: 0 if success, otherwise error code
3258 */
3259 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3260 struct mgsl_struct *info)
3261 {
3262 DECLARE_WAITQUEUE(wait, current);
3263 int retval;
3264 bool do_clocal = false;
3265 unsigned long flags;
3266 int dcd;
3267 struct tty_port *port = &info->port;
3268
3269 if (debug_level >= DEBUG_LEVEL_INFO)
3270 printk("%s(%d):block_til_ready on %s\n",
3271 __FILE__,__LINE__, tty->driver->name );
3272
3273 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3274 /* nonblock mode is set or port is not enabled */
3275 port->flags |= ASYNC_NORMAL_ACTIVE;
3276 return 0;
3277 }
3278
3279 if (C_CLOCAL(tty))
3280 do_clocal = true;
3281
3282 /* Wait for carrier detect and the line to become
3283 * free (i.e., not in use by the callout). While we are in
3284 * this loop, port->count is dropped by one, so that
3285 * mgsl_close() knows when to free things. We restore it upon
3286 * exit, either normal or abnormal.
3287 */
3288
3289 retval = 0;
3290 add_wait_queue(&port->open_wait, &wait);
3291
3292 if (debug_level >= DEBUG_LEVEL_INFO)
3293 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3294 __FILE__,__LINE__, tty->driver->name, port->count );
3295
3296 spin_lock_irqsave(&info->irq_spinlock, flags);
3297 port->count--;
3298 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3299 port->blocked_open++;
3300
3301 while (1) {
3302 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3303 tty_port_raise_dtr_rts(port);
3304
3305 set_current_state(TASK_INTERRUPTIBLE);
3306
3307 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3308 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3309 -EAGAIN : -ERESTARTSYS;
3310 break;
3311 }
3312
3313 dcd = tty_port_carrier_raised(&info->port);
3314 if (do_clocal || dcd)
3315 break;
3316
3317 if (signal_pending(current)) {
3318 retval = -ERESTARTSYS;
3319 break;
3320 }
3321
3322 if (debug_level >= DEBUG_LEVEL_INFO)
3323 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3324 __FILE__,__LINE__, tty->driver->name, port->count );
3325
3326 tty_unlock(tty);
3327 schedule();
3328 tty_lock(tty);
3329 }
3330
3331 set_current_state(TASK_RUNNING);
3332 remove_wait_queue(&port->open_wait, &wait);
3333
3334 /* FIXME: Racy on hangup during close wait */
3335 if (!tty_hung_up_p(filp))
3336 port->count++;
3337 port->blocked_open--;
3338
3339 if (debug_level >= DEBUG_LEVEL_INFO)
3340 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3341 __FILE__,__LINE__, tty->driver->name, port->count );
3342
3343 if (!retval)
3344 port->flags |= ASYNC_NORMAL_ACTIVE;
3345
3346 return retval;
3347
3348 } /* end of block_til_ready() */
3349
3350 static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3351 {
3352 struct mgsl_struct *info;
3353 int line = tty->index;
3354
3355 /* verify range of specified line number */
3356 if (line >= mgsl_device_count) {
3357 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3358 __FILE__, __LINE__, line);
3359 return -ENODEV;
3360 }
3361
3362 /* find the info structure for the specified line */
3363 info = mgsl_device_list;
3364 while (info && info->line != line)
3365 info = info->next_device;
3366 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3367 return -ENODEV;
3368 tty->driver_data = info;
3369
3370 return tty_port_install(&info->port, driver, tty);
3371 }
3372
3373 /* mgsl_open()
3374 *
3375 * Called when a port is opened. Init and enable port.
3376 * Perform serial-specific initialization for the tty structure.
3377 *
3378 * Arguments: tty pointer to tty info structure
3379 * filp associated file pointer
3380 *
3381 * Return Value: 0 if success, otherwise error code
3382 */
3383 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3384 {
3385 struct mgsl_struct *info = tty->driver_data;
3386 unsigned long flags;
3387 int retval;
3388
3389 info->port.tty = tty;
3390
3391 if (debug_level >= DEBUG_LEVEL_INFO)
3392 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3393 __FILE__,__LINE__,tty->driver->name, info->port.count);
3394
3395 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3396
3397 spin_lock_irqsave(&info->netlock, flags);
3398 if (info->netcount) {
3399 retval = -EBUSY;
3400 spin_unlock_irqrestore(&info->netlock, flags);
3401 goto cleanup;
3402 }
3403 info->port.count++;
3404 spin_unlock_irqrestore(&info->netlock, flags);
3405
3406 if (info->port.count == 1) {
3407 /* 1st open on this device, init hardware */
3408 retval = startup(info);
3409 if (retval < 0)
3410 goto cleanup;
3411 }
3412
3413 retval = block_til_ready(tty, filp, info);
3414 if (retval) {
3415 if (debug_level >= DEBUG_LEVEL_INFO)
3416 printk("%s(%d):block_til_ready(%s) returned %d\n",
3417 __FILE__,__LINE__, info->device_name, retval);
3418 goto cleanup;
3419 }
3420
3421 if (debug_level >= DEBUG_LEVEL_INFO)
3422 printk("%s(%d):mgsl_open(%s) success\n",
3423 __FILE__,__LINE__, info->device_name);
3424 retval = 0;
3425
3426 cleanup:
3427 if (retval) {
3428 if (tty->count == 1)
3429 info->port.tty = NULL; /* tty layer will release tty struct */
3430 if(info->port.count)
3431 info->port.count--;
3432 }
3433
3434 return retval;
3435
3436 } /* end of mgsl_open() */
3437
3438 /*
3439 * /proc fs routines....
3440 */
3441
3442 static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3443 {
3444 char stat_buf[30];
3445 unsigned long flags;
3446
3447 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3448 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3449 info->device_name, info->io_base, info->irq_level,
3450 info->phys_memory_base, info->phys_lcr_base);
3451 } else {
3452 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3453 info->device_name, info->io_base,
3454 info->irq_level, info->dma_level);
3455 }
3456
3457 /* output current serial signal states */
3458 spin_lock_irqsave(&info->irq_spinlock,flags);
3459 usc_get_serial_signals(info);
3460 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3461
3462 stat_buf[0] = 0;
3463 stat_buf[1] = 0;
3464 if (info->serial_signals & SerialSignal_RTS)
3465 strcat(stat_buf, "|RTS");
3466 if (info->serial_signals & SerialSignal_CTS)
3467 strcat(stat_buf, "|CTS");
3468 if (info->serial_signals & SerialSignal_DTR)
3469 strcat(stat_buf, "|DTR");
3470 if (info->serial_signals & SerialSignal_DSR)
3471 strcat(stat_buf, "|DSR");
3472 if (info->serial_signals & SerialSignal_DCD)
3473 strcat(stat_buf, "|CD");
3474 if (info->serial_signals & SerialSignal_RI)
3475 strcat(stat_buf, "|RI");
3476
3477 if (info->params.mode == MGSL_MODE_HDLC ||
3478 info->params.mode == MGSL_MODE_RAW ) {
3479 seq_printf(m, " HDLC txok:%d rxok:%d",
3480 info->icount.txok, info->icount.rxok);
3481 if (info->icount.txunder)
3482 seq_printf(m, " txunder:%d", info->icount.txunder);
3483 if (info->icount.txabort)
3484 seq_printf(m, " txabort:%d", info->icount.txabort);
3485 if (info->icount.rxshort)
3486 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3487 if (info->icount.rxlong)
3488 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3489 if (info->icount.rxover)
3490 seq_printf(m, " rxover:%d", info->icount.rxover);
3491 if (info->icount.rxcrc)
3492 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3493 } else {
3494 seq_printf(m, " ASYNC tx:%d rx:%d",
3495 info->icount.tx, info->icount.rx);
3496 if (info->icount.frame)
3497 seq_printf(m, " fe:%d", info->icount.frame);
3498 if (info->icount.parity)
3499 seq_printf(m, " pe:%d", info->icount.parity);
3500 if (info->icount.brk)
3501 seq_printf(m, " brk:%d", info->icount.brk);
3502 if (info->icount.overrun)
3503 seq_printf(m, " oe:%d", info->icount.overrun);
3504 }
3505
3506 /* Append serial signal status to end */
3507 seq_printf(m, " %s\n", stat_buf+1);
3508
3509 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3510 info->tx_active,info->bh_requested,info->bh_running,
3511 info->pending_bh);
3512
3513 spin_lock_irqsave(&info->irq_spinlock,flags);
3514 {
3515 u16 Tcsr = usc_InReg( info, TCSR );
3516 u16 Tdmr = usc_InDmaReg( info, TDMR );
3517 u16 Ticr = usc_InReg( info, TICR );
3518 u16 Rscr = usc_InReg( info, RCSR );
3519 u16 Rdmr = usc_InDmaReg( info, RDMR );
3520 u16 Ricr = usc_InReg( info, RICR );
3521 u16 Icr = usc_InReg( info, ICR );
3522 u16 Dccr = usc_InReg( info, DCCR );
3523 u16 Tmr = usc_InReg( info, TMR );
3524 u16 Tccr = usc_InReg( info, TCCR );
3525 u16 Ccar = inw( info->io_base + CCAR );
3526 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3527 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3528 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3529 }
3530 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3531 }
3532
3533 /* Called to print information about devices */
3534 static int mgsl_proc_show(struct seq_file *m, void *v)
3535 {
3536 struct mgsl_struct *info;
3537
3538 seq_printf(m, "synclink driver:%s\n", driver_version);
3539
3540 info = mgsl_device_list;
3541 while( info ) {
3542 line_info(m, info);
3543 info = info->next_device;
3544 }
3545 return 0;
3546 }
3547
3548 static int mgsl_proc_open(struct inode *inode, struct file *file)
3549 {
3550 return single_open(file, mgsl_proc_show, NULL);
3551 }
3552
3553 static const struct file_operations mgsl_proc_fops = {
3554 .owner = THIS_MODULE,
3555 .open = mgsl_proc_open,
3556 .read = seq_read,
3557 .llseek = seq_lseek,
3558 .release = single_release,
3559 };
3560
3561 /* mgsl_allocate_dma_buffers()
3562 *
3563 * Allocate and format DMA buffers (ISA adapter)
3564 * or format shared memory buffers (PCI adapter).
3565 *
3566 * Arguments: info pointer to device instance data
3567 * Return Value: 0 if success, otherwise error
3568 */
3569 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3570 {
3571 unsigned short BuffersPerFrame;
3572
3573 info->last_mem_alloc = 0;
3574
3575 /* Calculate the number of DMA buffers necessary to hold the */
3576 /* largest allowable frame size. Note: If the max frame size is */
3577 /* not an even multiple of the DMA buffer size then we need to */
3578 /* round the buffer count per frame up one. */
3579
3580 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3581 if ( info->max_frame_size % DMABUFFERSIZE )
3582 BuffersPerFrame++;
3583
3584 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3585 /*
3586 * The PCI adapter has 256KBytes of shared memory to use.
3587 * This is 64 PAGE_SIZE buffers.
3588 *
3589 * The first page is used for padding at this time so the
3590 * buffer list does not begin at offset 0 of the PCI
3591 * adapter's shared memory.
3592 *
3593 * The 2nd page is used for the buffer list. A 4K buffer
3594 * list can hold 128 DMA_BUFFER structures at 32 bytes
3595 * each.
3596 *
3597 * This leaves 62 4K pages.
3598 *
3599 * The next N pages are used for transmit frame(s). We
3600 * reserve enough 4K page blocks to hold the required
3601 * number of transmit dma buffers (num_tx_dma_buffers),
3602 * each of MaxFrameSize size.
3603 *
3604 * Of the remaining pages (62-N), determine how many can
3605 * be used to receive full MaxFrameSize inbound frames
3606 */
3607 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3608 info->rx_buffer_count = 62 - info->tx_buffer_count;
3609 } else {
3610 /* Calculate the number of PAGE_SIZE buffers needed for */
3611 /* receive and transmit DMA buffers. */
3612
3613
3614 /* Calculate the number of DMA buffers necessary to */
3615 /* hold 7 max size receive frames and one max size transmit frame. */
3616 /* The receive buffer count is bumped by one so we avoid an */
3617 /* End of List condition if all receive buffers are used when */
3618 /* using linked list DMA buffers. */
3619
3620 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3621 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3622
3623 /*
3624 * limit total TxBuffers & RxBuffers to 62 4K total
3625 * (ala PCI Allocation)
3626 */
3627
3628 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3629 info->rx_buffer_count = 62 - info->tx_buffer_count;
3630
3631 }
3632
3633 if ( debug_level >= DEBUG_LEVEL_INFO )
3634 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3635 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3636
3637 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3638 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3639 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3640 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3641 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3642 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3643 return -ENOMEM;
3644 }
3645
3646 mgsl_reset_rx_dma_buffers( info );
3647 mgsl_reset_tx_dma_buffers( info );
3648
3649 return 0;
3650
3651 } /* end of mgsl_allocate_dma_buffers() */
3652
3653 /*
3654 * mgsl_alloc_buffer_list_memory()
3655 *
3656 * Allocate a common DMA buffer for use as the
3657 * receive and transmit buffer lists.
3658 *
3659 * A buffer list is a set of buffer entries where each entry contains
3660 * a pointer to an actual buffer and a pointer to the next buffer entry
3661 * (plus some other info about the buffer).
3662 *
3663 * The buffer entries for a list are built to form a circular list so
3664 * that when the entire list has been traversed you start back at the
3665 * beginning.
3666 *
3667 * This function allocates memory for just the buffer entries.
3668 * The links (pointer to next entry) are filled in with the physical
3669 * address of the next entry so the adapter can navigate the list
3670 * using bus master DMA. The pointers to the actual buffers are filled
3671 * out later when the actual buffers are allocated.
3672 *
3673 * Arguments: info pointer to device instance data
3674 * Return Value: 0 if success, otherwise error
3675 */
3676 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3677 {
3678 unsigned int i;
3679
3680 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3681 /* PCI adapter uses shared memory. */
3682 info->buffer_list = info->memory_base + info->last_mem_alloc;
3683 info->buffer_list_phys = info->last_mem_alloc;
3684 info->last_mem_alloc += BUFFERLISTSIZE;
3685 } else {
3686 /* ISA adapter uses system memory. */
3687 /* The buffer lists are allocated as a common buffer that both */
3688 /* the processor and adapter can access. This allows the driver to */
3689 /* inspect portions of the buffer while other portions are being */
3690 /* updated by the adapter using Bus Master DMA. */
3691
3692 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3693 if (info->buffer_list == NULL)
3694 return -ENOMEM;
3695 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3696 }
3697
3698 /* We got the memory for the buffer entry lists. */
3699 /* Initialize the memory block to all zeros. */
3700 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3701
3702 /* Save virtual address pointers to the receive and */
3703 /* transmit buffer lists. (Receive 1st). These pointers will */
3704 /* be used by the processor to access the lists. */
3705 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3706 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3707 info->tx_buffer_list += info->rx_buffer_count;
3708
3709 /*
3710 * Build the links for the buffer entry lists such that
3711 * two circular lists are built. (Transmit and Receive).
3712 *
3713 * Note: the links are physical addresses
3714 * which are read by the adapter to determine the next
3715 * buffer entry to use.
3716 */
3717
3718 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3719 /* calculate and store physical address of this buffer entry */
3720 info->rx_buffer_list[i].phys_entry =
3721 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3722
3723 /* calculate and store physical address of */
3724 /* next entry in cirular list of entries */
3725
3726 info->rx_buffer_list[i].link = info->buffer_list_phys;
3727
3728 if ( i < info->rx_buffer_count - 1 )
3729 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3730 }
3731
3732 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3733 /* calculate and store physical address of this buffer entry */
3734 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3735 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3736
3737 /* calculate and store physical address of */
3738 /* next entry in cirular list of entries */
3739
3740 info->tx_buffer_list[i].link = info->buffer_list_phys +
3741 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3742
3743 if ( i < info->tx_buffer_count - 1 )
3744 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3745 }
3746
3747 return 0;
3748
3749 } /* end of mgsl_alloc_buffer_list_memory() */
3750
3751 /* Free DMA buffers allocated for use as the
3752 * receive and transmit buffer lists.
3753 * Warning:
3754 *
3755 * The data transfer buffers associated with the buffer list
3756 * MUST be freed before freeing the buffer list itself because
3757 * the buffer list contains the information necessary to free
3758 * the individual buffers!
3759 */
3760 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3761 {
3762 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3763 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3764
3765 info->buffer_list = NULL;
3766 info->rx_buffer_list = NULL;
3767 info->tx_buffer_list = NULL;
3768
3769 } /* end of mgsl_free_buffer_list_memory() */
3770
3771 /*
3772 * mgsl_alloc_frame_memory()
3773 *
3774 * Allocate the frame DMA buffers used by the specified buffer list.
3775 * Each DMA buffer will be one memory page in size. This is necessary
3776 * because memory can fragment enough that it may be impossible
3777 * contiguous pages.
3778 *
3779 * Arguments:
3780 *
3781 * info pointer to device instance data
3782 * BufferList pointer to list of buffer entries
3783 * Buffercount count of buffer entries in buffer list
3784 *
3785 * Return Value: 0 if success, otherwise -ENOMEM
3786 */
3787 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3788 {
3789 int i;
3790 u32 phys_addr;
3791
3792 /* Allocate page sized buffers for the receive buffer list */
3793
3794 for ( i = 0; i < Buffercount; i++ ) {
3795 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3796 /* PCI adapter uses shared memory buffers. */
3797 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3798 phys_addr = info->last_mem_alloc;
3799 info->last_mem_alloc += DMABUFFERSIZE;
3800 } else {
3801 /* ISA adapter uses system memory. */
3802 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3803 if (BufferList[i].virt_addr == NULL)
3804 return -ENOMEM;
3805 phys_addr = (u32)(BufferList[i].dma_addr);
3806 }
3807 BufferList[i].phys_addr = phys_addr;
3808 }
3809
3810 return 0;
3811
3812 } /* end of mgsl_alloc_frame_memory() */
3813
3814 /*
3815 * mgsl_free_frame_memory()
3816 *
3817 * Free the buffers associated with
3818 * each buffer entry of a buffer list.
3819 *
3820 * Arguments:
3821 *
3822 * info pointer to device instance data
3823 * BufferList pointer to list of buffer entries
3824 * Buffercount count of buffer entries in buffer list
3825 *
3826 * Return Value: None
3827 */
3828 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3829 {
3830 int i;
3831
3832 if ( BufferList ) {
3833 for ( i = 0 ; i < Buffercount ; i++ ) {
3834 if ( BufferList[i].virt_addr ) {
3835 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3836 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3837 BufferList[i].virt_addr = NULL;
3838 }
3839 }
3840 }
3841
3842 } /* end of mgsl_free_frame_memory() */
3843
3844 /* mgsl_free_dma_buffers()
3845 *
3846 * Free DMA buffers
3847 *
3848 * Arguments: info pointer to device instance data
3849 * Return Value: None
3850 */
3851 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3852 {
3853 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3854 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3855 mgsl_free_buffer_list_memory( info );
3856
3857 } /* end of mgsl_free_dma_buffers() */
3858
3859
3860 /*
3861 * mgsl_alloc_intermediate_rxbuffer_memory()
3862 *
3863 * Allocate a buffer large enough to hold max_frame_size. This buffer
3864 * is used to pass an assembled frame to the line discipline.
3865 *
3866 * Arguments:
3867 *
3868 * info pointer to device instance data
3869 *
3870 * Return Value: 0 if success, otherwise -ENOMEM
3871 */
3872 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3873 {
3874 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3875 if ( info->intermediate_rxbuffer == NULL )
3876 return -ENOMEM;
3877 /* unused flag buffer to satisfy receive_buf calling interface */
3878 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3879 if (!info->flag_buf) {
3880 kfree(info->intermediate_rxbuffer);
3881 info->intermediate_rxbuffer = NULL;
3882 return -ENOMEM;
3883 }
3884 return 0;
3885
3886 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3887
3888 /*
3889 * mgsl_free_intermediate_rxbuffer_memory()
3890 *
3891 *
3892 * Arguments:
3893 *
3894 * info pointer to device instance data
3895 *
3896 * Return Value: None
3897 */
3898 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3899 {
3900 kfree(info->intermediate_rxbuffer);
3901 info->intermediate_rxbuffer = NULL;
3902 kfree(info->flag_buf);
3903 info->flag_buf = NULL;
3904
3905 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3906
3907 /*
3908 * mgsl_alloc_intermediate_txbuffer_memory()
3909 *
3910 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3911 * This buffer is used to load transmit frames into the adapter's dma transfer
3912 * buffers when there is sufficient space.
3913 *
3914 * Arguments:
3915 *
3916 * info pointer to device instance data
3917 *
3918 * Return Value: 0 if success, otherwise -ENOMEM
3919 */
3920 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3921 {
3922 int i;
3923
3924 if ( debug_level >= DEBUG_LEVEL_INFO )
3925 printk("%s %s(%d) allocating %d tx holding buffers\n",
3926 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3927
3928 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3929
3930 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3931 info->tx_holding_buffers[i].buffer =
3932 kmalloc(info->max_frame_size, GFP_KERNEL);
3933 if (info->tx_holding_buffers[i].buffer == NULL) {
3934 for (--i; i >= 0; i--) {
3935 kfree(info->tx_holding_buffers[i].buffer);
3936 info->tx_holding_buffers[i].buffer = NULL;
3937 }
3938 return -ENOMEM;
3939 }
3940 }
3941
3942 return 0;
3943
3944 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3945
3946 /*
3947 * mgsl_free_intermediate_txbuffer_memory()
3948 *
3949 *
3950 * Arguments:
3951 *
3952 * info pointer to device instance data
3953 *
3954 * Return Value: None
3955 */
3956 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3957 {
3958 int i;
3959
3960 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3961 kfree(info->tx_holding_buffers[i].buffer);
3962 info->tx_holding_buffers[i].buffer = NULL;
3963 }
3964
3965 info->get_tx_holding_index = 0;
3966 info->put_tx_holding_index = 0;
3967 info->tx_holding_count = 0;
3968
3969 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3970
3971
3972 /*
3973 * load_next_tx_holding_buffer()
3974 *
3975 * attempts to load the next buffered tx request into the
3976 * tx dma buffers
3977 *
3978 * Arguments:
3979 *
3980 * info pointer to device instance data
3981 *
3982 * Return Value: true if next buffered tx request loaded
3983 * into adapter's tx dma buffer,
3984 * false otherwise
3985 */
3986 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
3987 {
3988 bool ret = false;
3989
3990 if ( info->tx_holding_count ) {
3991 /* determine if we have enough tx dma buffers
3992 * to accommodate the next tx frame
3993 */
3994 struct tx_holding_buffer *ptx =
3995 &info->tx_holding_buffers[info->get_tx_holding_index];
3996 int num_free = num_free_tx_dma_buffers(info);
3997 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
3998 if ( ptx->buffer_size % DMABUFFERSIZE )
3999 ++num_needed;
4000
4001 if (num_needed <= num_free) {
4002 info->xmit_cnt = ptx->buffer_size;
4003 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4004
4005 --info->tx_holding_count;
4006 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4007 info->get_tx_holding_index=0;
4008
4009 /* restart transmit timer */
4010 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4011
4012 ret = true;
4013 }
4014 }
4015
4016 return ret;
4017 }
4018
4019 /*
4020 * save_tx_buffer_request()
4021 *
4022 * attempt to store transmit frame request for later transmission
4023 *
4024 * Arguments:
4025 *
4026 * info pointer to device instance data
4027 * Buffer pointer to buffer containing frame to load
4028 * BufferSize size in bytes of frame in Buffer
4029 *
4030 * Return Value: 1 if able to store, 0 otherwise
4031 */
4032 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4033 {
4034 struct tx_holding_buffer *ptx;
4035
4036 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4037 return 0; /* all buffers in use */
4038 }
4039
4040 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4041 ptx->buffer_size = BufferSize;
4042 memcpy( ptx->buffer, Buffer, BufferSize);
4043
4044 ++info->tx_holding_count;
4045 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4046 info->put_tx_holding_index=0;
4047
4048 return 1;
4049 }
4050
4051 static int mgsl_claim_resources(struct mgsl_struct *info)
4052 {
4053 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4054 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4055 __FILE__,__LINE__,info->device_name, info->io_base);
4056 return -ENODEV;
4057 }
4058 info->io_addr_requested = true;
4059
4060 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4061 info->device_name, info ) < 0 ) {
4062 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4063 __FILE__,__LINE__,info->device_name, info->irq_level );
4064 goto errout;
4065 }
4066 info->irq_requested = true;
4067
4068 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4069 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4070 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4071 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4072 goto errout;
4073 }
4074 info->shared_mem_requested = true;
4075 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4076 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4077 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4078 goto errout;
4079 }
4080 info->lcr_mem_requested = true;
4081
4082 info->memory_base = ioremap_nocache(info->phys_memory_base,
4083 0x40000);
4084 if (!info->memory_base) {
4085 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4086 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4087 goto errout;
4088 }
4089
4090 if ( !mgsl_memory_test(info) ) {
4091 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4092 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4093 goto errout;
4094 }
4095
4096 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4097 PAGE_SIZE);
4098 if (!info->lcr_base) {
4099 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4100 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4101 goto errout;
4102 }
4103 info->lcr_base += info->lcr_offset;
4104
4105 } else {
4106 /* claim DMA channel */
4107
4108 if (request_dma(info->dma_level,info->device_name) < 0){
4109 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4110 __FILE__,__LINE__,info->device_name, info->dma_level );
4111 mgsl_release_resources( info );
4112 return -ENODEV;
4113 }
4114 info->dma_requested = true;
4115
4116 /* ISA adapter uses bus master DMA */
4117 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4118 enable_dma(info->dma_level);
4119 }
4120
4121 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4122 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4123 __FILE__,__LINE__,info->device_name, info->dma_level );
4124 goto errout;
4125 }
4126
4127 return 0;
4128 errout:
4129 mgsl_release_resources(info);
4130 return -ENODEV;
4131
4132 } /* end of mgsl_claim_resources() */
4133
4134 static void mgsl_release_resources(struct mgsl_struct *info)
4135 {
4136 if ( debug_level >= DEBUG_LEVEL_INFO )
4137 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4138 __FILE__,__LINE__,info->device_name );
4139
4140 if ( info->irq_requested ) {
4141 free_irq(info->irq_level, info);
4142 info->irq_requested = false;
4143 }
4144 if ( info->dma_requested ) {
4145 disable_dma(info->dma_level);
4146 free_dma(info->dma_level);
4147 info->dma_requested = false;
4148 }
4149 mgsl_free_dma_buffers(info);
4150 mgsl_free_intermediate_rxbuffer_memory(info);
4151 mgsl_free_intermediate_txbuffer_memory(info);
4152
4153 if ( info->io_addr_requested ) {
4154 release_region(info->io_base,info->io_addr_size);
4155 info->io_addr_requested = false;
4156 }
4157 if ( info->shared_mem_requested ) {
4158 release_mem_region(info->phys_memory_base,0x40000);
4159 info->shared_mem_requested = false;
4160 }
4161 if ( info->lcr_mem_requested ) {
4162 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4163 info->lcr_mem_requested = false;
4164 }
4165 if (info->memory_base){
4166 iounmap(info->memory_base);
4167 info->memory_base = NULL;
4168 }
4169 if (info->lcr_base){
4170 iounmap(info->lcr_base - info->lcr_offset);
4171 info->lcr_base = NULL;
4172 }
4173
4174 if ( debug_level >= DEBUG_LEVEL_INFO )
4175 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4176 __FILE__,__LINE__,info->device_name );
4177
4178 } /* end of mgsl_release_resources() */
4179
4180 /* mgsl_add_device()
4181 *
4182 * Add the specified device instance data structure to the
4183 * global linked list of devices and increment the device count.
4184 *
4185 * Arguments: info pointer to device instance data
4186 * Return Value: None
4187 */
4188 static void mgsl_add_device( struct mgsl_struct *info )
4189 {
4190 info->next_device = NULL;
4191 info->line = mgsl_device_count;
4192 sprintf(info->device_name,"ttySL%d",info->line);
4193
4194 if (info->line < MAX_TOTAL_DEVICES) {
4195 if (maxframe[info->line])
4196 info->max_frame_size = maxframe[info->line];
4197
4198 if (txdmabufs[info->line]) {
4199 info->num_tx_dma_buffers = txdmabufs[info->line];
4200 if (info->num_tx_dma_buffers < 1)
4201 info->num_tx_dma_buffers = 1;
4202 }
4203
4204 if (txholdbufs[info->line]) {
4205 info->num_tx_holding_buffers = txholdbufs[info->line];
4206 if (info->num_tx_holding_buffers < 1)
4207 info->num_tx_holding_buffers = 1;
4208 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4209 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4210 }
4211 }
4212
4213 mgsl_device_count++;
4214
4215 if ( !mgsl_device_list )
4216 mgsl_device_list = info;
4217 else {
4218 struct mgsl_struct *current_dev = mgsl_device_list;
4219 while( current_dev->next_device )
4220 current_dev = current_dev->next_device;
4221 current_dev->next_device = info;
4222 }
4223
4224 if ( info->max_frame_size < 4096 )
4225 info->max_frame_size = 4096;
4226 else if ( info->max_frame_size > 65535 )
4227 info->max_frame_size = 65535;
4228
4229 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4230 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4231 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4232 info->phys_memory_base, info->phys_lcr_base,
4233 info->max_frame_size );
4234 } else {
4235 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4236 info->device_name, info->io_base, info->irq_level, info->dma_level,
4237 info->max_frame_size );
4238 }
4239
4240 #if SYNCLINK_GENERIC_HDLC
4241 hdlcdev_init(info);
4242 #endif
4243
4244 } /* end of mgsl_add_device() */
4245
4246 static const struct tty_port_operations mgsl_port_ops = {
4247 .carrier_raised = carrier_raised,
4248 .dtr_rts = dtr_rts,
4249 };
4250
4251
4252 /* mgsl_allocate_device()
4253 *
4254 * Allocate and initialize a device instance structure
4255 *
4256 * Arguments: none
4257 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4258 */
4259 static struct mgsl_struct* mgsl_allocate_device(void)
4260 {
4261 struct mgsl_struct *info;
4262
4263 info = kzalloc(sizeof(struct mgsl_struct),
4264 GFP_KERNEL);
4265
4266 if (!info) {
4267 printk("Error can't allocate device instance data\n");
4268 } else {
4269 tty_port_init(&info->port);
4270 info->port.ops = &mgsl_port_ops;
4271 info->magic = MGSL_MAGIC;
4272 INIT_WORK(&info->task, mgsl_bh_handler);
4273 info->max_frame_size = 4096;
4274 info->port.close_delay = 5*HZ/10;
4275 info->port.closing_wait = 30*HZ;
4276 init_waitqueue_head(&info->status_event_wait_q);
4277 init_waitqueue_head(&info->event_wait_q);
4278 spin_lock_init(&info->irq_spinlock);
4279 spin_lock_init(&info->netlock);
4280 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4281 info->idle_mode = HDLC_TXIDLE_FLAGS;
4282 info->num_tx_dma_buffers = 1;
4283 info->num_tx_holding_buffers = 0;
4284 }
4285
4286 return info;
4287
4288 } /* end of mgsl_allocate_device()*/
4289
4290 static const struct tty_operations mgsl_ops = {
4291 .install = mgsl_install,
4292 .open = mgsl_open,
4293 .close = mgsl_close,
4294 .write = mgsl_write,
4295 .put_char = mgsl_put_char,
4296 .flush_chars = mgsl_flush_chars,
4297 .write_room = mgsl_write_room,
4298 .chars_in_buffer = mgsl_chars_in_buffer,
4299 .flush_buffer = mgsl_flush_buffer,
4300 .ioctl = mgsl_ioctl,
4301 .throttle = mgsl_throttle,
4302 .unthrottle = mgsl_unthrottle,
4303 .send_xchar = mgsl_send_xchar,
4304 .break_ctl = mgsl_break,
4305 .wait_until_sent = mgsl_wait_until_sent,
4306 .set_termios = mgsl_set_termios,
4307 .stop = mgsl_stop,
4308 .start = mgsl_start,
4309 .hangup = mgsl_hangup,
4310 .tiocmget = tiocmget,
4311 .tiocmset = tiocmset,
4312 .get_icount = msgl_get_icount,
4313 .proc_fops = &mgsl_proc_fops,
4314 };
4315
4316 /*
4317 * perform tty device initialization
4318 */
4319 static int mgsl_init_tty(void)
4320 {
4321 int rc;
4322
4323 serial_driver = alloc_tty_driver(128);
4324 if (!serial_driver)
4325 return -ENOMEM;
4326
4327 serial_driver->driver_name = "synclink";
4328 serial_driver->name = "ttySL";
4329 serial_driver->major = ttymajor;
4330 serial_driver->minor_start = 64;
4331 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4332 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4333 serial_driver->init_termios = tty_std_termios;
4334 serial_driver->init_termios.c_cflag =
4335 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4336 serial_driver->init_termios.c_ispeed = 9600;
4337 serial_driver->init_termios.c_ospeed = 9600;
4338 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4339 tty_set_operations(serial_driver, &mgsl_ops);
4340 if ((rc = tty_register_driver(serial_driver)) < 0) {
4341 printk("%s(%d):Couldn't register serial driver\n",
4342 __FILE__,__LINE__);
4343 put_tty_driver(serial_driver);
4344 serial_driver = NULL;
4345 return rc;
4346 }
4347
4348 printk("%s %s, tty major#%d\n",
4349 driver_name, driver_version,
4350 serial_driver->major);
4351 return 0;
4352 }
4353
4354 /* enumerate user specified ISA adapters
4355 */
4356 static void mgsl_enum_isa_devices(void)
4357 {
4358 struct mgsl_struct *info;
4359 int i;
4360
4361 /* Check for user specified ISA devices */
4362
4363 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4364 if ( debug_level >= DEBUG_LEVEL_INFO )
4365 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4366 io[i], irq[i], dma[i] );
4367
4368 info = mgsl_allocate_device();
4369 if ( !info ) {
4370 /* error allocating device instance data */
4371 if ( debug_level >= DEBUG_LEVEL_ERROR )
4372 printk( "can't allocate device instance data.\n");
4373 continue;
4374 }
4375
4376 /* Copy user configuration info to device instance data */
4377 info->io_base = (unsigned int)io[i];
4378 info->irq_level = (unsigned int)irq[i];
4379 info->irq_level = irq_canonicalize(info->irq_level);
4380 info->dma_level = (unsigned int)dma[i];
4381 info->bus_type = MGSL_BUS_TYPE_ISA;
4382 info->io_addr_size = 16;
4383 info->irq_flags = 0;
4384
4385 mgsl_add_device( info );
4386 }
4387 }
4388
4389 static void synclink_cleanup(void)
4390 {
4391 int rc;
4392 struct mgsl_struct *info;
4393 struct mgsl_struct *tmp;
4394
4395 printk("Unloading %s: %s\n", driver_name, driver_version);
4396
4397 if (serial_driver) {
4398 rc = tty_unregister_driver(serial_driver);
4399 if (rc)
4400 printk("%s(%d) failed to unregister tty driver err=%d\n",
4401 __FILE__,__LINE__,rc);
4402 put_tty_driver(serial_driver);
4403 }
4404
4405 info = mgsl_device_list;
4406 while(info) {
4407 #if SYNCLINK_GENERIC_HDLC
4408 hdlcdev_exit(info);
4409 #endif
4410 mgsl_release_resources(info);
4411 tmp = info;
4412 info = info->next_device;
4413 tty_port_destroy(&tmp->port);
4414 kfree(tmp);
4415 }
4416
4417 if (pci_registered)
4418 pci_unregister_driver(&synclink_pci_driver);
4419 }
4420
4421 static int __init synclink_init(void)
4422 {
4423 int rc;
4424
4425 if (break_on_load) {
4426 mgsl_get_text_ptr();
4427 BREAKPOINT();
4428 }
4429
4430 printk("%s %s\n", driver_name, driver_version);
4431
4432 mgsl_enum_isa_devices();
4433 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4434 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4435 else
4436 pci_registered = true;
4437
4438 if ((rc = mgsl_init_tty()) < 0)
4439 goto error;
4440
4441 return 0;
4442
4443 error:
4444 synclink_cleanup();
4445 return rc;
4446 }
4447
4448 static void __exit synclink_exit(void)
4449 {
4450 synclink_cleanup();
4451 }
4452
4453 module_init(synclink_init);
4454 module_exit(synclink_exit);
4455
4456 /*
4457 * usc_RTCmd()
4458 *
4459 * Issue a USC Receive/Transmit command to the
4460 * Channel Command/Address Register (CCAR).
4461 *
4462 * Notes:
4463 *
4464 * The command is encoded in the most significant 5 bits <15..11>
4465 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4466 * and Bits <6..0> must be written as zeros.
4467 *
4468 * Arguments:
4469 *
4470 * info pointer to device information structure
4471 * Cmd command mask (use symbolic macros)
4472 *
4473 * Return Value:
4474 *
4475 * None
4476 */
4477 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4478 {
4479 /* output command to CCAR in bits <15..11> */
4480 /* preserve bits <10..7>, bits <6..0> must be zero */
4481
4482 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4483
4484 /* Read to flush write to CCAR */
4485 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4486 inw( info->io_base + CCAR );
4487
4488 } /* end of usc_RTCmd() */
4489
4490 /*
4491 * usc_DmaCmd()
4492 *
4493 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4494 *
4495 * Arguments:
4496 *
4497 * info pointer to device information structure
4498 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4499 *
4500 * Return Value:
4501 *
4502 * None
4503 */
4504 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4505 {
4506 /* write command mask to DCAR */
4507 outw( Cmd + info->mbre_bit, info->io_base );
4508
4509 /* Read to flush write to DCAR */
4510 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4511 inw( info->io_base );
4512
4513 } /* end of usc_DmaCmd() */
4514
4515 /*
4516 * usc_OutDmaReg()
4517 *
4518 * Write a 16-bit value to a USC DMA register
4519 *
4520 * Arguments:
4521 *
4522 * info pointer to device info structure
4523 * RegAddr register address (number) for write
4524 * RegValue 16-bit value to write to register
4525 *
4526 * Return Value:
4527 *
4528 * None
4529 *
4530 */
4531 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4532 {
4533 /* Note: The DCAR is located at the adapter base address */
4534 /* Note: must preserve state of BIT8 in DCAR */
4535
4536 outw( RegAddr + info->mbre_bit, info->io_base );
4537 outw( RegValue, info->io_base );
4538
4539 /* Read to flush write to DCAR */
4540 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4541 inw( info->io_base );
4542
4543 } /* end of usc_OutDmaReg() */
4544
4545 /*
4546 * usc_InDmaReg()
4547 *
4548 * Read a 16-bit value from a DMA register
4549 *
4550 * Arguments:
4551 *
4552 * info pointer to device info structure
4553 * RegAddr register address (number) to read from
4554 *
4555 * Return Value:
4556 *
4557 * The 16-bit value read from register
4558 *
4559 */
4560 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4561 {
4562 /* Note: The DCAR is located at the adapter base address */
4563 /* Note: must preserve state of BIT8 in DCAR */
4564
4565 outw( RegAddr + info->mbre_bit, info->io_base );
4566 return inw( info->io_base );
4567
4568 } /* end of usc_InDmaReg() */
4569
4570 /*
4571 *
4572 * usc_OutReg()
4573 *
4574 * Write a 16-bit value to a USC serial channel register
4575 *
4576 * Arguments:
4577 *
4578 * info pointer to device info structure
4579 * RegAddr register address (number) to write to
4580 * RegValue 16-bit value to write to register
4581 *
4582 * Return Value:
4583 *
4584 * None
4585 *
4586 */
4587 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4588 {
4589 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4590 outw( RegValue, info->io_base + CCAR );
4591
4592 /* Read to flush write to CCAR */
4593 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4594 inw( info->io_base + CCAR );
4595
4596 } /* end of usc_OutReg() */
4597
4598 /*
4599 * usc_InReg()
4600 *
4601 * Reads a 16-bit value from a USC serial channel register
4602 *
4603 * Arguments:
4604 *
4605 * info pointer to device extension
4606 * RegAddr register address (number) to read from
4607 *
4608 * Return Value:
4609 *
4610 * 16-bit value read from register
4611 */
4612 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4613 {
4614 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4615 return inw( info->io_base + CCAR );
4616
4617 } /* end of usc_InReg() */
4618
4619 /* usc_set_sdlc_mode()
4620 *
4621 * Set up the adapter for SDLC DMA communications.
4622 *
4623 * Arguments: info pointer to device instance data
4624 * Return Value: NONE
4625 */
4626 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4627 {
4628 u16 RegValue;
4629 bool PreSL1660;
4630
4631 /*
4632 * determine if the IUSC on the adapter is pre-SL1660. If
4633 * not, take advantage of the UnderWait feature of more
4634 * modern chips. If an underrun occurs and this bit is set,
4635 * the transmitter will idle the programmed idle pattern
4636 * until the driver has time to service the underrun. Otherwise,
4637 * the dma controller may get the cycles previously requested
4638 * and begin transmitting queued tx data.
4639 */
4640 usc_OutReg(info,TMCR,0x1f);
4641 RegValue=usc_InReg(info,TMDR);
4642 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4643
4644 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4645 {
4646 /*
4647 ** Channel Mode Register (CMR)
4648 **
4649 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4650 ** <13> 0 0 = Transmit Disabled (initially)
4651 ** <12> 0 1 = Consecutive Idles share common 0
4652 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4653 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4654 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4655 **
4656 ** 1000 1110 0000 0110 = 0x8e06
4657 */
4658 RegValue = 0x8e06;
4659
4660 /*--------------------------------------------------
4661 * ignore user options for UnderRun Actions and
4662 * preambles
4663 *--------------------------------------------------*/
4664 }
4665 else
4666 {
4667 /* Channel mode Register (CMR)
4668 *
4669 * <15..14> 00 Tx Sub modes, Underrun Action
4670 * <13> 0 1 = Send Preamble before opening flag
4671 * <12> 0 1 = Consecutive Idles share common 0
4672 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4673 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4674 * <3..0> 0110 Receiver mode = HDLC/SDLC
4675 *
4676 * 0000 0110 0000 0110 = 0x0606
4677 */
4678 if (info->params.mode == MGSL_MODE_RAW) {
4679 RegValue = 0x0001; /* Set Receive mode = external sync */
4680
4681 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4682 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4683
4684 /*
4685 * TxSubMode:
4686 * CMR <15> 0 Don't send CRC on Tx Underrun
4687 * CMR <14> x undefined
4688 * CMR <13> 0 Send preamble before openning sync
4689 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4690 *
4691 * TxMode:
4692 * CMR <11-8) 0100 MonoSync
4693 *
4694 * 0x00 0100 xxxx xxxx 04xx
4695 */
4696 RegValue |= 0x0400;
4697 }
4698 else {
4699
4700 RegValue = 0x0606;
4701
4702 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4703 RegValue |= BIT14;
4704 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4705 RegValue |= BIT15;
4706 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4707 RegValue |= BIT15 | BIT14;
4708 }
4709
4710 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4711 RegValue |= BIT13;
4712 }
4713
4714 if ( info->params.mode == MGSL_MODE_HDLC &&
4715 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4716 RegValue |= BIT12;
4717
4718 if ( info->params.addr_filter != 0xff )
4719 {
4720 /* set up receive address filtering */
4721 usc_OutReg( info, RSR, info->params.addr_filter );
4722 RegValue |= BIT4;
4723 }
4724
4725 usc_OutReg( info, CMR, RegValue );
4726 info->cmr_value = RegValue;
4727
4728 /* Receiver mode Register (RMR)
4729 *
4730 * <15..13> 000 encoding
4731 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4732 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4733 * <9> 0 1 = Include Receive chars in CRC
4734 * <8> 1 1 = Use Abort/PE bit as abort indicator
4735 * <7..6> 00 Even parity
4736 * <5> 0 parity disabled
4737 * <4..2> 000 Receive Char Length = 8 bits
4738 * <1..0> 00 Disable Receiver
4739 *
4740 * 0000 0101 0000 0000 = 0x0500
4741 */
4742
4743 RegValue = 0x0500;
4744
4745 switch ( info->params.encoding ) {
4746 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4747 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4748 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
4749 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4750 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4751 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4752 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4753 }
4754
4755 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4756 RegValue |= BIT9;
4757 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4758 RegValue |= ( BIT12 | BIT10 | BIT9 );
4759
4760 usc_OutReg( info, RMR, RegValue );
4761
4762 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4763 /* When an opening flag of an SDLC frame is recognized the */
4764 /* Receive Character count (RCC) is loaded with the value in */
4765 /* RCLR. The RCC is decremented for each received byte. The */
4766 /* value of RCC is stored after the closing flag of the frame */
4767 /* allowing the frame size to be computed. */
4768
4769 usc_OutReg( info, RCLR, RCLRVALUE );
4770
4771 usc_RCmd( info, RCmd_SelectRicrdma_level );
4772
4773 /* Receive Interrupt Control Register (RICR)
4774 *
4775 * <15..8> ? RxFIFO DMA Request Level
4776 * <7> 0 Exited Hunt IA (Interrupt Arm)
4777 * <6> 0 Idle Received IA
4778 * <5> 0 Break/Abort IA
4779 * <4> 0 Rx Bound IA
4780 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4781 * <2> 0 Abort/PE IA
4782 * <1> 1 Rx Overrun IA
4783 * <0> 0 Select TC0 value for readback
4784 *
4785 * 0000 0000 0000 1000 = 0x000a
4786 */
4787
4788 /* Carry over the Exit Hunt and Idle Received bits */
4789 /* in case they have been armed by usc_ArmEvents. */
4790
4791 RegValue = usc_InReg( info, RICR ) & 0xc0;
4792
4793 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4794 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4795 else
4796 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4797
4798 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4799
4800 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4801 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4802
4803 /* Transmit mode Register (TMR)
4804 *
4805 * <15..13> 000 encoding
4806 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4807 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4808 * <9> 0 1 = Tx CRC Enabled
4809 * <8> 0 1 = Append CRC to end of transmit frame
4810 * <7..6> 00 Transmit parity Even
4811 * <5> 0 Transmit parity Disabled
4812 * <4..2> 000 Tx Char Length = 8 bits
4813 * <1..0> 00 Disable Transmitter
4814 *
4815 * 0000 0100 0000 0000 = 0x0400
4816 */
4817
4818 RegValue = 0x0400;
4819
4820 switch ( info->params.encoding ) {
4821 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4822 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4823 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
4824 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4825 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4826 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4827 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4828 }
4829
4830 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4831 RegValue |= BIT9 | BIT8;
4832 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4833 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4834
4835 usc_OutReg( info, TMR, RegValue );
4836
4837 usc_set_txidle( info );
4838
4839
4840 usc_TCmd( info, TCmd_SelectTicrdma_level );
4841
4842 /* Transmit Interrupt Control Register (TICR)
4843 *
4844 * <15..8> ? Transmit FIFO DMA Level
4845 * <7> 0 Present IA (Interrupt Arm)
4846 * <6> 0 Idle Sent IA
4847 * <5> 1 Abort Sent IA
4848 * <4> 1 EOF/EOM Sent IA
4849 * <3> 0 CRC Sent IA
4850 * <2> 1 1 = Wait for SW Trigger to Start Frame
4851 * <1> 1 Tx Underrun IA
4852 * <0> 0 TC0 constant on read back
4853 *
4854 * 0000 0000 0011 0110 = 0x0036
4855 */
4856
4857 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4858 usc_OutReg( info, TICR, 0x0736 );
4859 else
4860 usc_OutReg( info, TICR, 0x1436 );
4861
4862 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4863 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4864
4865 /*
4866 ** Transmit Command/Status Register (TCSR)
4867 **
4868 ** <15..12> 0000 TCmd
4869 ** <11> 0/1 UnderWait
4870 ** <10..08> 000 TxIdle
4871 ** <7> x PreSent
4872 ** <6> x IdleSent
4873 ** <5> x AbortSent
4874 ** <4> x EOF/EOM Sent
4875 ** <3> x CRC Sent
4876 ** <2> x All Sent
4877 ** <1> x TxUnder
4878 ** <0> x TxEmpty
4879 **
4880 ** 0000 0000 0000 0000 = 0x0000
4881 */
4882 info->tcsr_value = 0;
4883
4884 if ( !PreSL1660 )
4885 info->tcsr_value |= TCSR_UNDERWAIT;
4886
4887 usc_OutReg( info, TCSR, info->tcsr_value );
4888
4889 /* Clock mode Control Register (CMCR)
4890 *
4891 * <15..14> 00 counter 1 Source = Disabled
4892 * <13..12> 00 counter 0 Source = Disabled
4893 * <11..10> 11 BRG1 Input is TxC Pin
4894 * <9..8> 11 BRG0 Input is TxC Pin
4895 * <7..6> 01 DPLL Input is BRG1 Output
4896 * <5..3> XXX TxCLK comes from Port 0
4897 * <2..0> XXX RxCLK comes from Port 1
4898 *
4899 * 0000 1111 0111 0111 = 0x0f77
4900 */
4901
4902 RegValue = 0x0f40;
4903
4904 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4905 RegValue |= 0x0003; /* RxCLK from DPLL */
4906 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4907 RegValue |= 0x0004; /* RxCLK from BRG0 */
4908 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4909 RegValue |= 0x0006; /* RxCLK from TXC Input */
4910 else
4911 RegValue |= 0x0007; /* RxCLK from Port1 */
4912
4913 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4914 RegValue |= 0x0018; /* TxCLK from DPLL */
4915 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4916 RegValue |= 0x0020; /* TxCLK from BRG0 */
4917 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4918 RegValue |= 0x0038; /* RxCLK from TXC Input */
4919 else
4920 RegValue |= 0x0030; /* TxCLK from Port0 */
4921
4922 usc_OutReg( info, CMCR, RegValue );
4923
4924
4925 /* Hardware Configuration Register (HCR)
4926 *
4927 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4928 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4929 * <12> 0 CVOK:0=report code violation in biphase
4930 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4931 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4932 * <7..6> 00 reserved
4933 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4934 * <4> X BRG1 Enable
4935 * <3..2> 00 reserved
4936 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4937 * <0> 0 BRG0 Enable
4938 */
4939
4940 RegValue = 0x0000;
4941
4942 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
4943 u32 XtalSpeed;
4944 u32 DpllDivisor;
4945 u16 Tc;
4946
4947 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4948 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4949
4950 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4951 XtalSpeed = 11059200;
4952 else
4953 XtalSpeed = 14745600;
4954
4955 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4956 DpllDivisor = 16;
4957 RegValue |= BIT10;
4958 }
4959 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4960 DpllDivisor = 8;
4961 RegValue |= BIT11;
4962 }
4963 else
4964 DpllDivisor = 32;
4965
4966 /* Tc = (Xtal/Speed) - 1 */
4967 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4968 /* then rounding up gives a more precise time constant. Instead */
4969 /* of rounding up and then subtracting 1 we just don't subtract */
4970 /* the one in this case. */
4971
4972 /*--------------------------------------------------
4973 * ejz: for DPLL mode, application should use the
4974 * same clock speed as the partner system, even
4975 * though clocking is derived from the input RxData.
4976 * In case the user uses a 0 for the clock speed,
4977 * default to 0xffffffff and don't try to divide by
4978 * zero
4979 *--------------------------------------------------*/
4980 if ( info->params.clock_speed )
4981 {
4982 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4983 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4984 / info->params.clock_speed) )
4985 Tc--;
4986 }
4987 else
4988 Tc = -1;
4989
4990
4991 /* Write 16-bit Time Constant for BRG1 */
4992 usc_OutReg( info, TC1R, Tc );
4993
4994 RegValue |= BIT4; /* enable BRG1 */
4995
4996 switch ( info->params.encoding ) {
4997 case HDLC_ENCODING_NRZ:
4998 case HDLC_ENCODING_NRZB:
4999 case HDLC_ENCODING_NRZI_MARK:
5000 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5001 case HDLC_ENCODING_BIPHASE_MARK:
5002 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5003 case HDLC_ENCODING_BIPHASE_LEVEL:
5004 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
5005 }
5006 }
5007
5008 usc_OutReg( info, HCR, RegValue );
5009
5010
5011 /* Channel Control/status Register (CCSR)
5012 *
5013 * <15> X RCC FIFO Overflow status (RO)
5014 * <14> X RCC FIFO Not Empty status (RO)
5015 * <13> 0 1 = Clear RCC FIFO (WO)
5016 * <12> X DPLL Sync (RW)
5017 * <11> X DPLL 2 Missed Clocks status (RO)
5018 * <10> X DPLL 1 Missed Clock status (RO)
5019 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5020 * <7> X SDLC Loop On status (RO)
5021 * <6> X SDLC Loop Send status (RO)
5022 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5023 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5024 * <1..0> 00 reserved
5025 *
5026 * 0000 0000 0010 0000 = 0x0020
5027 */
5028
5029 usc_OutReg( info, CCSR, 0x1020 );
5030
5031
5032 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5033 usc_OutReg( info, SICR,
5034 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5035 }
5036
5037
5038 /* enable Master Interrupt Enable bit (MIE) */
5039 usc_EnableMasterIrqBit( info );
5040
5041 usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
5042 TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
5043
5044 /* arm RCC underflow interrupt */
5045 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5046 usc_EnableInterrupts(info, MISC);
5047
5048 info->mbre_bit = 0;
5049 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5050 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5051 info->mbre_bit = BIT8;
5052 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5053
5054 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5055 /* Enable DMAEN (Port 7, Bit 14) */
5056 /* This connects the DMA request signal to the ISA bus */
5057 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5058 }
5059
5060 /* DMA Control Register (DCR)
5061 *
5062 * <15..14> 10 Priority mode = Alternating Tx/Rx
5063 * 01 Rx has priority
5064 * 00 Tx has priority
5065 *
5066 * <13> 1 Enable Priority Preempt per DCR<15..14>
5067 * (WARNING DCR<11..10> must be 00 when this is 1)
5068 * 0 Choose activate channel per DCR<11..10>
5069 *
5070 * <12> 0 Little Endian for Array/List
5071 * <11..10> 00 Both Channels can use each bus grant
5072 * <9..6> 0000 reserved
5073 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5074 * <4> 0 1 = drive D/C and S/D pins
5075 * <3> 1 1 = Add one wait state to all DMA cycles.
5076 * <2> 0 1 = Strobe /UAS on every transfer.
5077 * <1..0> 11 Addr incrementing only affects LS24 bits
5078 *
5079 * 0110 0000 0000 1011 = 0x600b
5080 */
5081
5082 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5083 /* PCI adapter does not need DMA wait state */
5084 usc_OutDmaReg( info, DCR, 0xa00b );
5085 }
5086 else
5087 usc_OutDmaReg( info, DCR, 0x800b );
5088
5089
5090 /* Receive DMA mode Register (RDMR)
5091 *
5092 * <15..14> 11 DMA mode = Linked List Buffer mode
5093 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5094 * <12> 1 Clear count of List Entry after fetching
5095 * <11..10> 00 Address mode = Increment
5096 * <9> 1 Terminate Buffer on RxBound
5097 * <8> 0 Bus Width = 16bits
5098 * <7..0> ? status Bits (write as 0s)
5099 *
5100 * 1111 0010 0000 0000 = 0xf200
5101 */
5102
5103 usc_OutDmaReg( info, RDMR, 0xf200 );
5104
5105
5106 /* Transmit DMA mode Register (TDMR)
5107 *
5108 * <15..14> 11 DMA mode = Linked List Buffer mode
5109 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5110 * <12> 1 Clear count of List Entry after fetching
5111 * <11..10> 00 Address mode = Increment
5112 * <9> 1 Terminate Buffer on end of frame
5113 * <8> 0 Bus Width = 16bits
5114 * <7..0> ? status Bits (Read Only so write as 0)
5115 *
5116 * 1111 0010 0000 0000 = 0xf200
5117 */
5118
5119 usc_OutDmaReg( info, TDMR, 0xf200 );
5120
5121
5122 /* DMA Interrupt Control Register (DICR)
5123 *
5124 * <15> 1 DMA Interrupt Enable
5125 * <14> 0 1 = Disable IEO from USC
5126 * <13> 0 1 = Don't provide vector during IntAck
5127 * <12> 1 1 = Include status in Vector
5128 * <10..2> 0 reserved, Must be 0s
5129 * <1> 0 1 = Rx DMA Interrupt Enabled
5130 * <0> 0 1 = Tx DMA Interrupt Enabled
5131 *
5132 * 1001 0000 0000 0000 = 0x9000
5133 */
5134
5135 usc_OutDmaReg( info, DICR, 0x9000 );
5136
5137 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5138 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5139 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5140
5141 /* Channel Control Register (CCR)
5142 *
5143 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5144 * <13> 0 Trigger Tx on SW Command Disabled
5145 * <12> 0 Flag Preamble Disabled
5146 * <11..10> 00 Preamble Length
5147 * <9..8> 00 Preamble Pattern
5148 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5149 * <5> 0 Trigger Rx on SW Command Disabled
5150 * <4..0> 0 reserved
5151 *
5152 * 1000 0000 1000 0000 = 0x8080
5153 */
5154
5155 RegValue = 0x8080;
5156
5157 switch ( info->params.preamble_length ) {
5158 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5159 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5160 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
5161 }
5162
5163 switch ( info->params.preamble ) {
5164 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
5165 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5166 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5167 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
5168 }
5169
5170 usc_OutReg( info, CCR, RegValue );
5171
5172
5173 /*
5174 * Burst/Dwell Control Register
5175 *
5176 * <15..8> 0x20 Maximum number of transfers per bus grant
5177 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5178 */
5179
5180 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5181 /* don't limit bus occupancy on PCI adapter */
5182 usc_OutDmaReg( info, BDCR, 0x0000 );
5183 }
5184 else
5185 usc_OutDmaReg( info, BDCR, 0x2000 );
5186
5187 usc_stop_transmitter(info);
5188 usc_stop_receiver(info);
5189
5190 } /* end of usc_set_sdlc_mode() */
5191
5192 /* usc_enable_loopback()
5193 *
5194 * Set the 16C32 for internal loopback mode.
5195 * The TxCLK and RxCLK signals are generated from the BRG0 and
5196 * the TxD is looped back to the RxD internally.
5197 *
5198 * Arguments: info pointer to device instance data
5199 * enable 1 = enable loopback, 0 = disable
5200 * Return Value: None
5201 */
5202 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5203 {
5204 if (enable) {
5205 /* blank external TXD output */
5206 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
5207
5208 /* Clock mode Control Register (CMCR)
5209 *
5210 * <15..14> 00 counter 1 Disabled
5211 * <13..12> 00 counter 0 Disabled
5212 * <11..10> 11 BRG1 Input is TxC Pin
5213 * <9..8> 11 BRG0 Input is TxC Pin
5214 * <7..6> 01 DPLL Input is BRG1 Output
5215 * <5..3> 100 TxCLK comes from BRG0
5216 * <2..0> 100 RxCLK comes from BRG0
5217 *
5218 * 0000 1111 0110 0100 = 0x0f64
5219 */
5220
5221 usc_OutReg( info, CMCR, 0x0f64 );
5222
5223 /* Write 16-bit Time Constant for BRG0 */
5224 /* use clock speed if available, otherwise use 8 for diagnostics */
5225 if (info->params.clock_speed) {
5226 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5227 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5228 else
5229 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5230 } else
5231 usc_OutReg(info, TC0R, (u16)8);
5232
5233 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5234 mode = Continuous Set Bit 0 to enable BRG0. */
5235 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5236
5237 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5238 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5239
5240 /* set Internal Data loopback mode */
5241 info->loopback_bits = 0x300;
5242 outw( 0x0300, info->io_base + CCAR );
5243 } else {
5244 /* enable external TXD output */
5245 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
5246
5247 /* clear Internal Data loopback mode */
5248 info->loopback_bits = 0;
5249 outw( 0,info->io_base + CCAR );
5250 }
5251
5252 } /* end of usc_enable_loopback() */
5253
5254 /* usc_enable_aux_clock()
5255 *
5256 * Enabled the AUX clock output at the specified frequency.
5257 *
5258 * Arguments:
5259 *
5260 * info pointer to device extension
5261 * data_rate data rate of clock in bits per second
5262 * A data rate of 0 disables the AUX clock.
5263 *
5264 * Return Value: None
5265 */
5266 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5267 {
5268 u32 XtalSpeed;
5269 u16 Tc;
5270
5271 if ( data_rate ) {
5272 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5273 XtalSpeed = 11059200;
5274 else
5275 XtalSpeed = 14745600;
5276
5277
5278 /* Tc = (Xtal/Speed) - 1 */
5279 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5280 /* then rounding up gives a more precise time constant. Instead */
5281 /* of rounding up and then subtracting 1 we just don't subtract */
5282 /* the one in this case. */
5283
5284
5285 Tc = (u16)(XtalSpeed/data_rate);
5286 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5287 Tc--;
5288
5289 /* Write 16-bit Time Constant for BRG0 */
5290 usc_OutReg( info, TC0R, Tc );
5291
5292 /*
5293 * Hardware Configuration Register (HCR)
5294 * Clear Bit 1, BRG0 mode = Continuous
5295 * Set Bit 0 to enable BRG0.
5296 */
5297
5298 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5299
5300 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5301 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5302 } else {
5303 /* data rate == 0 so turn off BRG0 */
5304 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5305 }
5306
5307 } /* end of usc_enable_aux_clock() */
5308
5309 /*
5310 *
5311 * usc_process_rxoverrun_sync()
5312 *
5313 * This function processes a receive overrun by resetting the
5314 * receive DMA buffers and issuing a Purge Rx FIFO command
5315 * to allow the receiver to continue receiving.
5316 *
5317 * Arguments:
5318 *
5319 * info pointer to device extension
5320 *
5321 * Return Value: None
5322 */
5323 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5324 {
5325 int start_index;
5326 int end_index;
5327 int frame_start_index;
5328 bool start_of_frame_found = false;
5329 bool end_of_frame_found = false;
5330 bool reprogram_dma = false;
5331
5332 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5333 u32 phys_addr;
5334
5335 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5336 usc_RCmd( info, RCmd_EnterHuntmode );
5337 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5338
5339 /* CurrentRxBuffer points to the 1st buffer of the next */
5340 /* possibly available receive frame. */
5341
5342 frame_start_index = start_index = end_index = info->current_rx_buffer;
5343
5344 /* Search for an unfinished string of buffers. This means */
5345 /* that a receive frame started (at least one buffer with */
5346 /* count set to zero) but there is no terminiting buffer */
5347 /* (status set to non-zero). */
5348
5349 while( !buffer_list[end_index].count )
5350 {
5351 /* Count field has been reset to zero by 16C32. */
5352 /* This buffer is currently in use. */
5353
5354 if ( !start_of_frame_found )
5355 {
5356 start_of_frame_found = true;
5357 frame_start_index = end_index;
5358 end_of_frame_found = false;
5359 }
5360
5361 if ( buffer_list[end_index].status )
5362 {
5363 /* Status field has been set by 16C32. */
5364 /* This is the last buffer of a received frame. */
5365
5366 /* We want to leave the buffers for this frame intact. */
5367 /* Move on to next possible frame. */
5368
5369 start_of_frame_found = false;
5370 end_of_frame_found = true;
5371 }
5372
5373 /* advance to next buffer entry in linked list */
5374 end_index++;
5375 if ( end_index == info->rx_buffer_count )
5376 end_index = 0;
5377
5378 if ( start_index == end_index )
5379 {
5380 /* The entire list has been searched with all Counts == 0 and */
5381 /* all Status == 0. The receive buffers are */
5382 /* completely screwed, reset all receive buffers! */
5383 mgsl_reset_rx_dma_buffers( info );
5384 frame_start_index = 0;
5385 start_of_frame_found = false;
5386 reprogram_dma = true;
5387 break;
5388 }
5389 }
5390
5391 if ( start_of_frame_found && !end_of_frame_found )
5392 {
5393 /* There is an unfinished string of receive DMA buffers */
5394 /* as a result of the receiver overrun. */
5395
5396 /* Reset the buffers for the unfinished frame */
5397 /* and reprogram the receive DMA controller to start */
5398 /* at the 1st buffer of unfinished frame. */
5399
5400 start_index = frame_start_index;
5401
5402 do
5403 {
5404 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5405
5406 /* Adjust index for wrap around. */
5407 if ( start_index == info->rx_buffer_count )
5408 start_index = 0;
5409
5410 } while( start_index != end_index );
5411
5412 reprogram_dma = true;
5413 }
5414
5415 if ( reprogram_dma )
5416 {
5417 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5418 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5419 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5420
5421 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5422
5423 /* This empties the receive FIFO and loads the RCC with RCLR */
5424 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5425
5426 /* program 16C32 with physical address of 1st DMA buffer entry */
5427 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5428 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5429 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5430
5431 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5432 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5433 usc_EnableInterrupts( info, RECEIVE_STATUS );
5434
5435 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5436 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5437
5438 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5439 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5440 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5441 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5442 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5443 else
5444 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5445 }
5446 else
5447 {
5448 /* This empties the receive FIFO and loads the RCC with RCLR */
5449 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5450 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5451 }
5452
5453 } /* end of usc_process_rxoverrun_sync() */
5454
5455 /* usc_stop_receiver()
5456 *
5457 * Disable USC receiver
5458 *
5459 * Arguments: info pointer to device instance data
5460 * Return Value: None
5461 */
5462 static void usc_stop_receiver( struct mgsl_struct *info )
5463 {
5464 if (debug_level >= DEBUG_LEVEL_ISR)
5465 printk("%s(%d):usc_stop_receiver(%s)\n",
5466 __FILE__,__LINE__, info->device_name );
5467
5468 /* Disable receive DMA channel. */
5469 /* This also disables receive DMA channel interrupts */
5470 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5471
5472 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5473 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5474 usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
5475
5476 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5477
5478 /* This empties the receive FIFO and loads the RCC with RCLR */
5479 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5480 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5481
5482 info->rx_enabled = false;
5483 info->rx_overflow = false;
5484 info->rx_rcc_underrun = false;
5485
5486 } /* end of stop_receiver() */
5487
5488 /* usc_start_receiver()
5489 *
5490 * Enable the USC receiver
5491 *
5492 * Arguments: info pointer to device instance data
5493 * Return Value: None
5494 */
5495 static void usc_start_receiver( struct mgsl_struct *info )
5496 {
5497 u32 phys_addr;
5498
5499 if (debug_level >= DEBUG_LEVEL_ISR)
5500 printk("%s(%d):usc_start_receiver(%s)\n",
5501 __FILE__,__LINE__, info->device_name );
5502
5503 mgsl_reset_rx_dma_buffers( info );
5504 usc_stop_receiver( info );
5505
5506 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5507 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5508
5509 if ( info->params.mode == MGSL_MODE_HDLC ||
5510 info->params.mode == MGSL_MODE_RAW ) {
5511 /* DMA mode Transfers */
5512 /* Program the DMA controller. */
5513 /* Enable the DMA controller end of buffer interrupt. */
5514
5515 /* program 16C32 with physical address of 1st DMA buffer entry */
5516 phys_addr = info->rx_buffer_list[0].phys_entry;
5517 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5518 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5519
5520 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5521 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5522 usc_EnableInterrupts( info, RECEIVE_STATUS );
5523
5524 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5525 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5526
5527 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5528 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5529 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5530 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5531 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5532 else
5533 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5534 } else {
5535 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5536 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
5537 usc_EnableInterrupts(info, RECEIVE_DATA);
5538
5539 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5540 usc_RCmd( info, RCmd_EnterHuntmode );
5541
5542 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5543 }
5544
5545 usc_OutReg( info, CCSR, 0x1020 );
5546
5547 info->rx_enabled = true;
5548
5549 } /* end of usc_start_receiver() */
5550
5551 /* usc_start_transmitter()
5552 *
5553 * Enable the USC transmitter and send a transmit frame if
5554 * one is loaded in the DMA buffers.
5555 *
5556 * Arguments: info pointer to device instance data
5557 * Return Value: None
5558 */
5559 static void usc_start_transmitter( struct mgsl_struct *info )
5560 {
5561 u32 phys_addr;
5562 unsigned int FrameSize;
5563
5564 if (debug_level >= DEBUG_LEVEL_ISR)
5565 printk("%s(%d):usc_start_transmitter(%s)\n",
5566 __FILE__,__LINE__, info->device_name );
5567
5568 if ( info->xmit_cnt ) {
5569
5570 /* If auto RTS enabled and RTS is inactive, then assert */
5571 /* RTS and set a flag indicating that the driver should */
5572 /* negate RTS when the transmission completes. */
5573
5574 info->drop_rts_on_tx_done = false;
5575
5576 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5577 usc_get_serial_signals( info );
5578 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5579 info->serial_signals |= SerialSignal_RTS;
5580 usc_set_serial_signals( info );
5581 info->drop_rts_on_tx_done = true;
5582 }
5583 }
5584
5585
5586 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5587 if ( !info->tx_active ) {
5588 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5589 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5590 usc_EnableInterrupts(info, TRANSMIT_DATA);
5591 usc_load_txfifo(info);
5592 }
5593 } else {
5594 /* Disable transmit DMA controller while programming. */
5595 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5596
5597 /* Transmit DMA buffer is loaded, so program USC */
5598 /* to send the frame contained in the buffers. */
5599
5600 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5601
5602 /* if operating in Raw sync mode, reset the rcc component
5603 * of the tx dma buffer entry, otherwise, the serial controller
5604 * will send a closing sync char after this count.
5605 */
5606 if ( info->params.mode == MGSL_MODE_RAW )
5607 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5608
5609 /* Program the Transmit Character Length Register (TCLR) */
5610 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5611 usc_OutReg( info, TCLR, (u16)FrameSize );
5612
5613 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5614
5615 /* Program the address of the 1st DMA Buffer Entry in linked list */
5616 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5617 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5618 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5619
5620 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5621 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5622 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5623
5624 if ( info->params.mode == MGSL_MODE_RAW &&
5625 info->num_tx_dma_buffers > 1 ) {
5626 /* When running external sync mode, attempt to 'stream' transmit */
5627 /* by filling tx dma buffers as they become available. To do this */
5628 /* we need to enable Tx DMA EOB Status interrupts : */
5629 /* */
5630 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5631 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5632
5633 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5634 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5635 }
5636
5637 /* Initialize Transmit DMA Channel */
5638 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5639
5640 usc_TCmd( info, TCmd_SendFrame );
5641
5642 mod_timer(&info->tx_timer, jiffies +
5643 msecs_to_jiffies(5000));
5644 }
5645 info->tx_active = true;
5646 }
5647
5648 if ( !info->tx_enabled ) {
5649 info->tx_enabled = true;
5650 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5651 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5652 else
5653 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5654 }
5655
5656 } /* end of usc_start_transmitter() */
5657
5658 /* usc_stop_transmitter()
5659 *
5660 * Stops the transmitter and DMA
5661 *
5662 * Arguments: info pointer to device isntance data
5663 * Return Value: None
5664 */
5665 static void usc_stop_transmitter( struct mgsl_struct *info )
5666 {
5667 if (debug_level >= DEBUG_LEVEL_ISR)
5668 printk("%s(%d):usc_stop_transmitter(%s)\n",
5669 __FILE__,__LINE__, info->device_name );
5670
5671 del_timer(&info->tx_timer);
5672
5673 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5674 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5675 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5676
5677 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5678 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5679 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5680
5681 info->tx_enabled = false;
5682 info->tx_active = false;
5683
5684 } /* end of usc_stop_transmitter() */
5685
5686 /* usc_load_txfifo()
5687 *
5688 * Fill the transmit FIFO until the FIFO is full or
5689 * there is no more data to load.
5690 *
5691 * Arguments: info pointer to device extension (instance data)
5692 * Return Value: None
5693 */
5694 static void usc_load_txfifo( struct mgsl_struct *info )
5695 {
5696 int Fifocount;
5697 u8 TwoBytes[2];
5698
5699 if ( !info->xmit_cnt && !info->x_char )
5700 return;
5701
5702 /* Select transmit FIFO status readback in TICR */
5703 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5704
5705 /* load the Transmit FIFO until FIFOs full or all data sent */
5706
5707 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5708 /* there is more space in the transmit FIFO and */
5709 /* there is more data in transmit buffer */
5710
5711 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5712 /* write a 16-bit word from transmit buffer to 16C32 */
5713
5714 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5715 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5716 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5717 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5718
5719 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5720
5721 info->xmit_cnt -= 2;
5722 info->icount.tx += 2;
5723 } else {
5724 /* only 1 byte left to transmit or 1 FIFO slot left */
5725
5726 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5727 info->io_base + CCAR );
5728
5729 if (info->x_char) {
5730 /* transmit pending high priority char */
5731 outw( info->x_char,info->io_base + CCAR );
5732 info->x_char = 0;
5733 } else {
5734 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5735 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5736 info->xmit_cnt--;
5737 }
5738 info->icount.tx++;
5739 }
5740 }
5741
5742 } /* end of usc_load_txfifo() */
5743
5744 /* usc_reset()
5745 *
5746 * Reset the adapter to a known state and prepare it for further use.
5747 *
5748 * Arguments: info pointer to device instance data
5749 * Return Value: None
5750 */
5751 static void usc_reset( struct mgsl_struct *info )
5752 {
5753 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5754 int i;
5755 u32 readval;
5756
5757 /* Set BIT30 of Misc Control Register */
5758 /* (Local Control Register 0x50) to force reset of USC. */
5759
5760 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5761 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5762
5763 info->misc_ctrl_value |= BIT30;
5764 *MiscCtrl = info->misc_ctrl_value;
5765
5766 /*
5767 * Force at least 170ns delay before clearing
5768 * reset bit. Each read from LCR takes at least
5769 * 30ns so 10 times for 300ns to be safe.
5770 */
5771 for(i=0;i<10;i++)
5772 readval = *MiscCtrl;
5773
5774 info->misc_ctrl_value &= ~BIT30;
5775 *MiscCtrl = info->misc_ctrl_value;
5776
5777 *LCR0BRDR = BUS_DESCRIPTOR(
5778 1, // Write Strobe Hold (0-3)
5779 2, // Write Strobe Delay (0-3)
5780 2, // Read Strobe Delay (0-3)
5781 0, // NWDD (Write data-data) (0-3)
5782 4, // NWAD (Write Addr-data) (0-31)
5783 0, // NXDA (Read/Write Data-Addr) (0-3)
5784 0, // NRDD (Read Data-Data) (0-3)
5785 5 // NRAD (Read Addr-Data) (0-31)
5786 );
5787 } else {
5788 /* do HW reset */
5789 outb( 0,info->io_base + 8 );
5790 }
5791
5792 info->mbre_bit = 0;
5793 info->loopback_bits = 0;
5794 info->usc_idle_mode = 0;
5795
5796 /*
5797 * Program the Bus Configuration Register (BCR)
5798 *
5799 * <15> 0 Don't use separate address
5800 * <14..6> 0 reserved
5801 * <5..4> 00 IAckmode = Default, don't care
5802 * <3> 1 Bus Request Totem Pole output
5803 * <2> 1 Use 16 Bit data bus
5804 * <1> 0 IRQ Totem Pole output
5805 * <0> 0 Don't Shift Right Addr
5806 *
5807 * 0000 0000 0000 1100 = 0x000c
5808 *
5809 * By writing to io_base + SDPIN the Wait/Ack pin is
5810 * programmed to work as a Wait pin.
5811 */
5812
5813 outw( 0x000c,info->io_base + SDPIN );
5814
5815
5816 outw( 0,info->io_base );
5817 outw( 0,info->io_base + CCAR );
5818
5819 /* select little endian byte ordering */
5820 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5821
5822
5823 /* Port Control Register (PCR)
5824 *
5825 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5826 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5827 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5828 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5829 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5830 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5831 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5832 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5833 *
5834 * 1111 0000 1111 0101 = 0xf0f5
5835 */
5836
5837 usc_OutReg( info, PCR, 0xf0f5 );
5838
5839
5840 /*
5841 * Input/Output Control Register
5842 *
5843 * <15..14> 00 CTS is active low input
5844 * <13..12> 00 DCD is active low input
5845 * <11..10> 00 TxREQ pin is input (DSR)
5846 * <9..8> 00 RxREQ pin is input (RI)
5847 * <7..6> 00 TxD is output (Transmit Data)
5848 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5849 * <2..0> 100 RxC is Output (drive with BRG0)
5850 *
5851 * 0000 0000 0000 0100 = 0x0004
5852 */
5853
5854 usc_OutReg( info, IOCR, 0x0004 );
5855
5856 } /* end of usc_reset() */
5857
5858 /* usc_set_async_mode()
5859 *
5860 * Program adapter for asynchronous communications.
5861 *
5862 * Arguments: info pointer to device instance data
5863 * Return Value: None
5864 */
5865 static void usc_set_async_mode( struct mgsl_struct *info )
5866 {
5867 u16 RegValue;
5868
5869 /* disable interrupts while programming USC */
5870 usc_DisableMasterIrqBit( info );
5871
5872 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5873 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5874
5875 usc_loopback_frame( info );
5876
5877 /* Channel mode Register (CMR)
5878 *
5879 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5880 * <13..12> 00 00 = 16X Clock
5881 * <11..8> 0000 Transmitter mode = Asynchronous
5882 * <7..6> 00 reserved?
5883 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5884 * <3..0> 0000 Receiver mode = Asynchronous
5885 *
5886 * 0000 0000 0000 0000 = 0x0
5887 */
5888
5889 RegValue = 0;
5890 if ( info->params.stop_bits != 1 )
5891 RegValue |= BIT14;
5892 usc_OutReg( info, CMR, RegValue );
5893
5894
5895 /* Receiver mode Register (RMR)
5896 *
5897 * <15..13> 000 encoding = None
5898 * <12..08> 00000 reserved (Sync Only)
5899 * <7..6> 00 Even parity
5900 * <5> 0 parity disabled
5901 * <4..2> 000 Receive Char Length = 8 bits
5902 * <1..0> 00 Disable Receiver
5903 *
5904 * 0000 0000 0000 0000 = 0x0
5905 */
5906
5907 RegValue = 0;
5908
5909 if ( info->params.data_bits != 8 )
5910 RegValue |= BIT4 | BIT3 | BIT2;
5911
5912 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5913 RegValue |= BIT5;
5914 if ( info->params.parity != ASYNC_PARITY_ODD )
5915 RegValue |= BIT6;
5916 }
5917
5918 usc_OutReg( info, RMR, RegValue );
5919
5920
5921 /* Set IRQ trigger level */
5922
5923 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5924
5925
5926 /* Receive Interrupt Control Register (RICR)
5927 *
5928 * <15..8> ? RxFIFO IRQ Request Level
5929 *
5930 * Note: For async mode the receive FIFO level must be set
5931 * to 0 to avoid the situation where the FIFO contains fewer bytes
5932 * than the trigger level and no more data is expected.
5933 *
5934 * <7> 0 Exited Hunt IA (Interrupt Arm)
5935 * <6> 0 Idle Received IA
5936 * <5> 0 Break/Abort IA
5937 * <4> 0 Rx Bound IA
5938 * <3> 0 Queued status reflects oldest byte in FIFO
5939 * <2> 0 Abort/PE IA
5940 * <1> 0 Rx Overrun IA
5941 * <0> 0 Select TC0 value for readback
5942 *
5943 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5944 */
5945
5946 usc_OutReg( info, RICR, 0x0000 );
5947
5948 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5949 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5950
5951
5952 /* Transmit mode Register (TMR)
5953 *
5954 * <15..13> 000 encoding = None
5955 * <12..08> 00000 reserved (Sync Only)
5956 * <7..6> 00 Transmit parity Even
5957 * <5> 0 Transmit parity Disabled
5958 * <4..2> 000 Tx Char Length = 8 bits
5959 * <1..0> 00 Disable Transmitter
5960 *
5961 * 0000 0000 0000 0000 = 0x0
5962 */
5963
5964 RegValue = 0;
5965
5966 if ( info->params.data_bits != 8 )
5967 RegValue |= BIT4 | BIT3 | BIT2;
5968
5969 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5970 RegValue |= BIT5;
5971 if ( info->params.parity != ASYNC_PARITY_ODD )
5972 RegValue |= BIT6;
5973 }
5974
5975 usc_OutReg( info, TMR, RegValue );
5976
5977 usc_set_txidle( info );
5978
5979
5980 /* Set IRQ trigger level */
5981
5982 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5983
5984
5985 /* Transmit Interrupt Control Register (TICR)
5986 *
5987 * <15..8> ? Transmit FIFO IRQ Level
5988 * <7> 0 Present IA (Interrupt Arm)
5989 * <6> 1 Idle Sent IA
5990 * <5> 0 Abort Sent IA
5991 * <4> 0 EOF/EOM Sent IA
5992 * <3> 0 CRC Sent IA
5993 * <2> 0 1 = Wait for SW Trigger to Start Frame
5994 * <1> 0 Tx Underrun IA
5995 * <0> 0 TC0 constant on read back
5996 *
5997 * 0000 0000 0100 0000 = 0x0040
5998 */
5999
6000 usc_OutReg( info, TICR, 0x1f40 );
6001
6002 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6003 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6004
6005 usc_enable_async_clock( info, info->params.data_rate );
6006
6007
6008 /* Channel Control/status Register (CCSR)
6009 *
6010 * <15> X RCC FIFO Overflow status (RO)
6011 * <14> X RCC FIFO Not Empty status (RO)
6012 * <13> 0 1 = Clear RCC FIFO (WO)
6013 * <12> X DPLL in Sync status (RO)
6014 * <11> X DPLL 2 Missed Clocks status (RO)
6015 * <10> X DPLL 1 Missed Clock status (RO)
6016 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6017 * <7> X SDLC Loop On status (RO)
6018 * <6> X SDLC Loop Send status (RO)
6019 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6020 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6021 * <1..0> 00 reserved
6022 *
6023 * 0000 0000 0010 0000 = 0x0020
6024 */
6025
6026 usc_OutReg( info, CCSR, 0x0020 );
6027
6028 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6029 RECEIVE_DATA + RECEIVE_STATUS );
6030
6031 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6032 RECEIVE_DATA + RECEIVE_STATUS );
6033
6034 usc_EnableMasterIrqBit( info );
6035
6036 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6037 /* Enable INTEN (Port 6, Bit12) */
6038 /* This connects the IRQ request signal to the ISA bus */
6039 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6040 }
6041
6042 if (info->params.loopback) {
6043 info->loopback_bits = 0x300;
6044 outw(0x0300, info->io_base + CCAR);
6045 }
6046
6047 } /* end of usc_set_async_mode() */
6048
6049 /* usc_loopback_frame()
6050 *
6051 * Loop back a small (2 byte) dummy SDLC frame.
6052 * Interrupts and DMA are NOT used. The purpose of this is to
6053 * clear any 'stale' status info left over from running in async mode.
6054 *
6055 * The 16C32 shows the strange behaviour of marking the 1st
6056 * received SDLC frame with a CRC error even when there is no
6057 * CRC error. To get around this a small dummy from of 2 bytes
6058 * is looped back when switching from async to sync mode.
6059 *
6060 * Arguments: info pointer to device instance data
6061 * Return Value: None
6062 */
6063 static void usc_loopback_frame( struct mgsl_struct *info )
6064 {
6065 int i;
6066 unsigned long oldmode = info->params.mode;
6067
6068 info->params.mode = MGSL_MODE_HDLC;
6069
6070 usc_DisableMasterIrqBit( info );
6071
6072 usc_set_sdlc_mode( info );
6073 usc_enable_loopback( info, 1 );
6074
6075 /* Write 16-bit Time Constant for BRG0 */
6076 usc_OutReg( info, TC0R, 0 );
6077
6078 /* Channel Control Register (CCR)
6079 *
6080 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6081 * <13> 0 Trigger Tx on SW Command Disabled
6082 * <12> 0 Flag Preamble Disabled
6083 * <11..10> 00 Preamble Length = 8-Bits
6084 * <9..8> 01 Preamble Pattern = flags
6085 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6086 * <5> 0 Trigger Rx on SW Command Disabled
6087 * <4..0> 0 reserved
6088 *
6089 * 0000 0001 0000 0000 = 0x0100
6090 */
6091
6092 usc_OutReg( info, CCR, 0x0100 );
6093
6094 /* SETUP RECEIVER */
6095 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6096 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6097
6098 /* SETUP TRANSMITTER */
6099 /* Program the Transmit Character Length Register (TCLR) */
6100 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6101 usc_OutReg( info, TCLR, 2 );
6102 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6103
6104 /* unlatch Tx status bits, and start transmit channel. */
6105 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6106 outw(0,info->io_base + DATAREG);
6107
6108 /* ENABLE TRANSMITTER */
6109 usc_TCmd( info, TCmd_SendFrame );
6110 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6111
6112 /* WAIT FOR RECEIVE COMPLETE */
6113 for (i=0 ; i<1000 ; i++)
6114 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
6115 break;
6116
6117 /* clear Internal Data loopback mode */
6118 usc_enable_loopback(info, 0);
6119
6120 usc_EnableMasterIrqBit(info);
6121
6122 info->params.mode = oldmode;
6123
6124 } /* end of usc_loopback_frame() */
6125
6126 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6127 *
6128 * Arguments: info pointer to adapter info structure
6129 * Return Value: None
6130 */
6131 static void usc_set_sync_mode( struct mgsl_struct *info )
6132 {
6133 usc_loopback_frame( info );
6134 usc_set_sdlc_mode( info );
6135
6136 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6137 /* Enable INTEN (Port 6, Bit12) */
6138 /* This connects the IRQ request signal to the ISA bus */
6139 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6140 }
6141
6142 usc_enable_aux_clock(info, info->params.clock_speed);
6143
6144 if (info->params.loopback)
6145 usc_enable_loopback(info,1);
6146
6147 } /* end of mgsl_set_sync_mode() */
6148
6149 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6150 *
6151 * Arguments: info pointer to device instance data
6152 * Return Value: None
6153 */
6154 static void usc_set_txidle( struct mgsl_struct *info )
6155 {
6156 u16 usc_idle_mode = IDLEMODE_FLAGS;
6157
6158 /* Map API idle mode to USC register bits */
6159
6160 switch( info->idle_mode ){
6161 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6162 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6163 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6164 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6165 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6166 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6167 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6168 }
6169
6170 info->usc_idle_mode = usc_idle_mode;
6171 //usc_OutReg(info, TCSR, usc_idle_mode);
6172 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6173 info->tcsr_value += usc_idle_mode;
6174 usc_OutReg(info, TCSR, info->tcsr_value);
6175
6176 /*
6177 * if SyncLink WAN adapter is running in external sync mode, the
6178 * transmitter has been set to Monosync in order to try to mimic
6179 * a true raw outbound bit stream. Monosync still sends an open/close
6180 * sync char at the start/end of a frame. Try to match those sync
6181 * patterns to the idle mode set here
6182 */
6183 if ( info->params.mode == MGSL_MODE_RAW ) {
6184 unsigned char syncpat = 0;
6185 switch( info->idle_mode ) {
6186 case HDLC_TXIDLE_FLAGS:
6187 syncpat = 0x7e;
6188 break;
6189 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6190 syncpat = 0x55;
6191 break;
6192 case HDLC_TXIDLE_ZEROS:
6193 case HDLC_TXIDLE_SPACE:
6194 syncpat = 0x00;
6195 break;
6196 case HDLC_TXIDLE_ONES:
6197 case HDLC_TXIDLE_MARK:
6198 syncpat = 0xff;
6199 break;
6200 case HDLC_TXIDLE_ALT_MARK_SPACE:
6201 syncpat = 0xaa;
6202 break;
6203 }
6204
6205 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6206 }
6207
6208 } /* end of usc_set_txidle() */
6209
6210 /* usc_get_serial_signals()
6211 *
6212 * Query the adapter for the state of the V24 status (input) signals.
6213 *
6214 * Arguments: info pointer to device instance data
6215 * Return Value: None
6216 */
6217 static void usc_get_serial_signals( struct mgsl_struct *info )
6218 {
6219 u16 status;
6220
6221 /* clear all serial signals except RTS and DTR */
6222 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
6223
6224 /* Read the Misc Interrupt status Register (MISR) to get */
6225 /* the V24 status signals. */
6226
6227 status = usc_InReg( info, MISR );
6228
6229 /* set serial signal bits to reflect MISR */
6230
6231 if ( status & MISCSTATUS_CTS )
6232 info->serial_signals |= SerialSignal_CTS;
6233
6234 if ( status & MISCSTATUS_DCD )
6235 info->serial_signals |= SerialSignal_DCD;
6236
6237 if ( status & MISCSTATUS_RI )
6238 info->serial_signals |= SerialSignal_RI;
6239
6240 if ( status & MISCSTATUS_DSR )
6241 info->serial_signals |= SerialSignal_DSR;
6242
6243 } /* end of usc_get_serial_signals() */
6244
6245 /* usc_set_serial_signals()
6246 *
6247 * Set the state of RTS and DTR based on contents of
6248 * serial_signals member of device extension.
6249 *
6250 * Arguments: info pointer to device instance data
6251 * Return Value: None
6252 */
6253 static void usc_set_serial_signals( struct mgsl_struct *info )
6254 {
6255 u16 Control;
6256 unsigned char V24Out = info->serial_signals;
6257
6258 /* get the current value of the Port Control Register (PCR) */
6259
6260 Control = usc_InReg( info, PCR );
6261
6262 if ( V24Out & SerialSignal_RTS )
6263 Control &= ~(BIT6);
6264 else
6265 Control |= BIT6;
6266
6267 if ( V24Out & SerialSignal_DTR )
6268 Control &= ~(BIT4);
6269 else
6270 Control |= BIT4;
6271
6272 usc_OutReg( info, PCR, Control );
6273
6274 } /* end of usc_set_serial_signals() */
6275
6276 /* usc_enable_async_clock()
6277 *
6278 * Enable the async clock at the specified frequency.
6279 *
6280 * Arguments: info pointer to device instance data
6281 * data_rate data rate of clock in bps
6282 * 0 disables the AUX clock.
6283 * Return Value: None
6284 */
6285 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6286 {
6287 if ( data_rate ) {
6288 /*
6289 * Clock mode Control Register (CMCR)
6290 *
6291 * <15..14> 00 counter 1 Disabled
6292 * <13..12> 00 counter 0 Disabled
6293 * <11..10> 11 BRG1 Input is TxC Pin
6294 * <9..8> 11 BRG0 Input is TxC Pin
6295 * <7..6> 01 DPLL Input is BRG1 Output
6296 * <5..3> 100 TxCLK comes from BRG0
6297 * <2..0> 100 RxCLK comes from BRG0
6298 *
6299 * 0000 1111 0110 0100 = 0x0f64
6300 */
6301
6302 usc_OutReg( info, CMCR, 0x0f64 );
6303
6304
6305 /*
6306 * Write 16-bit Time Constant for BRG0
6307 * Time Constant = (ClkSpeed / data_rate) - 1
6308 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6309 */
6310
6311 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6312 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6313 else
6314 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6315
6316
6317 /*
6318 * Hardware Configuration Register (HCR)
6319 * Clear Bit 1, BRG0 mode = Continuous
6320 * Set Bit 0 to enable BRG0.
6321 */
6322
6323 usc_OutReg( info, HCR,
6324 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6325
6326
6327 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6328
6329 usc_OutReg( info, IOCR,
6330 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6331 } else {
6332 /* data rate == 0 so turn off BRG0 */
6333 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6334 }
6335
6336 } /* end of usc_enable_async_clock() */
6337
6338 /*
6339 * Buffer Structures:
6340 *
6341 * Normal memory access uses virtual addresses that can make discontiguous
6342 * physical memory pages appear to be contiguous in the virtual address
6343 * space (the processors memory mapping handles the conversions).
6344 *
6345 * DMA transfers require physically contiguous memory. This is because
6346 * the DMA system controller and DMA bus masters deal with memory using
6347 * only physical addresses.
6348 *
6349 * This causes a problem under Windows NT when large DMA buffers are
6350 * needed. Fragmentation of the nonpaged pool prevents allocations of
6351 * physically contiguous buffers larger than the PAGE_SIZE.
6352 *
6353 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6354 * allows DMA transfers to physically discontiguous buffers. Information
6355 * about each data transfer buffer is contained in a memory structure
6356 * called a 'buffer entry'. A list of buffer entries is maintained
6357 * to track and control the use of the data transfer buffers.
6358 *
6359 * To support this strategy we will allocate sufficient PAGE_SIZE
6360 * contiguous memory buffers to allow for the total required buffer
6361 * space.
6362 *
6363 * The 16C32 accesses the list of buffer entries using Bus Master
6364 * DMA. Control information is read from the buffer entries by the
6365 * 16C32 to control data transfers. status information is written to
6366 * the buffer entries by the 16C32 to indicate the status of completed
6367 * transfers.
6368 *
6369 * The CPU writes control information to the buffer entries to control
6370 * the 16C32 and reads status information from the buffer entries to
6371 * determine information about received and transmitted frames.
6372 *
6373 * Because the CPU and 16C32 (adapter) both need simultaneous access
6374 * to the buffer entries, the buffer entry memory is allocated with
6375 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6376 * entry list to PAGE_SIZE.
6377 *
6378 * The actual data buffers on the other hand will only be accessed
6379 * by the CPU or the adapter but not by both simultaneously. This allows
6380 * Scatter/Gather packet based DMA procedures for using physically
6381 * discontiguous pages.
6382 */
6383
6384 /*
6385 * mgsl_reset_tx_dma_buffers()
6386 *
6387 * Set the count for all transmit buffers to 0 to indicate the
6388 * buffer is available for use and set the current buffer to the
6389 * first buffer. This effectively makes all buffers free and
6390 * discards any data in buffers.
6391 *
6392 * Arguments: info pointer to device instance data
6393 * Return Value: None
6394 */
6395 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6396 {
6397 unsigned int i;
6398
6399 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6400 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6401 }
6402
6403 info->current_tx_buffer = 0;
6404 info->start_tx_dma_buffer = 0;
6405 info->tx_dma_buffers_used = 0;
6406
6407 info->get_tx_holding_index = 0;
6408 info->put_tx_holding_index = 0;
6409 info->tx_holding_count = 0;
6410
6411 } /* end of mgsl_reset_tx_dma_buffers() */
6412
6413 /*
6414 * num_free_tx_dma_buffers()
6415 *
6416 * returns the number of free tx dma buffers available
6417 *
6418 * Arguments: info pointer to device instance data
6419 * Return Value: number of free tx dma buffers
6420 */
6421 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6422 {
6423 return info->tx_buffer_count - info->tx_dma_buffers_used;
6424 }
6425
6426 /*
6427 * mgsl_reset_rx_dma_buffers()
6428 *
6429 * Set the count for all receive buffers to DMABUFFERSIZE
6430 * and set the current buffer to the first buffer. This effectively
6431 * makes all buffers free and discards any data in buffers.
6432 *
6433 * Arguments: info pointer to device instance data
6434 * Return Value: None
6435 */
6436 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6437 {
6438 unsigned int i;
6439
6440 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6441 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6442 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6443 // info->rx_buffer_list[i].status = 0;
6444 }
6445
6446 info->current_rx_buffer = 0;
6447
6448 } /* end of mgsl_reset_rx_dma_buffers() */
6449
6450 /*
6451 * mgsl_free_rx_frame_buffers()
6452 *
6453 * Free the receive buffers used by a received SDLC
6454 * frame such that the buffers can be reused.
6455 *
6456 * Arguments:
6457 *
6458 * info pointer to device instance data
6459 * StartIndex index of 1st receive buffer of frame
6460 * EndIndex index of last receive buffer of frame
6461 *
6462 * Return Value: None
6463 */
6464 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6465 {
6466 bool Done = false;
6467 DMABUFFERENTRY *pBufEntry;
6468 unsigned int Index;
6469
6470 /* Starting with 1st buffer entry of the frame clear the status */
6471 /* field and set the count field to DMA Buffer Size. */
6472
6473 Index = StartIndex;
6474
6475 while( !Done ) {
6476 pBufEntry = &(info->rx_buffer_list[Index]);
6477
6478 if ( Index == EndIndex ) {
6479 /* This is the last buffer of the frame! */
6480 Done = true;
6481 }
6482
6483 /* reset current buffer for reuse */
6484 // pBufEntry->status = 0;
6485 // pBufEntry->count = DMABUFFERSIZE;
6486 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6487
6488 /* advance to next buffer entry in linked list */
6489 Index++;
6490 if ( Index == info->rx_buffer_count )
6491 Index = 0;
6492 }
6493
6494 /* set current buffer to next buffer after last buffer of frame */
6495 info->current_rx_buffer = Index;
6496
6497 } /* end of free_rx_frame_buffers() */
6498
6499 /* mgsl_get_rx_frame()
6500 *
6501 * This function attempts to return a received SDLC frame from the
6502 * receive DMA buffers. Only frames received without errors are returned.
6503 *
6504 * Arguments: info pointer to device extension
6505 * Return Value: true if frame returned, otherwise false
6506 */
6507 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6508 {
6509 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6510 unsigned short status;
6511 DMABUFFERENTRY *pBufEntry;
6512 unsigned int framesize = 0;
6513 bool ReturnCode = false;
6514 unsigned long flags;
6515 struct tty_struct *tty = info->port.tty;
6516 bool return_frame = false;
6517
6518 /*
6519 * current_rx_buffer points to the 1st buffer of the next available
6520 * receive frame. To find the last buffer of the frame look for
6521 * a non-zero status field in the buffer entries. (The status
6522 * field is set by the 16C32 after completing a receive frame.
6523 */
6524
6525 StartIndex = EndIndex = info->current_rx_buffer;
6526
6527 while( !info->rx_buffer_list[EndIndex].status ) {
6528 /*
6529 * If the count field of the buffer entry is non-zero then
6530 * this buffer has not been used. (The 16C32 clears the count
6531 * field when it starts using the buffer.) If an unused buffer
6532 * is encountered then there are no frames available.
6533 */
6534
6535 if ( info->rx_buffer_list[EndIndex].count )
6536 goto Cleanup;
6537
6538 /* advance to next buffer entry in linked list */
6539 EndIndex++;
6540 if ( EndIndex == info->rx_buffer_count )
6541 EndIndex = 0;
6542
6543 /* if entire list searched then no frame available */
6544 if ( EndIndex == StartIndex ) {
6545 /* If this occurs then something bad happened,
6546 * all buffers have been 'used' but none mark
6547 * the end of a frame. Reset buffers and receiver.
6548 */
6549
6550 if ( info->rx_enabled ){
6551 spin_lock_irqsave(&info->irq_spinlock,flags);
6552 usc_start_receiver(info);
6553 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6554 }
6555 goto Cleanup;
6556 }
6557 }
6558
6559
6560 /* check status of receive frame */
6561
6562 status = info->rx_buffer_list[EndIndex].status;
6563
6564 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6565 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6566 if ( status & RXSTATUS_SHORT_FRAME )
6567 info->icount.rxshort++;
6568 else if ( status & RXSTATUS_ABORT )
6569 info->icount.rxabort++;
6570 else if ( status & RXSTATUS_OVERRUN )
6571 info->icount.rxover++;
6572 else {
6573 info->icount.rxcrc++;
6574 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6575 return_frame = true;
6576 }
6577 framesize = 0;
6578 #if SYNCLINK_GENERIC_HDLC
6579 {
6580 info->netdev->stats.rx_errors++;
6581 info->netdev->stats.rx_frame_errors++;
6582 }
6583 #endif
6584 } else
6585 return_frame = true;
6586
6587 if ( return_frame ) {
6588 /* receive frame has no errors, get frame size.
6589 * The frame size is the starting value of the RCC (which was
6590 * set to 0xffff) minus the ending value of the RCC (decremented
6591 * once for each receive character) minus 2 for the 16-bit CRC.
6592 */
6593
6594 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6595
6596 /* adjust frame size for CRC if any */
6597 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6598 framesize -= 2;
6599 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6600 framesize -= 4;
6601 }
6602
6603 if ( debug_level >= DEBUG_LEVEL_BH )
6604 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6605 __FILE__,__LINE__,info->device_name,status,framesize);
6606
6607 if ( debug_level >= DEBUG_LEVEL_DATA )
6608 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6609 min_t(int, framesize, DMABUFFERSIZE),0);
6610
6611 if (framesize) {
6612 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6613 ((framesize+1) > info->max_frame_size) ) ||
6614 (framesize > info->max_frame_size) )
6615 info->icount.rxlong++;
6616 else {
6617 /* copy dma buffer(s) to contiguous intermediate buffer */
6618 int copy_count = framesize;
6619 int index = StartIndex;
6620 unsigned char *ptmp = info->intermediate_rxbuffer;
6621
6622 if ( !(status & RXSTATUS_CRC_ERROR))
6623 info->icount.rxok++;
6624
6625 while(copy_count) {
6626 int partial_count;
6627 if ( copy_count > DMABUFFERSIZE )
6628 partial_count = DMABUFFERSIZE;
6629 else
6630 partial_count = copy_count;
6631
6632 pBufEntry = &(info->rx_buffer_list[index]);
6633 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6634 ptmp += partial_count;
6635 copy_count -= partial_count;
6636
6637 if ( ++index == info->rx_buffer_count )
6638 index = 0;
6639 }
6640
6641 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6642 ++framesize;
6643 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6644 RX_CRC_ERROR :
6645 RX_OK);
6646
6647 if ( debug_level >= DEBUG_LEVEL_DATA )
6648 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6649 __FILE__,__LINE__,info->device_name,
6650 *ptmp);
6651 }
6652
6653 #if SYNCLINK_GENERIC_HDLC
6654 if (info->netcount)
6655 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6656 else
6657 #endif
6658 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6659 }
6660 }
6661 /* Free the buffers used by this frame. */
6662 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6663
6664 ReturnCode = true;
6665
6666 Cleanup:
6667
6668 if ( info->rx_enabled && info->rx_overflow ) {
6669 /* The receiver needs to restarted because of
6670 * a receive overflow (buffer or FIFO). If the
6671 * receive buffers are now empty, then restart receiver.
6672 */
6673
6674 if ( !info->rx_buffer_list[EndIndex].status &&
6675 info->rx_buffer_list[EndIndex].count ) {
6676 spin_lock_irqsave(&info->irq_spinlock,flags);
6677 usc_start_receiver(info);
6678 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6679 }
6680 }
6681
6682 return ReturnCode;
6683
6684 } /* end of mgsl_get_rx_frame() */
6685
6686 /* mgsl_get_raw_rx_frame()
6687 *
6688 * This function attempts to return a received frame from the
6689 * receive DMA buffers when running in external loop mode. In this mode,
6690 * we will return at most one DMABUFFERSIZE frame to the application.
6691 * The USC receiver is triggering off of DCD going active to start a new
6692 * frame, and DCD going inactive to terminate the frame (similar to
6693 * processing a closing flag character).
6694 *
6695 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6696 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6697 * status field and the RCC field will indicate the length of the
6698 * entire received frame. We take this RCC field and get the modulus
6699 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6700 * last Rx DMA buffer and return that last portion of the frame.
6701 *
6702 * Arguments: info pointer to device extension
6703 * Return Value: true if frame returned, otherwise false
6704 */
6705 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6706 {
6707 unsigned int CurrentIndex, NextIndex;
6708 unsigned short status;
6709 DMABUFFERENTRY *pBufEntry;
6710 unsigned int framesize = 0;
6711 bool ReturnCode = false;
6712 unsigned long flags;
6713 struct tty_struct *tty = info->port.tty;
6714
6715 /*
6716 * current_rx_buffer points to the 1st buffer of the next available
6717 * receive frame. The status field is set by the 16C32 after
6718 * completing a receive frame. If the status field of this buffer
6719 * is zero, either the USC is still filling this buffer or this
6720 * is one of a series of buffers making up a received frame.
6721 *
6722 * If the count field of this buffer is zero, the USC is either
6723 * using this buffer or has used this buffer. Look at the count
6724 * field of the next buffer. If that next buffer's count is
6725 * non-zero, the USC is still actively using the current buffer.
6726 * Otherwise, if the next buffer's count field is zero, the
6727 * current buffer is complete and the USC is using the next
6728 * buffer.
6729 */
6730 CurrentIndex = NextIndex = info->current_rx_buffer;
6731 ++NextIndex;
6732 if ( NextIndex == info->rx_buffer_count )
6733 NextIndex = 0;
6734
6735 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6736 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6737 info->rx_buffer_list[NextIndex].count == 0)) {
6738 /*
6739 * Either the status field of this dma buffer is non-zero
6740 * (indicating the last buffer of a receive frame) or the next
6741 * buffer is marked as in use -- implying this buffer is complete
6742 * and an intermediate buffer for this received frame.
6743 */
6744
6745 status = info->rx_buffer_list[CurrentIndex].status;
6746
6747 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6748 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6749 if ( status & RXSTATUS_SHORT_FRAME )
6750 info->icount.rxshort++;
6751 else if ( status & RXSTATUS_ABORT )
6752 info->icount.rxabort++;
6753 else if ( status & RXSTATUS_OVERRUN )
6754 info->icount.rxover++;
6755 else
6756 info->icount.rxcrc++;
6757 framesize = 0;
6758 } else {
6759 /*
6760 * A receive frame is available, get frame size and status.
6761 *
6762 * The frame size is the starting value of the RCC (which was
6763 * set to 0xffff) minus the ending value of the RCC (decremented
6764 * once for each receive character) minus 2 or 4 for the 16-bit
6765 * or 32-bit CRC.
6766 *
6767 * If the status field is zero, this is an intermediate buffer.
6768 * It's size is 4K.
6769 *
6770 * If the DMA Buffer Entry's Status field is non-zero, the
6771 * receive operation completed normally (ie: DCD dropped). The
6772 * RCC field is valid and holds the received frame size.
6773 * It is possible that the RCC field will be zero on a DMA buffer
6774 * entry with a non-zero status. This can occur if the total
6775 * frame size (number of bytes between the time DCD goes active
6776 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6777 * case the 16C32 has underrun on the RCC count and appears to
6778 * stop updating this counter to let us know the actual received
6779 * frame size. If this happens (non-zero status and zero RCC),
6780 * simply return the entire RxDMA Buffer
6781 */
6782 if ( status ) {
6783 /*
6784 * In the event that the final RxDMA Buffer is
6785 * terminated with a non-zero status and the RCC
6786 * field is zero, we interpret this as the RCC
6787 * having underflowed (received frame > 65535 bytes).
6788 *
6789 * Signal the event to the user by passing back
6790 * a status of RxStatus_CrcError returning the full
6791 * buffer and let the app figure out what data is
6792 * actually valid
6793 */
6794 if ( info->rx_buffer_list[CurrentIndex].rcc )
6795 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6796 else
6797 framesize = DMABUFFERSIZE;
6798 }
6799 else
6800 framesize = DMABUFFERSIZE;
6801 }
6802
6803 if ( framesize > DMABUFFERSIZE ) {
6804 /*
6805 * if running in raw sync mode, ISR handler for
6806 * End Of Buffer events terminates all buffers at 4K.
6807 * If this frame size is said to be >4K, get the
6808 * actual number of bytes of the frame in this buffer.
6809 */
6810 framesize = framesize % DMABUFFERSIZE;
6811 }
6812
6813
6814 if ( debug_level >= DEBUG_LEVEL_BH )
6815 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6816 __FILE__,__LINE__,info->device_name,status,framesize);
6817
6818 if ( debug_level >= DEBUG_LEVEL_DATA )
6819 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6820 min_t(int, framesize, DMABUFFERSIZE),0);
6821
6822 if (framesize) {
6823 /* copy dma buffer(s) to contiguous intermediate buffer */
6824 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6825
6826 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6827 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6828 info->icount.rxok++;
6829
6830 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6831 }
6832
6833 /* Free the buffers used by this frame. */
6834 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6835
6836 ReturnCode = true;
6837 }
6838
6839
6840 if ( info->rx_enabled && info->rx_overflow ) {
6841 /* The receiver needs to restarted because of
6842 * a receive overflow (buffer or FIFO). If the
6843 * receive buffers are now empty, then restart receiver.
6844 */
6845
6846 if ( !info->rx_buffer_list[CurrentIndex].status &&
6847 info->rx_buffer_list[CurrentIndex].count ) {
6848 spin_lock_irqsave(&info->irq_spinlock,flags);
6849 usc_start_receiver(info);
6850 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6851 }
6852 }
6853
6854 return ReturnCode;
6855
6856 } /* end of mgsl_get_raw_rx_frame() */
6857
6858 /* mgsl_load_tx_dma_buffer()
6859 *
6860 * Load the transmit DMA buffer with the specified data.
6861 *
6862 * Arguments:
6863 *
6864 * info pointer to device extension
6865 * Buffer pointer to buffer containing frame to load
6866 * BufferSize size in bytes of frame in Buffer
6867 *
6868 * Return Value: None
6869 */
6870 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6871 const char *Buffer, unsigned int BufferSize)
6872 {
6873 unsigned short Copycount;
6874 unsigned int i = 0;
6875 DMABUFFERENTRY *pBufEntry;
6876
6877 if ( debug_level >= DEBUG_LEVEL_DATA )
6878 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6879
6880 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6881 /* set CMR:13 to start transmit when
6882 * next GoAhead (abort) is received
6883 */
6884 info->cmr_value |= BIT13;
6885 }
6886
6887 /* begin loading the frame in the next available tx dma
6888 * buffer, remember it's starting location for setting
6889 * up tx dma operation
6890 */
6891 i = info->current_tx_buffer;
6892 info->start_tx_dma_buffer = i;
6893
6894 /* Setup the status and RCC (Frame Size) fields of the 1st */
6895 /* buffer entry in the transmit DMA buffer list. */
6896
6897 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6898 info->tx_buffer_list[i].rcc = BufferSize;
6899 info->tx_buffer_list[i].count = BufferSize;
6900
6901 /* Copy frame data from 1st source buffer to the DMA buffers. */
6902 /* The frame data may span multiple DMA buffers. */
6903
6904 while( BufferSize ){
6905 /* Get a pointer to next DMA buffer entry. */
6906 pBufEntry = &info->tx_buffer_list[i++];
6907
6908 if ( i == info->tx_buffer_count )
6909 i=0;
6910
6911 /* Calculate the number of bytes that can be copied from */
6912 /* the source buffer to this DMA buffer. */
6913 if ( BufferSize > DMABUFFERSIZE )
6914 Copycount = DMABUFFERSIZE;
6915 else
6916 Copycount = BufferSize;
6917
6918 /* Actually copy data from source buffer to DMA buffer. */
6919 /* Also set the data count for this individual DMA buffer. */
6920 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6921 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6922 else
6923 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6924
6925 pBufEntry->count = Copycount;
6926
6927 /* Advance source pointer and reduce remaining data count. */
6928 Buffer += Copycount;
6929 BufferSize -= Copycount;
6930
6931 ++info->tx_dma_buffers_used;
6932 }
6933
6934 /* remember next available tx dma buffer */
6935 info->current_tx_buffer = i;
6936
6937 } /* end of mgsl_load_tx_dma_buffer() */
6938
6939 /*
6940 * mgsl_register_test()
6941 *
6942 * Performs a register test of the 16C32.
6943 *
6944 * Arguments: info pointer to device instance data
6945 * Return Value: true if test passed, otherwise false
6946 */
6947 static bool mgsl_register_test( struct mgsl_struct *info )
6948 {
6949 static unsigned short BitPatterns[] =
6950 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6951 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6952 unsigned int i;
6953 bool rc = true;
6954 unsigned long flags;
6955
6956 spin_lock_irqsave(&info->irq_spinlock,flags);
6957 usc_reset(info);
6958
6959 /* Verify the reset state of some registers. */
6960
6961 if ( (usc_InReg( info, SICR ) != 0) ||
6962 (usc_InReg( info, IVR ) != 0) ||
6963 (usc_InDmaReg( info, DIVR ) != 0) ){
6964 rc = false;
6965 }
6966
6967 if ( rc ){
6968 /* Write bit patterns to various registers but do it out of */
6969 /* sync, then read back and verify values. */
6970
6971 for ( i = 0 ; i < Patterncount ; i++ ) {
6972 usc_OutReg( info, TC0R, BitPatterns[i] );
6973 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6974 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6975 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6976 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6977 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6978
6979 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6980 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6981 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6982 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6983 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6984 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6985 rc = false;
6986 break;
6987 }
6988 }
6989 }
6990
6991 usc_reset(info);
6992 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6993
6994 return rc;
6995
6996 } /* end of mgsl_register_test() */
6997
6998 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6999 *
7000 * Arguments: info pointer to device instance data
7001 * Return Value: true if test passed, otherwise false
7002 */
7003 static bool mgsl_irq_test( struct mgsl_struct *info )
7004 {
7005 unsigned long EndTime;
7006 unsigned long flags;
7007
7008 spin_lock_irqsave(&info->irq_spinlock,flags);
7009 usc_reset(info);
7010
7011 /*
7012 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7013 * The ISR sets irq_occurred to true.
7014 */
7015
7016 info->irq_occurred = false;
7017
7018 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7019 /* Enable INTEN (Port 6, Bit12) */
7020 /* This connects the IRQ request signal to the ISA bus */
7021 /* on the ISA adapter. This has no effect for the PCI adapter */
7022 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7023
7024 usc_EnableMasterIrqBit(info);
7025 usc_EnableInterrupts(info, IO_PIN);
7026 usc_ClearIrqPendingBits(info, IO_PIN);
7027
7028 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7029 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7030
7031 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7032
7033 EndTime=100;
7034 while( EndTime-- && !info->irq_occurred ) {
7035 msleep_interruptible(10);
7036 }
7037
7038 spin_lock_irqsave(&info->irq_spinlock,flags);
7039 usc_reset(info);
7040 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7041
7042 return info->irq_occurred;
7043
7044 } /* end of mgsl_irq_test() */
7045
7046 /* mgsl_dma_test()
7047 *
7048 * Perform a DMA test of the 16C32. A small frame is
7049 * transmitted via DMA from a transmit buffer to a receive buffer
7050 * using single buffer DMA mode.
7051 *
7052 * Arguments: info pointer to device instance data
7053 * Return Value: true if test passed, otherwise false
7054 */
7055 static bool mgsl_dma_test( struct mgsl_struct *info )
7056 {
7057 unsigned short FifoLevel;
7058 unsigned long phys_addr;
7059 unsigned int FrameSize;
7060 unsigned int i;
7061 char *TmpPtr;
7062 bool rc = true;
7063 unsigned short status=0;
7064 unsigned long EndTime;
7065 unsigned long flags;
7066 MGSL_PARAMS tmp_params;
7067
7068 /* save current port options */
7069 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7070 /* load default port options */
7071 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7072
7073 #define TESTFRAMESIZE 40
7074
7075 spin_lock_irqsave(&info->irq_spinlock,flags);
7076
7077 /* setup 16C32 for SDLC DMA transfer mode */
7078
7079 usc_reset(info);
7080 usc_set_sdlc_mode(info);
7081 usc_enable_loopback(info,1);
7082
7083 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7084 * field of the buffer entry after fetching buffer address. This
7085 * way we can detect a DMA failure for a DMA read (which should be
7086 * non-destructive to system memory) before we try and write to
7087 * memory (where a failure could corrupt system memory).
7088 */
7089
7090 /* Receive DMA mode Register (RDMR)
7091 *
7092 * <15..14> 11 DMA mode = Linked List Buffer mode
7093 * <13> 1 RSBinA/L = store Rx status Block in List entry
7094 * <12> 0 1 = Clear count of List Entry after fetching
7095 * <11..10> 00 Address mode = Increment
7096 * <9> 1 Terminate Buffer on RxBound
7097 * <8> 0 Bus Width = 16bits
7098 * <7..0> ? status Bits (write as 0s)
7099 *
7100 * 1110 0010 0000 0000 = 0xe200
7101 */
7102
7103 usc_OutDmaReg( info, RDMR, 0xe200 );
7104
7105 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7106
7107
7108 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7109
7110 FrameSize = TESTFRAMESIZE;
7111
7112 /* setup 1st transmit buffer entry: */
7113 /* with frame size and transmit control word */
7114
7115 info->tx_buffer_list[0].count = FrameSize;
7116 info->tx_buffer_list[0].rcc = FrameSize;
7117 info->tx_buffer_list[0].status = 0x4000;
7118
7119 /* build a transmit frame in 1st transmit DMA buffer */
7120
7121 TmpPtr = info->tx_buffer_list[0].virt_addr;
7122 for (i = 0; i < FrameSize; i++ )
7123 *TmpPtr++ = i;
7124
7125 /* setup 1st receive buffer entry: */
7126 /* clear status, set max receive buffer size */
7127
7128 info->rx_buffer_list[0].status = 0;
7129 info->rx_buffer_list[0].count = FrameSize + 4;
7130
7131 /* zero out the 1st receive buffer */
7132
7133 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7134
7135 /* Set count field of next buffer entries to prevent */
7136 /* 16C32 from using buffers after the 1st one. */
7137
7138 info->tx_buffer_list[1].count = 0;
7139 info->rx_buffer_list[1].count = 0;
7140
7141
7142 /***************************/
7143 /* Program 16C32 receiver. */
7144 /***************************/
7145
7146 spin_lock_irqsave(&info->irq_spinlock,flags);
7147
7148 /* setup DMA transfers */
7149 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7150
7151 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7152 phys_addr = info->rx_buffer_list[0].phys_entry;
7153 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7154 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7155
7156 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7157 usc_InDmaReg( info, RDMR );
7158 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7159
7160 /* Enable Receiver (RMR <1..0> = 10) */
7161 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7162
7163 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7164
7165
7166 /*************************************************************/
7167 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7168 /*************************************************************/
7169
7170 /* Wait 100ms for interrupt. */
7171 EndTime = jiffies + msecs_to_jiffies(100);
7172
7173 for(;;) {
7174 if (time_after(jiffies, EndTime)) {
7175 rc = false;
7176 break;
7177 }
7178
7179 spin_lock_irqsave(&info->irq_spinlock,flags);
7180 status = usc_InDmaReg( info, RDMR );
7181 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7182
7183 if ( !(status & BIT4) && (status & BIT5) ) {
7184 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7185 /* BUSY (BIT 5) is active (channel still active). */
7186 /* This means the buffer entry read has completed. */
7187 break;
7188 }
7189 }
7190
7191
7192 /******************************/
7193 /* Program 16C32 transmitter. */
7194 /******************************/
7195
7196 spin_lock_irqsave(&info->irq_spinlock,flags);
7197
7198 /* Program the Transmit Character Length Register (TCLR) */
7199 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7200
7201 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7202 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7203
7204 /* Program the address of the 1st DMA Buffer Entry in linked list */
7205
7206 phys_addr = info->tx_buffer_list[0].phys_entry;
7207 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7208 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7209
7210 /* unlatch Tx status bits, and start transmit channel. */
7211
7212 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7213 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7214
7215 /* wait for DMA controller to fill transmit FIFO */
7216
7217 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7218
7219 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7220
7221
7222 /**********************************/
7223 /* WAIT FOR TRANSMIT FIFO TO FILL */
7224 /**********************************/
7225
7226 /* Wait 100ms */
7227 EndTime = jiffies + msecs_to_jiffies(100);
7228
7229 for(;;) {
7230 if (time_after(jiffies, EndTime)) {
7231 rc = false;
7232 break;
7233 }
7234
7235 spin_lock_irqsave(&info->irq_spinlock,flags);
7236 FifoLevel = usc_InReg(info, TICR) >> 8;
7237 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7238
7239 if ( FifoLevel < 16 )
7240 break;
7241 else
7242 if ( FrameSize < 32 ) {
7243 /* This frame is smaller than the entire transmit FIFO */
7244 /* so wait for the entire frame to be loaded. */
7245 if ( FifoLevel <= (32 - FrameSize) )
7246 break;
7247 }
7248 }
7249
7250
7251 if ( rc )
7252 {
7253 /* Enable 16C32 transmitter. */
7254
7255 spin_lock_irqsave(&info->irq_spinlock,flags);
7256
7257 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7258 usc_TCmd( info, TCmd_SendFrame );
7259 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7260
7261 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7262
7263
7264 /******************************/
7265 /* WAIT FOR TRANSMIT COMPLETE */
7266 /******************************/
7267
7268 /* Wait 100ms */
7269 EndTime = jiffies + msecs_to_jiffies(100);
7270
7271 /* While timer not expired wait for transmit complete */
7272
7273 spin_lock_irqsave(&info->irq_spinlock,flags);
7274 status = usc_InReg( info, TCSR );
7275 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276
7277 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
7278 if (time_after(jiffies, EndTime)) {
7279 rc = false;
7280 break;
7281 }
7282
7283 spin_lock_irqsave(&info->irq_spinlock,flags);
7284 status = usc_InReg( info, TCSR );
7285 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7286 }
7287 }
7288
7289
7290 if ( rc ){
7291 /* CHECK FOR TRANSMIT ERRORS */
7292 if ( status & (BIT5 | BIT1) )
7293 rc = false;
7294 }
7295
7296 if ( rc ) {
7297 /* WAIT FOR RECEIVE COMPLETE */
7298
7299 /* Wait 100ms */
7300 EndTime = jiffies + msecs_to_jiffies(100);
7301
7302 /* Wait for 16C32 to write receive status to buffer entry. */
7303 status=info->rx_buffer_list[0].status;
7304 while ( status == 0 ) {
7305 if (time_after(jiffies, EndTime)) {
7306 rc = false;
7307 break;
7308 }
7309 status=info->rx_buffer_list[0].status;
7310 }
7311 }
7312
7313
7314 if ( rc ) {
7315 /* CHECK FOR RECEIVE ERRORS */
7316 status = info->rx_buffer_list[0].status;
7317
7318 if ( status & (BIT8 | BIT3 | BIT1) ) {
7319 /* receive error has occurred */
7320 rc = false;
7321 } else {
7322 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7323 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7324 rc = false;
7325 }
7326 }
7327 }
7328
7329 spin_lock_irqsave(&info->irq_spinlock,flags);
7330 usc_reset( info );
7331 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7332
7333 /* restore current port options */
7334 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7335
7336 return rc;
7337
7338 } /* end of mgsl_dma_test() */
7339
7340 /* mgsl_adapter_test()
7341 *
7342 * Perform the register, IRQ, and DMA tests for the 16C32.
7343 *
7344 * Arguments: info pointer to device instance data
7345 * Return Value: 0 if success, otherwise -ENODEV
7346 */
7347 static int mgsl_adapter_test( struct mgsl_struct *info )
7348 {
7349 if ( debug_level >= DEBUG_LEVEL_INFO )
7350 printk( "%s(%d):Testing device %s\n",
7351 __FILE__,__LINE__,info->device_name );
7352
7353 if ( !mgsl_register_test( info ) ) {
7354 info->init_error = DiagStatus_AddressFailure;
7355 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7356 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7357 return -ENODEV;
7358 }
7359
7360 if ( !mgsl_irq_test( info ) ) {
7361 info->init_error = DiagStatus_IrqFailure;
7362 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7363 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7364 return -ENODEV;
7365 }
7366
7367 if ( !mgsl_dma_test( info ) ) {
7368 info->init_error = DiagStatus_DmaFailure;
7369 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7370 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7371 return -ENODEV;
7372 }
7373
7374 if ( debug_level >= DEBUG_LEVEL_INFO )
7375 printk( "%s(%d):device %s passed diagnostics\n",
7376 __FILE__,__LINE__,info->device_name );
7377
7378 return 0;
7379
7380 } /* end of mgsl_adapter_test() */
7381
7382 /* mgsl_memory_test()
7383 *
7384 * Test the shared memory on a PCI adapter.
7385 *
7386 * Arguments: info pointer to device instance data
7387 * Return Value: true if test passed, otherwise false
7388 */
7389 static bool mgsl_memory_test( struct mgsl_struct *info )
7390 {
7391 static unsigned long BitPatterns[] =
7392 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7393 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7394 unsigned long i;
7395 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7396 unsigned long * TestAddr;
7397
7398 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7399 return true;
7400
7401 TestAddr = (unsigned long *)info->memory_base;
7402
7403 /* Test data lines with test pattern at one location. */
7404
7405 for ( i = 0 ; i < Patterncount ; i++ ) {
7406 *TestAddr = BitPatterns[i];
7407 if ( *TestAddr != BitPatterns[i] )
7408 return false;
7409 }
7410
7411 /* Test address lines with incrementing pattern over */
7412 /* entire address range. */
7413
7414 for ( i = 0 ; i < TestLimit ; i++ ) {
7415 *TestAddr = i * 4;
7416 TestAddr++;
7417 }
7418
7419 TestAddr = (unsigned long *)info->memory_base;
7420
7421 for ( i = 0 ; i < TestLimit ; i++ ) {
7422 if ( *TestAddr != i * 4 )
7423 return false;
7424 TestAddr++;
7425 }
7426
7427 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7428
7429 return true;
7430
7431 } /* End Of mgsl_memory_test() */
7432
7433
7434 /* mgsl_load_pci_memory()
7435 *
7436 * Load a large block of data into the PCI shared memory.
7437 * Use this instead of memcpy() or memmove() to move data
7438 * into the PCI shared memory.
7439 *
7440 * Notes:
7441 *
7442 * This function prevents the PCI9050 interface chip from hogging
7443 * the adapter local bus, which can starve the 16C32 by preventing
7444 * 16C32 bus master cycles.
7445 *
7446 * The PCI9050 documentation says that the 9050 will always release
7447 * control of the local bus after completing the current read
7448 * or write operation.
7449 *
7450 * It appears that as long as the PCI9050 write FIFO is full, the
7451 * PCI9050 treats all of the writes as a single burst transaction
7452 * and will not release the bus. This causes DMA latency problems
7453 * at high speeds when copying large data blocks to the shared
7454 * memory.
7455 *
7456 * This function in effect, breaks the a large shared memory write
7457 * into multiple transations by interleaving a shared memory read
7458 * which will flush the write FIFO and 'complete' the write
7459 * transation. This allows any pending DMA request to gain control
7460 * of the local bus in a timely fasion.
7461 *
7462 * Arguments:
7463 *
7464 * TargetPtr pointer to target address in PCI shared memory
7465 * SourcePtr pointer to source buffer for data
7466 * count count in bytes of data to copy
7467 *
7468 * Return Value: None
7469 */
7470 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7471 unsigned short count )
7472 {
7473 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7474 #define PCI_LOAD_INTERVAL 64
7475
7476 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7477 unsigned short Index;
7478 unsigned long Dummy;
7479
7480 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7481 {
7482 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7483 Dummy = *((volatile unsigned long *)TargetPtr);
7484 TargetPtr += PCI_LOAD_INTERVAL;
7485 SourcePtr += PCI_LOAD_INTERVAL;
7486 }
7487
7488 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7489
7490 } /* End Of mgsl_load_pci_memory() */
7491
7492 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7493 {
7494 int i;
7495 int linecount;
7496 if (xmit)
7497 printk("%s tx data:\n",info->device_name);
7498 else
7499 printk("%s rx data:\n",info->device_name);
7500
7501 while(count) {
7502 if (count > 16)
7503 linecount = 16;
7504 else
7505 linecount = count;
7506
7507 for(i=0;i<linecount;i++)
7508 printk("%02X ",(unsigned char)data[i]);
7509 for(;i<17;i++)
7510 printk(" ");
7511 for(i=0;i<linecount;i++) {
7512 if (data[i]>=040 && data[i]<=0176)
7513 printk("%c",data[i]);
7514 else
7515 printk(".");
7516 }
7517 printk("\n");
7518
7519 data += linecount;
7520 count -= linecount;
7521 }
7522 } /* end of mgsl_trace_block() */
7523
7524 /* mgsl_tx_timeout()
7525 *
7526 * called when HDLC frame times out
7527 * update stats and do tx completion processing
7528 *
7529 * Arguments: context pointer to device instance data
7530 * Return Value: None
7531 */
7532 static void mgsl_tx_timeout(unsigned long context)
7533 {
7534 struct mgsl_struct *info = (struct mgsl_struct*)context;
7535 unsigned long flags;
7536
7537 if ( debug_level >= DEBUG_LEVEL_INFO )
7538 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7539 __FILE__,__LINE__,info->device_name);
7540 if(info->tx_active &&
7541 (info->params.mode == MGSL_MODE_HDLC ||
7542 info->params.mode == MGSL_MODE_RAW) ) {
7543 info->icount.txtimeout++;
7544 }
7545 spin_lock_irqsave(&info->irq_spinlock,flags);
7546 info->tx_active = false;
7547 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7548
7549 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7550 usc_loopmode_cancel_transmit( info );
7551
7552 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7553
7554 #if SYNCLINK_GENERIC_HDLC
7555 if (info->netcount)
7556 hdlcdev_tx_done(info);
7557 else
7558 #endif
7559 mgsl_bh_transmit(info);
7560
7561 } /* end of mgsl_tx_timeout() */
7562
7563 /* signal that there are no more frames to send, so that
7564 * line is 'released' by echoing RxD to TxD when current
7565 * transmission is complete (or immediately if no tx in progress).
7566 */
7567 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7568 {
7569 unsigned long flags;
7570
7571 spin_lock_irqsave(&info->irq_spinlock,flags);
7572 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7573 if (info->tx_active)
7574 info->loopmode_send_done_requested = true;
7575 else
7576 usc_loopmode_send_done(info);
7577 }
7578 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7579
7580 return 0;
7581 }
7582
7583 /* release the line by echoing RxD to TxD
7584 * upon completion of a transmit frame
7585 */
7586 static void usc_loopmode_send_done( struct mgsl_struct * info )
7587 {
7588 info->loopmode_send_done_requested = false;
7589 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7590 info->cmr_value &= ~BIT13;
7591 usc_OutReg(info, CMR, info->cmr_value);
7592 }
7593
7594 /* abort a transmit in progress while in HDLC LoopMode
7595 */
7596 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7597 {
7598 /* reset tx dma channel and purge TxFifo */
7599 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7600 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7601 usc_loopmode_send_done( info );
7602 }
7603
7604 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7605 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7606 * we must clear CMR:13 to begin repeating TxData to RxData
7607 */
7608 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7609 {
7610 info->loopmode_insert_requested = true;
7611
7612 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7613 * begin repeating TxData on RxData (complete insertion)
7614 */
7615 usc_OutReg( info, RICR,
7616 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7617
7618 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7619 info->cmr_value |= BIT13;
7620 usc_OutReg(info, CMR, info->cmr_value);
7621 }
7622
7623 /* return 1 if station is inserted into the loop, otherwise 0
7624 */
7625 static int usc_loopmode_active( struct mgsl_struct * info)
7626 {
7627 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7628 }
7629
7630 #if SYNCLINK_GENERIC_HDLC
7631
7632 /**
7633 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7634 * set encoding and frame check sequence (FCS) options
7635 *
7636 * dev pointer to network device structure
7637 * encoding serial encoding setting
7638 * parity FCS setting
7639 *
7640 * returns 0 if success, otherwise error code
7641 */
7642 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7643 unsigned short parity)
7644 {
7645 struct mgsl_struct *info = dev_to_port(dev);
7646 unsigned char new_encoding;
7647 unsigned short new_crctype;
7648
7649 /* return error if TTY interface open */
7650 if (info->port.count)
7651 return -EBUSY;
7652
7653 switch (encoding)
7654 {
7655 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7656 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7657 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7658 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7659 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7660 default: return -EINVAL;
7661 }
7662
7663 switch (parity)
7664 {
7665 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7666 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7667 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7668 default: return -EINVAL;
7669 }
7670
7671 info->params.encoding = new_encoding;
7672 info->params.crc_type = new_crctype;
7673
7674 /* if network interface up, reprogram hardware */
7675 if (info->netcount)
7676 mgsl_program_hw(info);
7677
7678 return 0;
7679 }
7680
7681 /**
7682 * called by generic HDLC layer to send frame
7683 *
7684 * skb socket buffer containing HDLC frame
7685 * dev pointer to network device structure
7686 */
7687 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7688 struct net_device *dev)
7689 {
7690 struct mgsl_struct *info = dev_to_port(dev);
7691 unsigned long flags;
7692
7693 if (debug_level >= DEBUG_LEVEL_INFO)
7694 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7695
7696 /* stop sending until this frame completes */
7697 netif_stop_queue(dev);
7698
7699 /* copy data to device buffers */
7700 info->xmit_cnt = skb->len;
7701 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7702
7703 /* update network statistics */
7704 dev->stats.tx_packets++;
7705 dev->stats.tx_bytes += skb->len;
7706
7707 /* done with socket buffer, so free it */
7708 dev_kfree_skb(skb);
7709
7710 /* save start time for transmit timeout detection */
7711 dev->trans_start = jiffies;
7712
7713 /* start hardware transmitter if necessary */
7714 spin_lock_irqsave(&info->irq_spinlock,flags);
7715 if (!info->tx_active)
7716 usc_start_transmitter(info);
7717 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7718
7719 return NETDEV_TX_OK;
7720 }
7721
7722 /**
7723 * called by network layer when interface enabled
7724 * claim resources and initialize hardware
7725 *
7726 * dev pointer to network device structure
7727 *
7728 * returns 0 if success, otherwise error code
7729 */
7730 static int hdlcdev_open(struct net_device *dev)
7731 {
7732 struct mgsl_struct *info = dev_to_port(dev);
7733 int rc;
7734 unsigned long flags;
7735
7736 if (debug_level >= DEBUG_LEVEL_INFO)
7737 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7738
7739 /* generic HDLC layer open processing */
7740 rc = hdlc_open(dev);
7741 if (rc)
7742 return rc;
7743
7744 /* arbitrate between network and tty opens */
7745 spin_lock_irqsave(&info->netlock, flags);
7746 if (info->port.count != 0 || info->netcount != 0) {
7747 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7748 spin_unlock_irqrestore(&info->netlock, flags);
7749 return -EBUSY;
7750 }
7751 info->netcount=1;
7752 spin_unlock_irqrestore(&info->netlock, flags);
7753
7754 /* claim resources and init adapter */
7755 if ((rc = startup(info)) != 0) {
7756 spin_lock_irqsave(&info->netlock, flags);
7757 info->netcount=0;
7758 spin_unlock_irqrestore(&info->netlock, flags);
7759 return rc;
7760 }
7761
7762 /* assert RTS and DTR, apply hardware settings */
7763 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
7764 mgsl_program_hw(info);
7765
7766 /* enable network layer transmit */
7767 dev->trans_start = jiffies;
7768 netif_start_queue(dev);
7769
7770 /* inform generic HDLC layer of current DCD status */
7771 spin_lock_irqsave(&info->irq_spinlock, flags);
7772 usc_get_serial_signals(info);
7773 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7774 if (info->serial_signals & SerialSignal_DCD)
7775 netif_carrier_on(dev);
7776 else
7777 netif_carrier_off(dev);
7778 return 0;
7779 }
7780
7781 /**
7782 * called by network layer when interface is disabled
7783 * shutdown hardware and release resources
7784 *
7785 * dev pointer to network device structure
7786 *
7787 * returns 0 if success, otherwise error code
7788 */
7789 static int hdlcdev_close(struct net_device *dev)
7790 {
7791 struct mgsl_struct *info = dev_to_port(dev);
7792 unsigned long flags;
7793
7794 if (debug_level >= DEBUG_LEVEL_INFO)
7795 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7796
7797 netif_stop_queue(dev);
7798
7799 /* shutdown adapter and release resources */
7800 shutdown(info);
7801
7802 hdlc_close(dev);
7803
7804 spin_lock_irqsave(&info->netlock, flags);
7805 info->netcount=0;
7806 spin_unlock_irqrestore(&info->netlock, flags);
7807
7808 return 0;
7809 }
7810
7811 /**
7812 * called by network layer to process IOCTL call to network device
7813 *
7814 * dev pointer to network device structure
7815 * ifr pointer to network interface request structure
7816 * cmd IOCTL command code
7817 *
7818 * returns 0 if success, otherwise error code
7819 */
7820 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7821 {
7822 const size_t size = sizeof(sync_serial_settings);
7823 sync_serial_settings new_line;
7824 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7825 struct mgsl_struct *info = dev_to_port(dev);
7826 unsigned int flags;
7827
7828 if (debug_level >= DEBUG_LEVEL_INFO)
7829 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7830
7831 /* return error if TTY interface open */
7832 if (info->port.count)
7833 return -EBUSY;
7834
7835 if (cmd != SIOCWANDEV)
7836 return hdlc_ioctl(dev, ifr, cmd);
7837
7838 switch(ifr->ifr_settings.type) {
7839 case IF_GET_IFACE: /* return current sync_serial_settings */
7840
7841 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7842 if (ifr->ifr_settings.size < size) {
7843 ifr->ifr_settings.size = size; /* data size wanted */
7844 return -ENOBUFS;
7845 }
7846
7847 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7848 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7849 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7850 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7851
7852 memset(&new_line, 0, sizeof(new_line));
7853 switch (flags){
7854 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7855 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7856 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7857 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7858 default: new_line.clock_type = CLOCK_DEFAULT;
7859 }
7860
7861 new_line.clock_rate = info->params.clock_speed;
7862 new_line.loopback = info->params.loopback ? 1:0;
7863
7864 if (copy_to_user(line, &new_line, size))
7865 return -EFAULT;
7866 return 0;
7867
7868 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7869
7870 if(!capable(CAP_NET_ADMIN))
7871 return -EPERM;
7872 if (copy_from_user(&new_line, line, size))
7873 return -EFAULT;
7874
7875 switch (new_line.clock_type)
7876 {
7877 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7878 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7879 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7880 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7881 case CLOCK_DEFAULT: flags = info->params.flags &
7882 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7883 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7884 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7885 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7886 default: return -EINVAL;
7887 }
7888
7889 if (new_line.loopback != 0 && new_line.loopback != 1)
7890 return -EINVAL;
7891
7892 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7893 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7894 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7895 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7896 info->params.flags |= flags;
7897
7898 info->params.loopback = new_line.loopback;
7899
7900 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7901 info->params.clock_speed = new_line.clock_rate;
7902 else
7903 info->params.clock_speed = 0;
7904
7905 /* if network interface up, reprogram hardware */
7906 if (info->netcount)
7907 mgsl_program_hw(info);
7908 return 0;
7909
7910 default:
7911 return hdlc_ioctl(dev, ifr, cmd);
7912 }
7913 }
7914
7915 /**
7916 * called by network layer when transmit timeout is detected
7917 *
7918 * dev pointer to network device structure
7919 */
7920 static void hdlcdev_tx_timeout(struct net_device *dev)
7921 {
7922 struct mgsl_struct *info = dev_to_port(dev);
7923 unsigned long flags;
7924
7925 if (debug_level >= DEBUG_LEVEL_INFO)
7926 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7927
7928 dev->stats.tx_errors++;
7929 dev->stats.tx_aborted_errors++;
7930
7931 spin_lock_irqsave(&info->irq_spinlock,flags);
7932 usc_stop_transmitter(info);
7933 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7934
7935 netif_wake_queue(dev);
7936 }
7937
7938 /**
7939 * called by device driver when transmit completes
7940 * reenable network layer transmit if stopped
7941 *
7942 * info pointer to device instance information
7943 */
7944 static void hdlcdev_tx_done(struct mgsl_struct *info)
7945 {
7946 if (netif_queue_stopped(info->netdev))
7947 netif_wake_queue(info->netdev);
7948 }
7949
7950 /**
7951 * called by device driver when frame received
7952 * pass frame to network layer
7953 *
7954 * info pointer to device instance information
7955 * buf pointer to buffer contianing frame data
7956 * size count of data bytes in buf
7957 */
7958 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7959 {
7960 struct sk_buff *skb = dev_alloc_skb(size);
7961 struct net_device *dev = info->netdev;
7962
7963 if (debug_level >= DEBUG_LEVEL_INFO)
7964 printk("hdlcdev_rx(%s)\n", dev->name);
7965
7966 if (skb == NULL) {
7967 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7968 dev->name);
7969 dev->stats.rx_dropped++;
7970 return;
7971 }
7972
7973 memcpy(skb_put(skb, size), buf, size);
7974
7975 skb->protocol = hdlc_type_trans(skb, dev);
7976
7977 dev->stats.rx_packets++;
7978 dev->stats.rx_bytes += size;
7979
7980 netif_rx(skb);
7981 }
7982
7983 static const struct net_device_ops hdlcdev_ops = {
7984 .ndo_open = hdlcdev_open,
7985 .ndo_stop = hdlcdev_close,
7986 .ndo_change_mtu = hdlc_change_mtu,
7987 .ndo_start_xmit = hdlc_start_xmit,
7988 .ndo_do_ioctl = hdlcdev_ioctl,
7989 .ndo_tx_timeout = hdlcdev_tx_timeout,
7990 };
7991
7992 /**
7993 * called by device driver when adding device instance
7994 * do generic HDLC initialization
7995 *
7996 * info pointer to device instance information
7997 *
7998 * returns 0 if success, otherwise error code
7999 */
8000 static int hdlcdev_init(struct mgsl_struct *info)
8001 {
8002 int rc;
8003 struct net_device *dev;
8004 hdlc_device *hdlc;
8005
8006 /* allocate and initialize network and HDLC layer objects */
8007
8008 dev = alloc_hdlcdev(info);
8009 if (!dev) {
8010 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8011 return -ENOMEM;
8012 }
8013
8014 /* for network layer reporting purposes only */
8015 dev->base_addr = info->io_base;
8016 dev->irq = info->irq_level;
8017 dev->dma = info->dma_level;
8018
8019 /* network layer callbacks and settings */
8020 dev->netdev_ops = &hdlcdev_ops;
8021 dev->watchdog_timeo = 10 * HZ;
8022 dev->tx_queue_len = 50;
8023
8024 /* generic HDLC layer callbacks and settings */
8025 hdlc = dev_to_hdlc(dev);
8026 hdlc->attach = hdlcdev_attach;
8027 hdlc->xmit = hdlcdev_xmit;
8028
8029 /* register objects with HDLC layer */
8030 rc = register_hdlc_device(dev);
8031 if (rc) {
8032 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8033 free_netdev(dev);
8034 return rc;
8035 }
8036
8037 info->netdev = dev;
8038 return 0;
8039 }
8040
8041 /**
8042 * called by device driver when removing device instance
8043 * do generic HDLC cleanup
8044 *
8045 * info pointer to device instance information
8046 */
8047 static void hdlcdev_exit(struct mgsl_struct *info)
8048 {
8049 unregister_hdlc_device(info->netdev);
8050 free_netdev(info->netdev);
8051 info->netdev = NULL;
8052 }
8053
8054 #endif /* CONFIG_HDLC */
8055
8056
8057 static int synclink_init_one (struct pci_dev *dev,
8058 const struct pci_device_id *ent)
8059 {
8060 struct mgsl_struct *info;
8061
8062 if (pci_enable_device(dev)) {
8063 printk("error enabling pci device %p\n", dev);
8064 return -EIO;
8065 }
8066
8067 info = mgsl_allocate_device();
8068 if (!info) {
8069 printk("can't allocate device instance data.\n");
8070 return -EIO;
8071 }
8072
8073 /* Copy user configuration info to device instance data */
8074
8075 info->io_base = pci_resource_start(dev, 2);
8076 info->irq_level = dev->irq;
8077 info->phys_memory_base = pci_resource_start(dev, 3);
8078
8079 /* Because veremap only works on page boundaries we must map
8080 * a larger area than is actually implemented for the LCR
8081 * memory range. We map a full page starting at the page boundary.
8082 */
8083 info->phys_lcr_base = pci_resource_start(dev, 0);
8084 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8085 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8086
8087 info->bus_type = MGSL_BUS_TYPE_PCI;
8088 info->io_addr_size = 8;
8089 info->irq_flags = IRQF_SHARED;
8090
8091 if (dev->device == 0x0210) {
8092 /* Version 1 PCI9030 based universal PCI adapter */
8093 info->misc_ctrl_value = 0x007c4080;
8094 info->hw_version = 1;
8095 } else {
8096 /* Version 0 PCI9050 based 5V PCI adapter
8097 * A PCI9050 bug prevents reading LCR registers if
8098 * LCR base address bit 7 is set. Maintain shadow
8099 * value so we can write to LCR misc control reg.
8100 */
8101 info->misc_ctrl_value = 0x087e4546;
8102 info->hw_version = 0;
8103 }
8104
8105 mgsl_add_device(info);
8106
8107 return 0;
8108 }
8109
8110 static void synclink_remove_one (struct pci_dev *dev)
8111 {
8112 }
8113
Linux with added FPC-III support