include/uapi/drm/via_drm.h

   1 /*
   2  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef _VIA_DRM_H_
  25 #define _VIA_DRM_H_
  26
  27 #include "drm.h"
  28
  29 /* WARNING: These defines must be the same as what the Xserver uses.
  30  * if you change them, you must change the defines in the Xserver.
  31  */
  32
  33 #ifndef _VIA_DEFINES_
  34 #define _VIA_DEFINES_
  35
  36
  37 #define VIA_NR_SAREA_CLIPRECTS          8
  38 #define VIA_NR_XVMC_PORTS               10
  39 #define VIA_NR_XVMC_LOCKS               5
  40 #define VIA_MAX_CACHELINE_SIZE          64
  41 #define XVMCLOCKPTR(saPriv,lockNo)                                      \
  42         ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
  43                                       (VIA_MAX_CACHELINE_SIZE - 1)) &   \
  44                                      ~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
  45                                     VIA_MAX_CACHELINE_SIZE*(lockNo)))
  46
  47 /* Each region is a minimum of 64k, and there are at most 64 of them.
  48  */
  49 #define VIA_NR_TEX_REGIONS 64
  50 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
  51 #endif
  52
  53 #define VIA_UPLOAD_TEX0IMAGE  0x1       /* handled clientside */
  54 #define VIA_UPLOAD_TEX1IMAGE  0x2       /* handled clientside */
  55 #define VIA_UPLOAD_CTX        0x4
  56 #define VIA_UPLOAD_BUFFERS    0x8
  57 #define VIA_UPLOAD_TEX0       0x10
  58 #define VIA_UPLOAD_TEX1       0x20
  59 #define VIA_UPLOAD_CLIPRECTS  0x40
  60 #define VIA_UPLOAD_ALL        0xff
  61
  62 /* VIA specific ioctls */
  63 #define DRM_VIA_ALLOCMEM        0x00
  64 #define DRM_VIA_FREEMEM         0x01
  65 #define DRM_VIA_AGP_INIT        0x02
  66 #define DRM_VIA_FB_INIT         0x03
  67 #define DRM_VIA_MAP_INIT        0x04
  68 #define DRM_VIA_DEC_FUTEX       0x05
  69 #define NOT_USED
  70 #define DRM_VIA_DMA_INIT        0x07
  71 #define DRM_VIA_CMDBUFFER       0x08
  72 #define DRM_VIA_FLUSH           0x09
  73 #define DRM_VIA_PCICMD          0x0a
  74 #define DRM_VIA_CMDBUF_SIZE     0x0b
  75 #define NOT_USED
  76 #define DRM_VIA_WAIT_IRQ        0x0d
  77 #define DRM_VIA_DMA_BLIT        0x0e
  78 #define DRM_VIA_BLIT_SYNC       0x0f
  79
  80 #define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
  81 #define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
  82 #define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
  83 #define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
  84 #define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
  85 #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
  86 #define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
  87 #define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
  88 #define DRM_IOCTL_VIA_FLUSH       DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
  89 #define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
  90 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
  91                                             drm_via_cmdbuf_size_t)
  92 #define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
  93 #define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
  94 #define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
  95
  96 /* Indices into buf.Setup where various bits of state are mirrored per
  97  * context and per buffer.  These can be fired at the card as a unit,
  98  * or in a piecewise fashion as required.
  99  */
 100
 101 #define VIA_TEX_SETUP_SIZE 8
 102
 103 /* Flags for clear ioctl
 104  */
 105 #define VIA_FRONT   0x1
 106 #define VIA_BACK    0x2
 107 #define VIA_DEPTH   0x4
 108 #define VIA_STENCIL 0x8
 109 #define VIA_MEM_VIDEO   0       /* matches drm constant */
 110 #define VIA_MEM_AGP     1       /* matches drm constant */
 111 #define VIA_MEM_SYSTEM  2
 112 #define VIA_MEM_MIXED   3
 113 #define VIA_MEM_UNKNOWN 4
 114
 115 typedef struct {
 116         __u32 offset;
 117         __u32 size;
 118 } drm_via_agp_t;
 119
 120 typedef struct {
 121         __u32 offset;
 122         __u32 size;
 123 } drm_via_fb_t;
 124
 125 typedef struct {
 126         __u32 context;
 127         __u32 type;
 128         __u32 size;
 129         unsigned long index;
 130         unsigned long offset;
 131 } drm_via_mem_t;
 132
 133 typedef struct _drm_via_init {
 134         enum {
 135                 VIA_INIT_MAP = 0x01,
 136                 VIA_CLEANUP_MAP = 0x02
 137         } func;
 138
 139         unsigned long sarea_priv_offset;
 140         unsigned long fb_offset;
 141         unsigned long mmio_offset;
 142         unsigned long agpAddr;
 143 } drm_via_init_t;
 144
 145 typedef struct _drm_via_futex {
 146         enum {
 147                 VIA_FUTEX_WAIT = 0x00,
 148                 VIA_FUTEX_WAKE = 0X01
 149         } func;
 150         __u32 ms;
 151         __u32 lock;
 152         __u32 val;
 153 } drm_via_futex_t;
 154
 155 typedef struct _drm_via_dma_init {
 156         enum {
 157                 VIA_INIT_DMA = 0x01,
 158                 VIA_CLEANUP_DMA = 0x02,
 159                 VIA_DMA_INITIALIZED = 0x03
 160         } func;
 161
 162         unsigned long offset;
 163         unsigned long size;
 164         unsigned long reg_pause_addr;
 165 } drm_via_dma_init_t;
 166
 167 typedef struct _drm_via_cmdbuffer {
 168         char __user *buf;
 169         unsigned long size;
 170 } drm_via_cmdbuffer_t;
 171
 172 /* Warning: If you change the SAREA structure you must change the Xserver
 173  * structure as well */
 174
 175 typedef struct _drm_via_tex_region {
 176         unsigned char next, prev;       /* indices to form a circular LRU  */
 177         unsigned char inUse;    /* owned by a client, or free? */
 178         int age;                /* tracked by clients to update local LRU's */
 179 } drm_via_tex_region_t;
 180
 181 typedef struct _drm_via_sarea {
 182         unsigned int dirty;
 183         unsigned int nbox;
 184         struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
 185         drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 186         int texAge;             /* last time texture was uploaded */
 187         int ctxOwner;           /* last context to upload state */
 188         int vertexPrim;
 189
 190         /*
 191          * Below is for XvMC.
 192          * We want the lock integers alone on, and aligned to, a cache line.
 193          * Therefore this somewhat strange construct.
 194          */
 195
 196         char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 197
 198         unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
 199         unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
 200         unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
 201
 202         /* Used by the 3d driver only at this point, for pageflipping:
 203          */
 204         unsigned int pfCurrentOffset;
 205 } drm_via_sarea_t;
 206
 207 typedef struct _drm_via_cmdbuf_size {
 208         enum {
 209                 VIA_CMDBUF_SPACE = 0x01,
 210                 VIA_CMDBUF_LAG = 0x02
 211         } func;
 212         int wait;
 213         __u32 size;
 214 } drm_via_cmdbuf_size_t;
 215
 216 typedef enum {
 217         VIA_IRQ_ABSOLUTE = 0x0,
 218         VIA_IRQ_RELATIVE = 0x1,
 219         VIA_IRQ_SIGNAL = 0x10000000,
 220         VIA_IRQ_FORCE_SEQUENCE = 0x20000000
 221 } via_irq_seq_type_t;
 222
 223 #define VIA_IRQ_FLAGS_MASK 0xF0000000
 224
 225 enum drm_via_irqs {
 226         drm_via_irq_hqv0 = 0,
 227         drm_via_irq_hqv1,
 228         drm_via_irq_dma0_dd,
 229         drm_via_irq_dma0_td,
 230         drm_via_irq_dma1_dd,
 231         drm_via_irq_dma1_td,
 232         drm_via_irq_num
 233 };
 234
 235 struct drm_via_wait_irq_request {
 236         unsigned irq;
 237         via_irq_seq_type_t type;
 238         __u32 sequence;
 239         __u32 signal;
 240 };
 241
 242 typedef union drm_via_irqwait {
 243         struct drm_via_wait_irq_request request;
 244         struct drm_wait_vblank_reply reply;
 245 } drm_via_irqwait_t;
 246
 247 typedef struct drm_via_blitsync {
 248         __u32 sync_handle;
 249         unsigned engine;
 250 } drm_via_blitsync_t;
 251
 252 /* - * Below,"flags" is currently unused but will be used for possible future
 253  * extensions like kernel space bounce buffers for bad alignments and
 254  * blit engine busy-wait polling for better latency in the absence of
 255  * interrupts.
 256  */
 257
 258 typedef struct drm_via_dmablit {
 259         __u32 num_lines;
 260         __u32 line_length;
 261
 262         __u32 fb_addr;
 263         __u32 fb_stride;
 264
 265         unsigned char *mem_addr;
 266         __u32 mem_stride;
 267
 268         __u32 flags;
 269         int to_fb;
 270
 271         drm_via_blitsync_t sync;
 272 } drm_via_dmablit_t;
 273
 274 #endif                          /* _VIA_DRM_H_ */