2 * wm8580.c -- WM8580 ALSA Soc Audio driver
4 * Copyright 2008-12 Wolfson Microelectronics PLC.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/slab.h>
29 #include <linux/of_device.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/tlv.h>
36 #include <sound/initval.h>
37 #include <asm/div64.h>
41 /* WM8580 register space */
42 #define WM8580_PLLA1 0x00
43 #define WM8580_PLLA2 0x01
44 #define WM8580_PLLA3 0x02
45 #define WM8580_PLLA4 0x03
46 #define WM8580_PLLB1 0x04
47 #define WM8580_PLLB2 0x05
48 #define WM8580_PLLB3 0x06
49 #define WM8580_PLLB4 0x07
50 #define WM8580_CLKSEL 0x08
51 #define WM8580_PAIF1 0x09
52 #define WM8580_PAIF2 0x0A
53 #define WM8580_SAIF1 0x0B
54 #define WM8580_PAIF3 0x0C
55 #define WM8580_PAIF4 0x0D
56 #define WM8580_SAIF2 0x0E
57 #define WM8580_DAC_CONTROL1 0x0F
58 #define WM8580_DAC_CONTROL2 0x10
59 #define WM8580_DAC_CONTROL3 0x11
60 #define WM8580_DAC_CONTROL4 0x12
61 #define WM8580_DAC_CONTROL5 0x13
62 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
63 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
64 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
65 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
66 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
67 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
68 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69 #define WM8580_ADC_CONTROL1 0x1D
70 #define WM8580_SPDTXCHAN0 0x1E
71 #define WM8580_SPDTXCHAN1 0x1F
72 #define WM8580_SPDTXCHAN2 0x20
73 #define WM8580_SPDTXCHAN3 0x21
74 #define WM8580_SPDTXCHAN4 0x22
75 #define WM8580_SPDTXCHAN5 0x23
76 #define WM8580_SPDMODE 0x24
77 #define WM8580_INTMASK 0x25
78 #define WM8580_GPO1 0x26
79 #define WM8580_GPO2 0x27
80 #define WM8580_GPO3 0x28
81 #define WM8580_GPO4 0x29
82 #define WM8580_GPO5 0x2A
83 #define WM8580_INTSTAT 0x2B
84 #define WM8580_SPDRXCHAN1 0x2C
85 #define WM8580_SPDRXCHAN2 0x2D
86 #define WM8580_SPDRXCHAN3 0x2E
87 #define WM8580_SPDRXCHAN4 0x2F
88 #define WM8580_SPDRXCHAN5 0x30
89 #define WM8580_SPDSTAT 0x31
90 #define WM8580_PWRDN1 0x32
91 #define WM8580_PWRDN2 0x33
92 #define WM8580_READBACK 0x34
93 #define WM8580_RESET 0x35
95 #define WM8580_MAX_REGISTER 0x35
97 #define WM8580_DACOSR 0x40
99 /* PLLB4 (register 7h) */
100 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
103 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
105 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
110 /* CLKSEL (register 8h) */
111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
115 /* AIF control 1 (registers 9h-bh) */
116 #define WM8580_AIF_RATE_MASK 0x7
117 #define WM8580_AIF_BCLKSEL_MASK 0x18
119 #define WM8580_AIF_MS 0x20
121 #define WM8580_AIF_CLKSRC_MASK 0xc0
122 #define WM8580_AIF_CLKSRC_PLLA 0x40
123 #define WM8580_AIF_CLKSRC_PLLB 0x40
124 #define WM8580_AIF_CLKSRC_MCLK 0xc0
126 /* AIF control 2 (registers ch-eh) */
127 #define WM8580_AIF_FMT_MASK 0x03
128 #define WM8580_AIF_FMT_RIGHTJ 0x00
129 #define WM8580_AIF_FMT_LEFTJ 0x01
130 #define WM8580_AIF_FMT_I2S 0x02
131 #define WM8580_AIF_FMT_DSP 0x03
133 #define WM8580_AIF_LENGTH_MASK 0x0c
134 #define WM8580_AIF_LENGTH_16 0x00
135 #define WM8580_AIF_LENGTH_20 0x04
136 #define WM8580_AIF_LENGTH_24 0x08
137 #define WM8580_AIF_LENGTH_32 0x0c
139 #define WM8580_AIF_LRP 0x10
140 #define WM8580_AIF_BCP 0x20
142 /* Powerdown Register 1 (register 32h) */
143 #define WM8580_PWRDN1_PWDN 0x001
144 #define WM8580_PWRDN1_ALLDACPD 0x040
146 /* Powerdown Register 2 (register 33h) */
147 #define WM8580_PWRDN2_OSSCPD 0x001
148 #define WM8580_PWRDN2_PLLAPD 0x002
149 #define WM8580_PWRDN2_PLLBPD 0x004
150 #define WM8580_PWRDN2_SPDIFPD 0x008
151 #define WM8580_PWRDN2_SPDIFTXD 0x010
152 #define WM8580_PWRDN2_SPDIFRXD 0x020
154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
157 * wm8580 register cache
158 * We can't read the WM8580 register space when we
159 * are using 2 wire for device control, so we cache them instead.
161 static const struct reg_default wm8580_reg_defaults
[] = {
217 static bool wm8580_volatile(struct device
*dev
, unsigned int reg
)
232 #define WM8580_NUM_SUPPLIES 3
233 static const char *wm8580_supply_names
[WM8580_NUM_SUPPLIES
] = {
239 /* codec private data */
241 struct regmap
*regmap
;
242 struct regulator_bulk_data supplies
[WM8580_NUM_SUPPLIES
];
248 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -12750, 50, 1);
250 static int wm8580_out_vu(struct snd_kcontrol
*kcontrol
,
251 struct snd_ctl_elem_value
*ucontrol
)
253 struct soc_mixer_control
*mc
=
254 (struct soc_mixer_control
*)kcontrol
->private_value
;
255 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
256 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
257 unsigned int reg
= mc
->reg
;
258 unsigned int reg2
= mc
->rreg
;
261 /* Clear the register cache VU so we write without VU set */
262 regcache_cache_only(wm8580
->regmap
, true);
263 regmap_update_bits(wm8580
->regmap
, reg
, 0x100, 0x000);
264 regmap_update_bits(wm8580
->regmap
, reg2
, 0x100, 0x000);
265 regcache_cache_only(wm8580
->regmap
, false);
267 ret
= snd_soc_put_volsw(kcontrol
, ucontrol
);
271 /* Now write again with the volume update bit set */
272 snd_soc_update_bits(codec
, reg
, 0x100, 0x100);
273 snd_soc_update_bits(codec
, reg2
, 0x100, 0x100);
278 static const struct snd_kcontrol_new wm8580_snd_controls
[] = {
279 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
280 WM8580_DIGITAL_ATTENUATION_DACL1
,
281 WM8580_DIGITAL_ATTENUATION_DACR1
,
282 0, 0xff, 0, snd_soc_get_volsw
, wm8580_out_vu
, dac_tlv
),
283 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
284 WM8580_DIGITAL_ATTENUATION_DACL2
,
285 WM8580_DIGITAL_ATTENUATION_DACR2
,
286 0, 0xff, 0, snd_soc_get_volsw
, wm8580_out_vu
, dac_tlv
),
287 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
288 WM8580_DIGITAL_ATTENUATION_DACL3
,
289 WM8580_DIGITAL_ATTENUATION_DACR3
,
290 0, 0xff, 0, snd_soc_get_volsw
, wm8580_out_vu
, dac_tlv
),
292 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3
, 0, 1, 0),
293 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3
, 1, 1, 0),
294 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3
, 2, 1, 0),
296 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4
, 0, 1, 1, 0),
297 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4
, 2, 3, 1, 0),
298 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4
, 4, 5, 1, 0),
300 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5
, 5, 1, 0),
301 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5
, 0, 1, 1),
302 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5
, 1, 1, 1),
303 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5
, 2, 1, 1),
305 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1
, 0, 1, 1, 1),
306 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1
, 4, 1, 0),
309 static const struct snd_soc_dapm_widget wm8580_dapm_widgets
[] = {
310 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1
, 2, 1),
311 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1
, 3, 1),
312 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1
, 4, 1),
314 SND_SOC_DAPM_OUTPUT("VOUT1L"),
315 SND_SOC_DAPM_OUTPUT("VOUT1R"),
316 SND_SOC_DAPM_OUTPUT("VOUT2L"),
317 SND_SOC_DAPM_OUTPUT("VOUT2R"),
318 SND_SOC_DAPM_OUTPUT("VOUT3L"),
319 SND_SOC_DAPM_OUTPUT("VOUT3R"),
321 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1
, 1, 1),
323 SND_SOC_DAPM_INPUT("AINL"),
324 SND_SOC_DAPM_INPUT("AINR"),
327 static const struct snd_soc_dapm_route wm8580_dapm_routes
[] = {
328 { "VOUT1L", NULL
, "DAC1" },
329 { "VOUT1R", NULL
, "DAC1" },
331 { "VOUT2L", NULL
, "DAC2" },
332 { "VOUT2R", NULL
, "DAC2" },
334 { "VOUT3L", NULL
, "DAC3" },
335 { "VOUT3R", NULL
, "DAC3" },
337 { "ADC", NULL
, "AINL" },
338 { "ADC", NULL
, "AINR" },
350 /* The size in bits of the pll divide */
351 #define FIXED_PLL_SIZE (1 << 22)
353 /* PLL rate to output rate divisions */
356 unsigned int freqmode
;
357 unsigned int postscale
;
369 static int pll_factors(struct _pll_div
*pll_div
, unsigned int target
,
373 unsigned int K
, Ndiv
, Nmod
;
376 pr_debug("wm8580: PLL %uHz->%uHz\n", source
, target
);
378 /* Scale the output frequency up; the PLL should run in the
379 * region of 90-100MHz.
381 for (i
= 0; i
< ARRAY_SIZE(post_table
); i
++) {
382 if (target
* post_table
[i
].div
>= 90000000 &&
383 target
* post_table
[i
].div
<= 100000000) {
384 pll_div
->freqmode
= post_table
[i
].freqmode
;
385 pll_div
->postscale
= post_table
[i
].postscale
;
386 target
*= post_table
[i
].div
;
391 if (i
== ARRAY_SIZE(post_table
)) {
392 printk(KERN_ERR
"wm8580: Unable to scale output frequency "
397 Ndiv
= target
/ source
;
401 pll_div
->prescale
= 1;
402 Ndiv
= target
/ source
;
404 pll_div
->prescale
= 0;
406 if ((Ndiv
< 5) || (Ndiv
> 13)) {
408 "WM8580 N=%u outside supported range\n", Ndiv
);
413 Nmod
= target
% source
;
414 Kpart
= FIXED_PLL_SIZE
* (long long)Nmod
;
416 do_div(Kpart
, source
);
418 K
= Kpart
& 0xFFFFFFFF;
422 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
423 pll_div
->n
, pll_div
->k
, pll_div
->prescale
, pll_div
->freqmode
,
429 static int wm8580_set_dai_pll(struct snd_soc_dai
*codec_dai
, int pll_id
,
430 int source
, unsigned int freq_in
, unsigned int freq_out
)
433 struct snd_soc_codec
*codec
= codec_dai
->codec
;
434 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
435 struct pll_state
*state
;
436 struct _pll_div pll_div
;
438 unsigned int pwr_mask
;
441 /* GCC isn't able to work out the ifs below for initialising/using
442 * pll_div so suppress warnings.
444 memset(&pll_div
, 0, sizeof(pll_div
));
450 pwr_mask
= WM8580_PWRDN2_PLLAPD
;
455 pwr_mask
= WM8580_PWRDN2_PLLBPD
;
461 if (freq_in
&& freq_out
) {
462 ret
= pll_factors(&pll_div
, freq_out
, freq_in
);
468 state
->out
= freq_out
;
470 /* Always disable the PLL - it is not safe to leave it running
471 * while reprogramming it.
473 snd_soc_update_bits(codec
, WM8580_PWRDN2
, pwr_mask
, pwr_mask
);
475 if (!freq_in
|| !freq_out
)
478 snd_soc_write(codec
, WM8580_PLLA1
+ offset
, pll_div
.k
& 0x1ff);
479 snd_soc_write(codec
, WM8580_PLLA2
+ offset
, (pll_div
.k
>> 9) & 0x1ff);
480 snd_soc_write(codec
, WM8580_PLLA3
+ offset
,
481 (pll_div
.k
>> 18 & 0xf) | (pll_div
.n
<< 4));
483 reg
= snd_soc_read(codec
, WM8580_PLLA4
+ offset
);
485 reg
|= pll_div
.prescale
| pll_div
.postscale
<< 1 |
486 pll_div
.freqmode
<< 3;
488 snd_soc_write(codec
, WM8580_PLLA4
+ offset
, reg
);
490 /* All done, turn it on */
491 snd_soc_update_bits(codec
, WM8580_PWRDN2
, pwr_mask
, 0);
496 static const int wm8580_sysclk_ratios
[] = {
497 128, 192, 256, 384, 512, 768, 1152,
501 * Set PCM DAI bit size and sample rate.
503 static int wm8580_paif_hw_params(struct snd_pcm_substream
*substream
,
504 struct snd_pcm_hw_params
*params
,
505 struct snd_soc_dai
*dai
)
507 struct snd_soc_codec
*codec
= dai
->codec
;
508 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
514 switch (params_width(params
)) {
520 paifb
|= WM8580_AIF_LENGTH_20
;
524 paifb
|= WM8580_AIF_LENGTH_24
;
528 paifb
|= WM8580_AIF_LENGTH_32
;
534 /* Look up the SYSCLK ratio; accept only exact matches */
535 ratio
= wm8580
->sysclk
[dai
->driver
->id
] / params_rate(params
);
536 for (i
= 0; i
< ARRAY_SIZE(wm8580_sysclk_ratios
); i
++)
537 if (ratio
== wm8580_sysclk_ratios
[i
])
539 if (i
== ARRAY_SIZE(wm8580_sysclk_ratios
)) {
540 dev_err(codec
->dev
, "Invalid clock ratio %d/%d\n",
541 wm8580
->sysclk
[dai
->driver
->id
], params_rate(params
));
545 dev_dbg(codec
->dev
, "Running at %dfs with %dHz clock\n",
546 wm8580_sysclk_ratios
[i
], wm8580
->sysclk
[dai
->driver
->id
]);
548 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
553 dev_dbg(codec
->dev
, "Selecting 64x OSR\n");
557 dev_dbg(codec
->dev
, "Selecting 128x OSR\n");
561 snd_soc_update_bits(codec
, WM8580_PAIF3
, WM8580_DACOSR
, osr
);
564 snd_soc_update_bits(codec
, WM8580_PAIF1
+ dai
->driver
->id
,
565 WM8580_AIF_RATE_MASK
| WM8580_AIF_BCLKSEL_MASK
,
567 snd_soc_update_bits(codec
, WM8580_PAIF3
+ dai
->driver
->id
,
568 WM8580_AIF_LENGTH_MASK
, paifb
);
572 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai
*codec_dai
,
575 struct snd_soc_codec
*codec
= codec_dai
->codec
;
578 int can_invert_lrclk
;
580 aifa
= snd_soc_read(codec
, WM8580_PAIF1
+ codec_dai
->driver
->id
);
581 aifb
= snd_soc_read(codec
, WM8580_PAIF3
+ codec_dai
->driver
->id
);
583 aifb
&= ~(WM8580_AIF_FMT_MASK
| WM8580_AIF_LRP
| WM8580_AIF_BCP
);
585 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
586 case SND_SOC_DAIFMT_CBS_CFS
:
587 aifa
&= ~WM8580_AIF_MS
;
589 case SND_SOC_DAIFMT_CBM_CFM
:
590 aifa
|= WM8580_AIF_MS
;
596 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
597 case SND_SOC_DAIFMT_I2S
:
598 can_invert_lrclk
= 1;
599 aifb
|= WM8580_AIF_FMT_I2S
;
601 case SND_SOC_DAIFMT_RIGHT_J
:
602 can_invert_lrclk
= 1;
603 aifb
|= WM8580_AIF_FMT_RIGHTJ
;
605 case SND_SOC_DAIFMT_LEFT_J
:
606 can_invert_lrclk
= 1;
607 aifb
|= WM8580_AIF_FMT_LEFTJ
;
609 case SND_SOC_DAIFMT_DSP_A
:
610 can_invert_lrclk
= 0;
611 aifb
|= WM8580_AIF_FMT_DSP
;
613 case SND_SOC_DAIFMT_DSP_B
:
614 can_invert_lrclk
= 0;
615 aifb
|= WM8580_AIF_FMT_DSP
;
616 aifb
|= WM8580_AIF_LRP
;
622 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
623 case SND_SOC_DAIFMT_NB_NF
:
626 case SND_SOC_DAIFMT_IB_IF
:
627 if (!can_invert_lrclk
)
629 aifb
|= WM8580_AIF_BCP
;
630 aifb
|= WM8580_AIF_LRP
;
633 case SND_SOC_DAIFMT_IB_NF
:
634 aifb
|= WM8580_AIF_BCP
;
637 case SND_SOC_DAIFMT_NB_IF
:
638 if (!can_invert_lrclk
)
640 aifb
|= WM8580_AIF_LRP
;
647 snd_soc_write(codec
, WM8580_PAIF1
+ codec_dai
->driver
->id
, aifa
);
648 snd_soc_write(codec
, WM8580_PAIF3
+ codec_dai
->driver
->id
, aifb
);
653 static int wm8580_set_dai_clkdiv(struct snd_soc_dai
*codec_dai
,
656 struct snd_soc_codec
*codec
= codec_dai
->codec
;
661 reg
= snd_soc_read(codec
, WM8580_PLLB4
);
662 reg
&= ~WM8580_PLLB4_MCLKOUTSRC_MASK
;
665 case WM8580_CLKSRC_MCLK
:
669 case WM8580_CLKSRC_PLLA
:
670 reg
|= WM8580_PLLB4_MCLKOUTSRC_PLLA
;
672 case WM8580_CLKSRC_PLLB
:
673 reg
|= WM8580_PLLB4_MCLKOUTSRC_PLLB
;
676 case WM8580_CLKSRC_OSC
:
677 reg
|= WM8580_PLLB4_MCLKOUTSRC_OSC
;
683 snd_soc_write(codec
, WM8580_PLLB4
, reg
);
686 case WM8580_CLKOUTSRC
:
687 reg
= snd_soc_read(codec
, WM8580_PLLB4
);
688 reg
&= ~WM8580_PLLB4_CLKOUTSRC_MASK
;
691 case WM8580_CLKSRC_NONE
:
694 case WM8580_CLKSRC_PLLA
:
695 reg
|= WM8580_PLLB4_CLKOUTSRC_PLLACLK
;
698 case WM8580_CLKSRC_PLLB
:
699 reg
|= WM8580_PLLB4_CLKOUTSRC_PLLBCLK
;
702 case WM8580_CLKSRC_OSC
:
703 reg
|= WM8580_PLLB4_CLKOUTSRC_OSCCLK
;
709 snd_soc_write(codec
, WM8580_PLLB4
, reg
);
719 static int wm8580_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
720 unsigned int freq
, int dir
)
722 struct snd_soc_codec
*codec
= dai
->codec
;
723 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
724 int ret
, sel
, sel_mask
, sel_shift
;
726 switch (dai
->driver
->id
) {
727 case WM8580_DAI_PAIFRX
:
732 case WM8580_DAI_PAIFTX
:
738 WARN(1, "Unknown DAI driver ID\n");
743 case WM8580_CLKSRC_ADCMCLK
:
744 if (dai
->driver
->id
!= WM8580_DAI_PAIFTX
)
746 sel
= 0 << sel_shift
;
748 case WM8580_CLKSRC_PLLA
:
749 sel
= 1 << sel_shift
;
751 case WM8580_CLKSRC_PLLB
:
752 sel
= 2 << sel_shift
;
754 case WM8580_CLKSRC_MCLK
:
755 sel
= 3 << sel_shift
;
758 dev_err(codec
->dev
, "Unknown clock %d\n", clk_id
);
762 /* We really should validate PLL settings but not yet */
763 wm8580
->sysclk
[dai
->driver
->id
] = freq
;
765 ret
= snd_soc_update_bits(codec
, WM8580_CLKSEL
, sel_mask
, sel
);
772 static int wm8580_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
774 struct snd_soc_codec
*codec
= codec_dai
->codec
;
777 reg
= snd_soc_read(codec
, WM8580_DAC_CONTROL5
);
780 reg
|= WM8580_DAC_CONTROL5_MUTEALL
;
782 reg
&= ~WM8580_DAC_CONTROL5_MUTEALL
;
784 snd_soc_write(codec
, WM8580_DAC_CONTROL5
, reg
);
789 static int wm8580_set_bias_level(struct snd_soc_codec
*codec
,
790 enum snd_soc_bias_level level
)
793 case SND_SOC_BIAS_ON
:
794 case SND_SOC_BIAS_PREPARE
:
797 case SND_SOC_BIAS_STANDBY
:
798 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
) {
799 /* Power up and get individual control of the DACs */
800 snd_soc_update_bits(codec
, WM8580_PWRDN1
,
802 WM8580_PWRDN1_ALLDACPD
, 0);
804 /* Make VMID high impedance */
805 snd_soc_update_bits(codec
, WM8580_ADC_CONTROL1
,
810 case SND_SOC_BIAS_OFF
:
811 snd_soc_update_bits(codec
, WM8580_PWRDN1
,
812 WM8580_PWRDN1_PWDN
, WM8580_PWRDN1_PWDN
);
818 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
819 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
821 static const struct snd_soc_dai_ops wm8580_dai_ops_playback
= {
822 .set_sysclk
= wm8580_set_sysclk
,
823 .hw_params
= wm8580_paif_hw_params
,
824 .set_fmt
= wm8580_set_paif_dai_fmt
,
825 .set_clkdiv
= wm8580_set_dai_clkdiv
,
826 .set_pll
= wm8580_set_dai_pll
,
827 .digital_mute
= wm8580_digital_mute
,
830 static const struct snd_soc_dai_ops wm8580_dai_ops_capture
= {
831 .set_sysclk
= wm8580_set_sysclk
,
832 .hw_params
= wm8580_paif_hw_params
,
833 .set_fmt
= wm8580_set_paif_dai_fmt
,
834 .set_clkdiv
= wm8580_set_dai_clkdiv
,
835 .set_pll
= wm8580_set_dai_pll
,
838 static struct snd_soc_dai_driver wm8580_dai
[] = {
840 .name
= "wm8580-hifi-playback",
841 .id
= WM8580_DAI_PAIFRX
,
843 .stream_name
= "Playback",
846 .rates
= SNDRV_PCM_RATE_8000_192000
,
847 .formats
= WM8580_FORMATS
,
849 .ops
= &wm8580_dai_ops_playback
,
852 .name
= "wm8580-hifi-capture",
853 .id
= WM8580_DAI_PAIFTX
,
855 .stream_name
= "Capture",
858 .rates
= SNDRV_PCM_RATE_8000_192000
,
859 .formats
= WM8580_FORMATS
,
861 .ops
= &wm8580_dai_ops_capture
,
865 static int wm8580_probe(struct snd_soc_codec
*codec
)
867 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
870 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8580
->supplies
),
873 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
874 goto err_regulator_get
;
877 /* Get the codec into a known state */
878 ret
= snd_soc_write(codec
, WM8580_RESET
, 0);
880 dev_err(codec
->dev
, "Failed to reset codec: %d\n", ret
);
881 goto err_regulator_enable
;
886 err_regulator_enable
:
887 regulator_bulk_disable(ARRAY_SIZE(wm8580
->supplies
), wm8580
->supplies
);
892 /* power down chip */
893 static int wm8580_remove(struct snd_soc_codec
*codec
)
895 struct wm8580_priv
*wm8580
= snd_soc_codec_get_drvdata(codec
);
897 regulator_bulk_disable(ARRAY_SIZE(wm8580
->supplies
), wm8580
->supplies
);
902 static struct snd_soc_codec_driver soc_codec_dev_wm8580
= {
903 .probe
= wm8580_probe
,
904 .remove
= wm8580_remove
,
905 .set_bias_level
= wm8580_set_bias_level
,
907 .controls
= wm8580_snd_controls
,
908 .num_controls
= ARRAY_SIZE(wm8580_snd_controls
),
909 .dapm_widgets
= wm8580_dapm_widgets
,
910 .num_dapm_widgets
= ARRAY_SIZE(wm8580_dapm_widgets
),
911 .dapm_routes
= wm8580_dapm_routes
,
912 .num_dapm_routes
= ARRAY_SIZE(wm8580_dapm_routes
),
915 static const struct of_device_id wm8580_of_match
[] = {
916 { .compatible
= "wlf,wm8580" },
919 MODULE_DEVICE_TABLE(of
, wm8580_of_match
);
921 static const struct regmap_config wm8580_regmap
= {
924 .max_register
= WM8580_MAX_REGISTER
,
926 .reg_defaults
= wm8580_reg_defaults
,
927 .num_reg_defaults
= ARRAY_SIZE(wm8580_reg_defaults
),
928 .cache_type
= REGCACHE_RBTREE
,
930 .volatile_reg
= wm8580_volatile
,
933 #if IS_ENABLED(CONFIG_I2C)
934 static int wm8580_i2c_probe(struct i2c_client
*i2c
,
935 const struct i2c_device_id
*id
)
937 struct wm8580_priv
*wm8580
;
940 wm8580
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8580_priv
),
945 wm8580
->regmap
= devm_regmap_init_i2c(i2c
, &wm8580_regmap
);
946 if (IS_ERR(wm8580
->regmap
))
947 return PTR_ERR(wm8580
->regmap
);
949 for (i
= 0; i
< ARRAY_SIZE(wm8580
->supplies
); i
++)
950 wm8580
->supplies
[i
].supply
= wm8580_supply_names
[i
];
952 ret
= devm_regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(wm8580
->supplies
),
955 dev_err(&i2c
->dev
, "Failed to request supplies: %d\n", ret
);
959 i2c_set_clientdata(i2c
, wm8580
);
961 ret
= snd_soc_register_codec(&i2c
->dev
,
962 &soc_codec_dev_wm8580
, wm8580_dai
, ARRAY_SIZE(wm8580_dai
));
967 static int wm8580_i2c_remove(struct i2c_client
*client
)
969 snd_soc_unregister_codec(&client
->dev
);
973 static const struct i2c_device_id wm8580_i2c_id
[] = {
977 MODULE_DEVICE_TABLE(i2c
, wm8580_i2c_id
);
979 static struct i2c_driver wm8580_i2c_driver
= {
982 .of_match_table
= wm8580_of_match
,
984 .probe
= wm8580_i2c_probe
,
985 .remove
= wm8580_i2c_remove
,
986 .id_table
= wm8580_i2c_id
,
990 static int __init
wm8580_modinit(void)
994 #if IS_ENABLED(CONFIG_I2C)
995 ret
= i2c_add_driver(&wm8580_i2c_driver
);
997 pr_err("Failed to register WM8580 I2C driver: %d\n", ret
);
1003 module_init(wm8580_modinit
);
1005 static void __exit
wm8580_exit(void)
1007 #if IS_ENABLED(CONFIG_I2C)
1008 i2c_del_driver(&wm8580_i2c_driver
);
1011 module_exit(wm8580_exit
);
1013 MODULE_DESCRIPTION("ASoC WM8580 driver");
1014 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1015 MODULE_LICENSE("GPL");