mfd: bcm590xx: Use devm_mfd_add_devices() for mfd_device registration
[linux/fpc-iii.git] / drivers / cpufreq / longhaul.c
blob0f6b229afcb9e621eb116f6ce805a619ddfe96b3
1 /*
2 * (C) 2001-2004 Dave Jones.
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 #include <linux/timex.h>
34 #include <linux/io.h>
35 #include <linux/acpi.h>
37 #include <asm/msr.h>
38 #include <asm/cpu_device_id.h>
39 #include <acpi/processor.h>
41 #include "longhaul.h"
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
49 #define CPU_SAMUEL 1
50 #define CPU_SAMUEL2 2
51 #define CPU_EZRA 3
52 #define CPU_EZRA_T 4
53 #define CPU_NEHEMIAH 5
54 #define CPU_NEHEMIAH_C 6
56 /* Flags */
57 #define USE_ACPI_C3 (1 << 1)
58 #define USE_NORTHBRIDGE (1 << 2)
60 static int cpu_model;
61 static unsigned int numscales = 16;
62 static unsigned int fsb;
64 static const struct mV_pos *vrm_mV_table;
65 static const unsigned char *mV_vrm_table;
67 static unsigned int highest_speed, lowest_speed; /* kHz */
68 static unsigned int minmult, maxmult;
69 static int can_scale_voltage;
70 static struct acpi_processor *pr;
71 static struct acpi_processor_cx *cx;
72 static u32 acpi_regs_addr;
73 static u8 longhaul_flags;
74 static unsigned int longhaul_index;
76 /* Module parameters */
77 static int scale_voltage;
78 static int disable_acpi_c3;
79 static int revid_errata;
80 static int enable;
82 /* Clock ratios multiplied by 10 */
83 static int mults[32];
84 static int eblcr[32];
85 static int longhaul_version;
86 static struct cpufreq_frequency_table *longhaul_table;
88 static char speedbuffer[8];
90 static char *print_speed(int speed)
92 if (speed < 1000) {
93 snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
94 return speedbuffer;
97 if (speed%1000 == 0)
98 snprintf(speedbuffer, sizeof(speedbuffer),
99 "%dGHz", speed/1000);
100 else
101 snprintf(speedbuffer, sizeof(speedbuffer),
102 "%d.%dGHz", speed/1000, (speed%1000)/100);
104 return speedbuffer;
108 static unsigned int calc_speed(int mult)
110 int khz;
111 khz = (mult/10)*fsb;
112 if (mult%10)
113 khz += fsb/2;
114 khz *= 1000;
115 return khz;
119 static int longhaul_get_cpu_mult(void)
121 unsigned long invalue = 0, lo, hi;
123 rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
124 invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
125 if (longhaul_version == TYPE_LONGHAUL_V2 ||
126 longhaul_version == TYPE_POWERSAVER) {
127 if (lo & (1<<27))
128 invalue += 16;
130 return eblcr[invalue];
133 /* For processor with BCR2 MSR */
135 static void do_longhaul1(unsigned int mults_index)
137 union msr_bcr2 bcr2;
139 rdmsrl(MSR_VIA_BCR2, bcr2.val);
140 /* Enable software clock multiplier */
141 bcr2.bits.ESOFTBF = 1;
142 bcr2.bits.CLOCKMUL = mults_index & 0xff;
144 /* Sync to timer tick */
145 safe_halt();
146 /* Change frequency on next halt or sleep */
147 wrmsrl(MSR_VIA_BCR2, bcr2.val);
148 /* Invoke transition */
149 ACPI_FLUSH_CPU_CACHE();
150 halt();
152 /* Disable software clock multiplier */
153 local_irq_disable();
154 rdmsrl(MSR_VIA_BCR2, bcr2.val);
155 bcr2.bits.ESOFTBF = 0;
156 wrmsrl(MSR_VIA_BCR2, bcr2.val);
159 /* For processor with Longhaul MSR */
161 static void do_powersaver(int cx_address, unsigned int mults_index,
162 unsigned int dir)
164 union msr_longhaul longhaul;
165 u32 t;
167 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
168 /* Setup new frequency */
169 if (!revid_errata)
170 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
171 else
172 longhaul.bits.RevisionKey = 0;
173 longhaul.bits.SoftBusRatio = mults_index & 0xf;
174 longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
175 /* Setup new voltage */
176 if (can_scale_voltage)
177 longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
178 /* Sync to timer tick */
179 safe_halt();
180 /* Raise voltage if necessary */
181 if (can_scale_voltage && dir) {
182 longhaul.bits.EnableSoftVID = 1;
183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
184 /* Change voltage */
185 if (!cx_address) {
186 ACPI_FLUSH_CPU_CACHE();
187 halt();
188 } else {
189 ACPI_FLUSH_CPU_CACHE();
190 /* Invoke C3 */
191 inb(cx_address);
192 /* Dummy op - must do something useless after P_LVL3
193 * read */
194 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
196 longhaul.bits.EnableSoftVID = 0;
197 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
200 /* Change frequency on next halt or sleep */
201 longhaul.bits.EnableSoftBusRatio = 1;
202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
203 if (!cx_address) {
204 ACPI_FLUSH_CPU_CACHE();
205 halt();
206 } else {
207 ACPI_FLUSH_CPU_CACHE();
208 /* Invoke C3 */
209 inb(cx_address);
210 /* Dummy op - must do something useless after P_LVL3 read */
211 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
213 /* Disable bus ratio bit */
214 longhaul.bits.EnableSoftBusRatio = 0;
215 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
217 /* Reduce voltage if necessary */
218 if (can_scale_voltage && !dir) {
219 longhaul.bits.EnableSoftVID = 1;
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221 /* Change voltage */
222 if (!cx_address) {
223 ACPI_FLUSH_CPU_CACHE();
224 halt();
225 } else {
226 ACPI_FLUSH_CPU_CACHE();
227 /* Invoke C3 */
228 inb(cx_address);
229 /* Dummy op - must do something useless after P_LVL3
230 * read */
231 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
233 longhaul.bits.EnableSoftVID = 0;
234 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
239 * longhaul_set_cpu_frequency()
240 * @mults_index : bitpattern of the new multiplier.
242 * Sets a new clock ratio.
245 static int longhaul_setstate(struct cpufreq_policy *policy,
246 unsigned int table_index)
248 unsigned int mults_index;
249 int speed, mult;
250 struct cpufreq_freqs freqs;
251 unsigned long flags;
252 unsigned int pic1_mask, pic2_mask;
253 u16 bm_status = 0;
254 u32 bm_timeout = 1000;
255 unsigned int dir = 0;
257 mults_index = longhaul_table[table_index].driver_data;
258 /* Safety precautions */
259 mult = mults[mults_index & 0x1f];
260 if (mult == -1)
261 return -EINVAL;
263 speed = calc_speed(mult);
264 if ((speed > highest_speed) || (speed < lowest_speed))
265 return -EINVAL;
267 /* Voltage transition before frequency transition? */
268 if (can_scale_voltage && longhaul_index < table_index)
269 dir = 1;
271 freqs.old = calc_speed(longhaul_get_cpu_mult());
272 freqs.new = speed;
274 pr_debug("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
275 fsb, mult/10, mult%10, print_speed(speed/1000));
276 retry_loop:
277 preempt_disable();
278 local_irq_save(flags);
280 pic2_mask = inb(0xA1);
281 pic1_mask = inb(0x21); /* works on C3. save mask. */
282 outb(0xFF, 0xA1); /* Overkill */
283 outb(0xFE, 0x21); /* TMR0 only */
285 /* Wait while PCI bus is busy. */
286 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
287 || ((pr != NULL) && pr->flags.bm_control))) {
288 bm_status = inw(acpi_regs_addr);
289 bm_status &= 1 << 4;
290 while (bm_status && bm_timeout) {
291 outw(1 << 4, acpi_regs_addr);
292 bm_timeout--;
293 bm_status = inw(acpi_regs_addr);
294 bm_status &= 1 << 4;
298 if (longhaul_flags & USE_NORTHBRIDGE) {
299 /* Disable AGP and PCI arbiters */
300 outb(3, 0x22);
301 } else if ((pr != NULL) && pr->flags.bm_control) {
302 /* Disable bus master arbitration */
303 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
305 switch (longhaul_version) {
308 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
309 * Software controlled multipliers only.
311 case TYPE_LONGHAUL_V1:
312 do_longhaul1(mults_index);
313 break;
316 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
318 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
319 * Nehemiah can do FSB scaling too, but this has never been proven
320 * to work in practice.
322 case TYPE_LONGHAUL_V2:
323 case TYPE_POWERSAVER:
324 if (longhaul_flags & USE_ACPI_C3) {
325 /* Don't allow wakeup */
326 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
327 do_powersaver(cx->address, mults_index, dir);
328 } else {
329 do_powersaver(0, mults_index, dir);
331 break;
334 if (longhaul_flags & USE_NORTHBRIDGE) {
335 /* Enable arbiters */
336 outb(0, 0x22);
337 } else if ((pr != NULL) && pr->flags.bm_control) {
338 /* Enable bus master arbitration */
339 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
341 outb(pic2_mask, 0xA1); /* restore mask */
342 outb(pic1_mask, 0x21);
344 local_irq_restore(flags);
345 preempt_enable();
347 freqs.new = calc_speed(longhaul_get_cpu_mult());
348 /* Check if requested frequency is set. */
349 if (unlikely(freqs.new != speed)) {
350 printk(KERN_INFO PFX "Failed to set requested frequency!\n");
351 /* Revision ID = 1 but processor is expecting revision key
352 * equal to 0. Jumpers at the bottom of processor will change
353 * multiplier and FSB, but will not change bits in Longhaul
354 * MSR nor enable voltage scaling. */
355 if (!revid_errata) {
356 printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
357 "option.\n");
358 revid_errata = 1;
359 msleep(200);
360 goto retry_loop;
362 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
363 * But it does happen. Processor is entering ACPI C3 state,
364 * but it doesn't change frequency. I tried poking various
365 * bits in northbridge registers, but without success. */
366 if (longhaul_flags & USE_ACPI_C3) {
367 printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
368 longhaul_flags &= ~USE_ACPI_C3;
369 if (revid_errata) {
370 printk(KERN_INFO PFX "Disabling \"Ignore "
371 "Revision ID\" option.\n");
372 revid_errata = 0;
374 msleep(200);
375 goto retry_loop;
377 /* This shouldn't happen. Longhaul ver. 2 was reported not
378 * working on processors without voltage scaling, but with
379 * RevID = 1. RevID errata will make things right. Just
380 * to be 100% sure. */
381 if (longhaul_version == TYPE_LONGHAUL_V2) {
382 printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
383 longhaul_version = TYPE_LONGHAUL_V1;
384 msleep(200);
385 goto retry_loop;
389 if (!bm_timeout) {
390 printk(KERN_INFO PFX "Warning: Timeout while waiting for "
391 "idle PCI bus.\n");
392 return -EBUSY;
395 return 0;
399 * Centaur decided to make life a little more tricky.
400 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
401 * Samuel2 and above have to try and guess what the FSB is.
402 * We do this by assuming we booted at maximum multiplier, and interpolate
403 * between that value multiplied by possible FSBs and cpu_mhz which
404 * was calculated at boot time. Really ugly, but no other way to do this.
407 #define ROUNDING 0xf
409 static int guess_fsb(int mult)
411 int speed = cpu_khz / 1000;
412 int i;
413 int speeds[] = { 666, 1000, 1333, 2000 };
414 int f_max, f_min;
416 for (i = 0; i < 4; i++) {
417 f_max = ((speeds[i] * mult) + 50) / 100;
418 f_max += (ROUNDING / 2);
419 f_min = f_max - ROUNDING;
420 if ((speed <= f_max) && (speed >= f_min))
421 return speeds[i] / 10;
423 return 0;
427 static int longhaul_get_ranges(void)
429 unsigned int i, j, k = 0;
430 unsigned int ratio;
431 int mult;
433 /* Get current frequency */
434 mult = longhaul_get_cpu_mult();
435 if (mult == -1) {
436 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
437 return -EINVAL;
439 fsb = guess_fsb(mult);
440 if (fsb == 0) {
441 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
442 return -EINVAL;
444 /* Get max multiplier - as we always did.
445 * Longhaul MSR is useful only when voltage scaling is enabled.
446 * C3 is booting at max anyway. */
447 maxmult = mult;
448 /* Get min multiplier */
449 switch (cpu_model) {
450 case CPU_NEHEMIAH:
451 minmult = 50;
452 break;
453 case CPU_NEHEMIAH_C:
454 minmult = 40;
455 break;
456 default:
457 minmult = 30;
458 break;
461 pr_debug("MinMult:%d.%dx MaxMult:%d.%dx\n",
462 minmult/10, minmult%10, maxmult/10, maxmult%10);
464 highest_speed = calc_speed(maxmult);
465 lowest_speed = calc_speed(minmult);
466 pr_debug("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
467 print_speed(lowest_speed/1000),
468 print_speed(highest_speed/1000));
470 if (lowest_speed == highest_speed) {
471 printk(KERN_INFO PFX "highestspeed == lowest, aborting.\n");
472 return -EINVAL;
474 if (lowest_speed > highest_speed) {
475 printk(KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
476 lowest_speed, highest_speed);
477 return -EINVAL;
480 longhaul_table = kzalloc((numscales + 1) * sizeof(*longhaul_table),
481 GFP_KERNEL);
482 if (!longhaul_table)
483 return -ENOMEM;
485 for (j = 0; j < numscales; j++) {
486 ratio = mults[j];
487 if (ratio == -1)
488 continue;
489 if (ratio > maxmult || ratio < minmult)
490 continue;
491 longhaul_table[k].frequency = calc_speed(ratio);
492 longhaul_table[k].driver_data = j;
493 k++;
495 if (k <= 1) {
496 kfree(longhaul_table);
497 return -ENODEV;
499 /* Sort */
500 for (j = 0; j < k - 1; j++) {
501 unsigned int min_f, min_i;
502 min_f = longhaul_table[j].frequency;
503 min_i = j;
504 for (i = j + 1; i < k; i++) {
505 if (longhaul_table[i].frequency < min_f) {
506 min_f = longhaul_table[i].frequency;
507 min_i = i;
510 if (min_i != j) {
511 swap(longhaul_table[j].frequency,
512 longhaul_table[min_i].frequency);
513 swap(longhaul_table[j].driver_data,
514 longhaul_table[min_i].driver_data);
518 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
520 /* Find index we are running on */
521 for (j = 0; j < k; j++) {
522 if (mults[longhaul_table[j].driver_data & 0x1f] == mult) {
523 longhaul_index = j;
524 break;
527 return 0;
531 static void longhaul_setup_voltagescaling(void)
533 struct cpufreq_frequency_table *freq_pos;
534 union msr_longhaul longhaul;
535 struct mV_pos minvid, maxvid, vid;
536 unsigned int j, speed, pos, kHz_step, numvscales;
537 int min_vid_speed;
539 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
540 if (!(longhaul.bits.RevisionID & 1)) {
541 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
542 return;
545 if (!longhaul.bits.VRMRev) {
546 printk(KERN_INFO PFX "VRM 8.5\n");
547 vrm_mV_table = &vrm85_mV[0];
548 mV_vrm_table = &mV_vrm85[0];
549 } else {
550 printk(KERN_INFO PFX "Mobile VRM\n");
551 if (cpu_model < CPU_NEHEMIAH)
552 return;
553 vrm_mV_table = &mobilevrm_mV[0];
554 mV_vrm_table = &mV_mobilevrm[0];
557 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
558 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
560 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
561 printk(KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
562 "Voltage scaling disabled.\n",
563 minvid.mV/1000, minvid.mV%1000,
564 maxvid.mV/1000, maxvid.mV%1000);
565 return;
568 if (minvid.mV == maxvid.mV) {
569 printk(KERN_INFO PFX "Claims to support voltage scaling but "
570 "min & max are both %d.%03d. "
571 "Voltage scaling disabled\n",
572 maxvid.mV/1000, maxvid.mV%1000);
573 return;
576 /* How many voltage steps*/
577 numvscales = maxvid.pos - minvid.pos + 1;
578 printk(KERN_INFO PFX
579 "Max VID=%d.%03d "
580 "Min VID=%d.%03d, "
581 "%d possible voltage scales\n",
582 maxvid.mV/1000, maxvid.mV%1000,
583 minvid.mV/1000, minvid.mV%1000,
584 numvscales);
586 /* Calculate max frequency at min voltage */
587 j = longhaul.bits.MinMHzBR;
588 if (longhaul.bits.MinMHzBR4)
589 j += 16;
590 min_vid_speed = eblcr[j];
591 if (min_vid_speed == -1)
592 return;
593 switch (longhaul.bits.MinMHzFSB) {
594 case 0:
595 min_vid_speed *= 13333;
596 break;
597 case 1:
598 min_vid_speed *= 10000;
599 break;
600 case 3:
601 min_vid_speed *= 6666;
602 break;
603 default:
604 return;
605 break;
607 if (min_vid_speed >= highest_speed)
608 return;
609 /* Calculate kHz for one voltage step */
610 kHz_step = (highest_speed - min_vid_speed) / numvscales;
612 cpufreq_for_each_entry(freq_pos, longhaul_table) {
613 speed = freq_pos->frequency;
614 if (speed > min_vid_speed)
615 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
616 else
617 pos = minvid.pos;
618 freq_pos->driver_data |= mV_vrm_table[pos] << 8;
619 vid = vrm_mV_table[mV_vrm_table[pos]];
620 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n",
621 speed, (int)(freq_pos - longhaul_table), vid.mV);
624 can_scale_voltage = 1;
625 printk(KERN_INFO PFX "Voltage scaling enabled.\n");
629 static int longhaul_target(struct cpufreq_policy *policy,
630 unsigned int table_index)
632 unsigned int i;
633 unsigned int dir = 0;
634 u8 vid, current_vid;
635 int retval = 0;
637 if (!can_scale_voltage)
638 retval = longhaul_setstate(policy, table_index);
639 else {
640 /* On test system voltage transitions exceeding single
641 * step up or down were turning motherboard off. Both
642 * "ondemand" and "userspace" are unsafe. C7 is doing
643 * this in hardware, C3 is old and we need to do this
644 * in software. */
645 i = longhaul_index;
646 current_vid = (longhaul_table[longhaul_index].driver_data >> 8);
647 current_vid &= 0x1f;
648 if (table_index > longhaul_index)
649 dir = 1;
650 while (i != table_index) {
651 vid = (longhaul_table[i].driver_data >> 8) & 0x1f;
652 if (vid != current_vid) {
653 retval = longhaul_setstate(policy, i);
654 current_vid = vid;
655 msleep(200);
657 if (dir)
658 i++;
659 else
660 i--;
662 retval = longhaul_setstate(policy, table_index);
665 longhaul_index = table_index;
666 return retval;
670 static unsigned int longhaul_get(unsigned int cpu)
672 if (cpu)
673 return 0;
674 return calc_speed(longhaul_get_cpu_mult());
677 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
678 u32 nesting_level,
679 void *context, void **return_value)
681 struct acpi_device *d;
683 if (acpi_bus_get_device(obj_handle, &d))
684 return 0;
686 *return_value = acpi_driver_data(d);
687 return 1;
690 /* VIA don't support PM2 reg, but have something similar */
691 static int enable_arbiter_disable(void)
693 struct pci_dev *dev;
694 int status = 1;
695 int reg;
696 u8 pci_cmd;
698 /* Find PLE133 host bridge */
699 reg = 0x78;
700 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
701 NULL);
702 /* Find PM133/VT8605 host bridge */
703 if (dev == NULL)
704 dev = pci_get_device(PCI_VENDOR_ID_VIA,
705 PCI_DEVICE_ID_VIA_8605_0, NULL);
706 /* Find CLE266 host bridge */
707 if (dev == NULL) {
708 reg = 0x76;
709 dev = pci_get_device(PCI_VENDOR_ID_VIA,
710 PCI_DEVICE_ID_VIA_862X_0, NULL);
711 /* Find CN400 V-Link host bridge */
712 if (dev == NULL)
713 dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
715 if (dev != NULL) {
716 /* Enable access to port 0x22 */
717 pci_read_config_byte(dev, reg, &pci_cmd);
718 if (!(pci_cmd & 1<<7)) {
719 pci_cmd |= 1<<7;
720 pci_write_config_byte(dev, reg, pci_cmd);
721 pci_read_config_byte(dev, reg, &pci_cmd);
722 if (!(pci_cmd & 1<<7)) {
723 printk(KERN_ERR PFX
724 "Can't enable access to port 0x22.\n");
725 status = 0;
728 pci_dev_put(dev);
729 return status;
731 return 0;
734 static int longhaul_setup_southbridge(void)
736 struct pci_dev *dev;
737 u8 pci_cmd;
739 /* Find VT8235 southbridge */
740 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
741 if (dev == NULL)
742 /* Find VT8237 southbridge */
743 dev = pci_get_device(PCI_VENDOR_ID_VIA,
744 PCI_DEVICE_ID_VIA_8237, NULL);
745 if (dev != NULL) {
746 /* Set transition time to max */
747 pci_read_config_byte(dev, 0xec, &pci_cmd);
748 pci_cmd &= ~(1 << 2);
749 pci_write_config_byte(dev, 0xec, pci_cmd);
750 pci_read_config_byte(dev, 0xe4, &pci_cmd);
751 pci_cmd &= ~(1 << 7);
752 pci_write_config_byte(dev, 0xe4, pci_cmd);
753 pci_read_config_byte(dev, 0xe5, &pci_cmd);
754 pci_cmd |= 1 << 7;
755 pci_write_config_byte(dev, 0xe5, pci_cmd);
756 /* Get address of ACPI registers block*/
757 pci_read_config_byte(dev, 0x81, &pci_cmd);
758 if (pci_cmd & 1 << 7) {
759 pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
760 acpi_regs_addr &= 0xff00;
761 printk(KERN_INFO PFX "ACPI I/O at 0x%x\n",
762 acpi_regs_addr);
765 pci_dev_put(dev);
766 return 1;
768 return 0;
771 static int longhaul_cpu_init(struct cpufreq_policy *policy)
773 struct cpuinfo_x86 *c = &cpu_data(0);
774 char *cpuname = NULL;
775 int ret;
776 u32 lo, hi;
778 /* Check what we have on this motherboard */
779 switch (c->x86_model) {
780 case 6:
781 cpu_model = CPU_SAMUEL;
782 cpuname = "C3 'Samuel' [C5A]";
783 longhaul_version = TYPE_LONGHAUL_V1;
784 memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
785 memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
786 break;
788 case 7:
789 switch (c->x86_mask) {
790 case 0:
791 longhaul_version = TYPE_LONGHAUL_V1;
792 cpu_model = CPU_SAMUEL2;
793 cpuname = "C3 'Samuel 2' [C5B]";
794 /* Note, this is not a typo, early Samuel2's had
795 * Samuel1 ratios. */
796 memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
797 memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
798 break;
799 case 1 ... 15:
800 longhaul_version = TYPE_LONGHAUL_V2;
801 if (c->x86_mask < 8) {
802 cpu_model = CPU_SAMUEL2;
803 cpuname = "C3 'Samuel 2' [C5B]";
804 } else {
805 cpu_model = CPU_EZRA;
806 cpuname = "C3 'Ezra' [C5C]";
808 memcpy(mults, ezra_mults, sizeof(ezra_mults));
809 memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
810 break;
812 break;
814 case 8:
815 cpu_model = CPU_EZRA_T;
816 cpuname = "C3 'Ezra-T' [C5M]";
817 longhaul_version = TYPE_POWERSAVER;
818 numscales = 32;
819 memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
820 memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
821 break;
823 case 9:
824 longhaul_version = TYPE_POWERSAVER;
825 numscales = 32;
826 memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
827 memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
828 switch (c->x86_mask) {
829 case 0 ... 1:
830 cpu_model = CPU_NEHEMIAH;
831 cpuname = "C3 'Nehemiah A' [C5XLOE]";
832 break;
833 case 2 ... 4:
834 cpu_model = CPU_NEHEMIAH;
835 cpuname = "C3 'Nehemiah B' [C5XLOH]";
836 break;
837 case 5 ... 15:
838 cpu_model = CPU_NEHEMIAH_C;
839 cpuname = "C3 'Nehemiah C' [C5P]";
840 break;
842 break;
844 default:
845 cpuname = "Unknown";
846 break;
848 /* Check Longhaul ver. 2 */
849 if (longhaul_version == TYPE_LONGHAUL_V2) {
850 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
851 if (lo == 0 && hi == 0)
852 /* Looks like MSR isn't present */
853 longhaul_version = TYPE_LONGHAUL_V1;
856 printk(KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
857 switch (longhaul_version) {
858 case TYPE_LONGHAUL_V1:
859 case TYPE_LONGHAUL_V2:
860 printk(KERN_CONT "Longhaul v%d supported.\n", longhaul_version);
861 break;
862 case TYPE_POWERSAVER:
863 printk(KERN_CONT "Powersaver supported.\n");
864 break;
867 /* Doesn't hurt */
868 longhaul_setup_southbridge();
870 /* Find ACPI data for processor */
871 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
872 ACPI_UINT32_MAX, &longhaul_walk_callback, NULL,
873 NULL, (void *)&pr);
875 /* Check ACPI support for C3 state */
876 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
877 cx = &pr->power.states[ACPI_STATE_C3];
878 if (cx->address > 0 && cx->latency <= 1000)
879 longhaul_flags |= USE_ACPI_C3;
881 /* Disable if it isn't working */
882 if (disable_acpi_c3)
883 longhaul_flags &= ~USE_ACPI_C3;
884 /* Check if northbridge is friendly */
885 if (enable_arbiter_disable())
886 longhaul_flags |= USE_NORTHBRIDGE;
888 /* Check ACPI support for bus master arbiter disable */
889 if (!(longhaul_flags & USE_ACPI_C3
890 || longhaul_flags & USE_NORTHBRIDGE)
891 && ((pr == NULL) || !(pr->flags.bm_control))) {
892 printk(KERN_ERR PFX
893 "No ACPI support. Unsupported northbridge.\n");
894 return -ENODEV;
897 if (longhaul_flags & USE_NORTHBRIDGE)
898 printk(KERN_INFO PFX "Using northbridge support.\n");
899 if (longhaul_flags & USE_ACPI_C3)
900 printk(KERN_INFO PFX "Using ACPI support.\n");
902 ret = longhaul_get_ranges();
903 if (ret != 0)
904 return ret;
906 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
907 longhaul_setup_voltagescaling();
909 policy->cpuinfo.transition_latency = 200000; /* nsec */
911 return cpufreq_table_validate_and_show(policy, longhaul_table);
914 static struct cpufreq_driver longhaul_driver = {
915 .verify = cpufreq_generic_frequency_table_verify,
916 .target_index = longhaul_target,
917 .get = longhaul_get,
918 .init = longhaul_cpu_init,
919 .name = "longhaul",
920 .attr = cpufreq_generic_attr,
923 static const struct x86_cpu_id longhaul_id[] = {
924 { X86_VENDOR_CENTAUR, 6 },
927 MODULE_DEVICE_TABLE(x86cpu, longhaul_id);
929 static int __init longhaul_init(void)
931 struct cpuinfo_x86 *c = &cpu_data(0);
933 if (!x86_match_cpu(longhaul_id))
934 return -ENODEV;
936 if (!enable) {
937 printk(KERN_ERR PFX "Option \"enable\" not set. Aborting.\n");
938 return -ENODEV;
940 #ifdef CONFIG_SMP
941 if (num_online_cpus() > 1) {
942 printk(KERN_ERR PFX "More than 1 CPU detected, "
943 "longhaul disabled.\n");
944 return -ENODEV;
946 #endif
947 #ifdef CONFIG_X86_IO_APIC
948 if (cpu_has_apic) {
949 printk(KERN_ERR PFX "APIC detected. Longhaul is currently "
950 "broken in this configuration.\n");
951 return -ENODEV;
953 #endif
954 switch (c->x86_model) {
955 case 6 ... 9:
956 return cpufreq_register_driver(&longhaul_driver);
957 case 10:
958 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
959 default:
963 return -ENODEV;
967 static void __exit longhaul_exit(void)
969 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
970 int i;
972 for (i = 0; i < numscales; i++) {
973 if (mults[i] == maxmult) {
974 struct cpufreq_freqs freqs;
976 freqs.old = policy->cur;
977 freqs.new = longhaul_table[i].frequency;
978 freqs.flags = 0;
980 cpufreq_freq_transition_begin(policy, &freqs);
981 longhaul_setstate(policy, i);
982 cpufreq_freq_transition_end(policy, &freqs, 0);
983 break;
987 cpufreq_cpu_put(policy);
988 cpufreq_unregister_driver(&longhaul_driver);
989 kfree(longhaul_table);
992 /* Even if BIOS is exporting ACPI C3 state, and it is used
993 * with success when CPU is idle, this state doesn't
994 * trigger frequency transition in some cases. */
995 module_param(disable_acpi_c3, int, 0644);
996 MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
997 /* Change CPU voltage with frequency. Very useful to save
998 * power, but most VIA C3 processors aren't supporting it. */
999 module_param(scale_voltage, int, 0644);
1000 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1001 /* Force revision key to 0 for processors which doesn't
1002 * support voltage scaling, but are introducing itself as
1003 * such. */
1004 module_param(revid_errata, int, 0644);
1005 MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1006 /* By default driver is disabled to prevent incompatible
1007 * system freeze. */
1008 module_param(enable, int, 0644);
1009 MODULE_PARM_DESC(enable, "Enable driver");
1011 MODULE_AUTHOR("Dave Jones");
1012 MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1013 MODULE_LICENSE("GPL");
1015 late_initcall(longhaul_init);
1016 module_exit(longhaul_exit);