watchdog: pic32-dmt: Remove .owner field for driver
[linux/fpc-iii.git] / drivers / crypto / qat / qat_dh895xcc / adf_dh895xcc_hw_data.h
blob092f7353ed23388cb84cf3363cd90ab4d3594be7
1 /*
2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
5 GPL LICENSE SUMMARY
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 Contact Information:
17 qat-linux@intel.com
19 BSD LICENSE
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
23 are met:
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
30 distribution.
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 #ifndef ADF_DH895x_HW_DATA_H_
48 #define ADF_DH895x_HW_DATA_H_
50 /* PCIe configuration space */
51 #define ADF_DH895XCC_SRAM_BAR 0
52 #define ADF_DH895XCC_PMISC_BAR 1
53 #define ADF_DH895XCC_ETR_BAR 2
54 #define ADF_DH895XCC_RX_RINGS_OFFSET 8
55 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF
56 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
57 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20
58 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
59 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
60 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
61 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
62 #define ADF_DH895XCC_MAX_ACCELERATORS 6
63 #define ADF_DH895XCC_MAX_ACCELENGINES 12
64 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13
65 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
66 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
67 #define ADF_DH895XCC_ETR_MAX_BANKS 32
68 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
69 #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
70 #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF
71 #define ADF_DH895XCC_SMIA1_MASK 0x1
72 /* Error detection and correction */
73 #define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
74 #define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
75 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28)
76 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
77 #define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18)
78 #define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10)
79 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
81 #define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
82 #define ADF_DH895XCC_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i) * 0x04))
83 /* FW names */
84 #define ADF_DH895XCC_FW "qat_895xcc.bin"
85 #define ADF_DH895XCC_MMP "qat_895xcc_mmp.bin"
87 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
88 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
89 #endif