drivers/phy/phy-qcom-ufs-qmp-20nm.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-qmp-20nm.h"
  16
  17 #define UFS_PHY_NAME "ufs_phy_qmp_20nm"
  18
  19 static
  20 int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  21                                         bool is_rate_B)
  22 {
  23         struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
  24         int tbl_size_A, tbl_size_B;
  25         u8 major = ufs_qcom_phy->host_ctrl_rev_major;
  26         u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
  27         u16 step = ufs_qcom_phy->host_ctrl_rev_step;
  28         int err;
  29
  30         if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
  31                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
  32                 tbl_A = phy_cal_table_rate_A_1_2_0;
  33         } else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
  34                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
  35                 tbl_A = phy_cal_table_rate_A_1_3_0;
  36         } else {
  37                 dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
  38                         __func__);
  39                 err = -ENODEV;
  40                 goto out;
  41         }
  42
  43         tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
  44         tbl_B = phy_cal_table_rate_B;
  45
  46         err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
  47                                                 tbl_B, tbl_size_B, is_rate_B);
  48
  49         if (err)
  50                 dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
  51                         __func__, err);
  52
  53 out:
  54         return err;
  55 }
  56
  57 static
  58 void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
  59 {
  60         phy_common->quirks =
  61                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
  62 }
  63
  64 static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
  65 {
  66         struct ufs_qcom_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
  67         struct ufs_qcom_phy *phy_common = &phy->common_cfg;
  68         int err = 0;
  69
  70         err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
  71         if (err) {
  72                 dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
  73                         __func__, err);
  74                 goto out;
  75         }
  76
  77         err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
  78         if (err) {
  79                 dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
  80                         __func__, err);
  81                 goto out;
  82         }
  83
  84         ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
  85
  86 out:
  87         return err;
  88 }
  89
  90 static
  91 void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
  92 {
  93         bool hibern8_exit_after_pwr_collapse = phy->quirks &
  94                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
  95
  96         if (val) {
  97                 writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  98                 /*
  99                  * Before any transactions involving PHY, ensure PHY knows
 100                  * that it's analog rail is powered ON.
 101                  */
 102                 mb();
 103
 104                 if (hibern8_exit_after_pwr_collapse) {
 105                         /*
 106                          * Give atleast 1us delay after restoring PHY analog
 107                          * power.
 108                          */
 109                         usleep_range(1, 2);
 110                         writel_relaxed(0x0A, phy->mmio +
 111                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 112                         writel_relaxed(0x08, phy->mmio +
 113                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 114                         /*
 115                          * Make sure workaround is deactivated before proceeding
 116                          * with normal PHY operations.
 117                          */
 118                         mb();
 119                 }
 120         } else {
 121                 if (hibern8_exit_after_pwr_collapse) {
 122                         writel_relaxed(0x0A, phy->mmio +
 123                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 124                         writel_relaxed(0x02, phy->mmio +
 125                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 126                         /*
 127                          * Make sure that above workaround is activated before
 128                          * PHY analog power collapse.
 129                          */
 130                         mb();
 131                 }
 132
 133                 writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
 134                 /*
 135                  * ensure that PHY knows its PHY analog rail is going
 136                  * to be powered down
 137                  */
 138                 mb();
 139         }
 140 }
 141
 142 static
 143 void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
 144 {
 145         writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
 146                         phy->mmio + UFS_PHY_TX_LANE_ENABLE);
 147         mb();
 148 }
 149
 150 static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
 151 {
 152         u32 tmp;
 153
 154         tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
 155         tmp &= ~MASK_SERDES_START;
 156         tmp |= (1 << OFFSET_SERDES_START);
 157         writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
 158         mb();
 159 }
 160
 161 static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 162 {
 163         int err = 0;
 164         u32 val;
 165
 166         err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
 167                         val, (val & MASK_PCS_READY), 10, 1000000);
 168         if (err)
 169                 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
 170                         __func__, err);
 171         return err;
 172 }
 173
 174 static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
 175         .init           = ufs_qcom_phy_qmp_20nm_init,
 176         .exit           = ufs_qcom_phy_exit,
 177         .power_on       = ufs_qcom_phy_power_on,
 178         .power_off      = ufs_qcom_phy_power_off,
 179         .owner          = THIS_MODULE,
 180 };
 181
 182 static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
 183         .calibrate_phy          = ufs_qcom_phy_qmp_20nm_phy_calibrate,
 184         .start_serdes           = ufs_qcom_phy_qmp_20nm_start_serdes,
 185         .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
 186         .set_tx_lane_enable     = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
 187         .power_control          = ufs_qcom_phy_qmp_20nm_power_control,
 188 };
 189
 190 static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
 191 {
 192         struct device *dev = &pdev->dev;
 193         struct phy *generic_phy;
 194         struct ufs_qcom_phy_qmp_20nm *phy;
 195         int err = 0;
 196
 197         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 198         if (!phy) {
 199                 dev_err(dev, "%s: failed to allocate phy\n", __func__);
 200                 err = -ENOMEM;
 201                 goto out;
 202         }
 203
 204         generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
 205                                 &ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
 206
 207         if (!generic_phy) {
 208                 dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
 209                         __func__);
 210                 err = -EIO;
 211                 goto out;
 212         }
 213
 214         phy_set_drvdata(generic_phy, phy);
 215
 216         strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
 217                         sizeof(phy->common_cfg.name));
 218
 219 out:
 220         return err;
 221 }
 222
 223 static int ufs_qcom_phy_qmp_20nm_remove(struct platform_device *pdev)
 224 {
 225         struct device *dev = &pdev->dev;
 226         struct phy *generic_phy = to_phy(dev);
 227         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 228         int err = 0;
 229
 230         err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
 231         if (err)
 232                 dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
 233                         __func__, err);
 234
 235         return err;
 236 }
 237
 238 static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
 239         {.compatible = "qcom,ufs-phy-qmp-20nm"},
 240         {},
 241 };
 242 MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
 243
 244 static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
 245         .probe = ufs_qcom_phy_qmp_20nm_probe,
 246         .remove = ufs_qcom_phy_qmp_20nm_remove,
 247         .driver = {
 248                 .of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
 249                 .name = "ufs_qcom_phy_qmp_20nm",
 250         },
 251 };
 252
 253 module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
 254
 255 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
 256 MODULE_LICENSE("GPL v2");