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drm/nouveau/tegra: Fix error handling
[linux/fpc-iii.git] / arch / x86 / events / intel / ds.c
blob0319311dbdbb548eef4f5b2431c285deea5dd00c
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "../perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 /* Version for Sandy Bridge and later */
55 static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
72 };
73
74 /* Patch up minor differences in the bits */
75 void __init intel_pmu_pebs_data_source_nhm(void)
76 {
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
80 }
81
82 static u64 precise_store_data(u64 status)
83 {
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
86
87 dse.val = status;
88
89 /*
90 * bit 4: TLB access
91 * 1 = stored missed 2nd level TLB
92 *
93 * so it either hit the walker or the OS
94 * otherwise hit 2nd level TLB
95 */
96 if (dse.st_stlb_miss)
97 val |= P(TLB, MISS);
98 else
99 val |= P(TLB, HIT);
100
101 /*
102 * bit 0: hit L1 data cache
103 * if not set, then all we know is that
104 * it missed L1D
105 */
106 if (dse.st_l1d_hit)
107 val |= P(LVL, HIT);
108 else
109 val |= P(LVL, MISS);
110
111 /*
112 * bit 5: Locked prefix
113 */
114 if (dse.st_locked)
115 val |= P(LOCK, LOCKED);
116
117 return val;
118 }
119
120 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
121 {
122 union perf_mem_data_src dse;
123
124 dse.val = PERF_MEM_NA;
125
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
130
131 /*
132 * L1 info only valid for following events:
133 *
134 * MEM_UOPS_RETIRED.STLB_MISS_STORES
135 * MEM_UOPS_RETIRED.LOCK_STORES
136 * MEM_UOPS_RETIRED.SPLIT_STORES
137 * MEM_UOPS_RETIRED.ALL_STORES
138 */
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
140 if (status & 1)
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
142 else
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
144 }
145 return dse.val;
146 }
147
148 static u64 load_latency_data(u64 status)
149 {
150 union intel_x86_pebs_dse dse;
151 u64 val;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
154
155 dse.val = status;
156
157 /*
158 * use the mapping table for bit 0-3
159 */
160 val = pebs_data_source[dse.ld_dse];
161
162 /*
163 * Nehalem models do not support TLB, Lock infos
164 */
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
168 return val;
169 }
170 /*
171 * bit 4: TLB access
172 * 0 = did not miss 2nd level TLB
173 * 1 = missed 2nd level TLB
174 */
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
177 else
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
179
180 /*
181 * bit 5: locked prefix
182 */
183 if (dse.ld_locked)
184 val |= P(LOCK, LOCKED);
185
186 return val;
187 }
188
189 struct pebs_record_core {
190 u64 flags, ip;
191 u64 ax, bx, cx, dx;
192 u64 si, di, bp, sp;
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195 };
196
197 struct pebs_record_nhm {
198 u64 flags, ip;
199 u64 ax, bx, cx, dx;
200 u64 si, di, bp, sp;
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
204 };
205
206 /*
207 * Same as pebs_record_nhm, with two additional fields.
208 */
209 struct pebs_record_hsw {
210 u64 flags, ip;
211 u64 ax, bx, cx, dx;
212 u64 si, di, bp, sp;
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
217 };
218
219 union hsw_tsx_tuning {
220 struct {
221 u32 cycles_last_block : 32,
222 hle_abort : 1,
223 rtm_abort : 1,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
226 retry : 1,
227 data_conflict : 1,
228 capacity_writes : 1,
229 capacity_reads : 1;
230 };
231 u64 value;
232 };
233
234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
235
236 /* Same as HSW, plus TSC */
237
238 struct pebs_record_skl {
239 u64 flags, ip;
240 u64 ax, bx, cx, dx;
241 u64 si, di, bp, sp;
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
246 u64 tsc;
247 };
248
249 void init_debug_store_on_cpu(int cpu)
250 {
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252
253 if (!ds)
254 return;
255
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
259 }
260
261 void fini_debug_store_on_cpu(int cpu)
262 {
263 if (!per_cpu(cpu_hw_events, cpu).ds)
264 return;
265
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
267 }
268
269 static DEFINE_PER_CPU(void *, insn_buffer);
270
271 static int alloc_pebs_buffer(int cpu)
272 {
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
275 int max;
276 void *buffer, *ibuffer;
277
278 if (!x86_pmu.pebs)
279 return 0;
280
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
283 return -ENOMEM;
284
285 /*
286 * HSW+ already provides us the eventing ip; no need to allocate this
287 * buffer then.
288 */
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
291 if (!ibuffer) {
292 kfree(buffer);
293 return -ENOMEM;
294 }
295 per_cpu(insn_buffer, cpu) = ibuffer;
296 }
297
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
299
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
304
305 return 0;
306 }
307
308 static void release_pebs_buffer(int cpu)
309 {
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
311
312 if (!ds || !x86_pmu.pebs)
313 return;
314
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
317
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
320 }
321
322 static int alloc_bts_buffer(int cpu)
323 {
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
326 int max, thresh;
327 void *buffer;
328
329 if (!x86_pmu.bts)
330 return 0;
331
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
335 return -ENOMEM;
336 }
337
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
339 thresh = max / 16;
340
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
347
348 return 0;
349 }
350
351 static void release_bts_buffer(int cpu)
352 {
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
354
355 if (!ds || !x86_pmu.bts)
356 return;
357
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
360 }
361
362 static int alloc_ds_buffer(int cpu)
363 {
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
366
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
368 if (unlikely(!ds))
369 return -ENOMEM;
370
371 per_cpu(cpu_hw_events, cpu).ds = ds;
372
373 return 0;
374 }
375
376 static void release_ds_buffer(int cpu)
377 {
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
379
380 if (!ds)
381 return;
382
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
384 kfree(ds);
385 }
386
387 void release_ds_buffers(void)
388 {
389 int cpu;
390
391 if (!x86_pmu.bts && !x86_pmu.pebs)
392 return;
393
394 get_online_cpus();
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
397
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
402 }
403 put_online_cpus();
404 }
405
406 void reserve_ds_buffers(void)
407 {
408 int bts_err = 0, pebs_err = 0;
409 int cpu;
410
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
413
414 if (!x86_pmu.bts && !x86_pmu.pebs)
415 return;
416
417 if (!x86_pmu.bts)
418 bts_err = 1;
419
420 if (!x86_pmu.pebs)
421 pebs_err = 1;
422
423 get_online_cpus();
424
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
427 bts_err = 1;
428 pebs_err = 1;
429 }
430
431 if (!bts_err && alloc_bts_buffer(cpu))
432 bts_err = 1;
433
434 if (!pebs_err && alloc_pebs_buffer(cpu))
435 pebs_err = 1;
436
437 if (bts_err && pebs_err)
438 break;
439 }
440
441 if (bts_err) {
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
444 }
445
446 if (pebs_err) {
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
449 }
450
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
454 } else {
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
457
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
460
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
463 }
464
465 put_online_cpus();
466 }
467
468 /*
469 * BTS
470 */
471
472 struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
474
475 void intel_pmu_enable_bts(u64 config)
476 {
477 unsigned long debugctlmsr;
478
479 debugctlmsr = get_debugctlmsr();
480
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
485
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
488
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
491
492 update_debugctlmsr(debugctlmsr);
493 }
494
495 void intel_pmu_disable_bts(void)
496 {
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
499
500 if (!cpuc->ds)
501 return;
502
503 debugctlmsr = get_debugctlmsr();
504
505 debugctlmsr &=
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
508
509 update_debugctlmsr(debugctlmsr);
510 }
511
512 int intel_pmu_drain_bts_buffer(void)
513 {
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
516 struct bts_record {
517 u64 from;
518 u64 to;
519 u64 flags;
520 };
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
527 struct pt_regs regs;
528
529 if (!event)
530 return 0;
531
532 if (!x86_pmu.bts_active)
533 return 0;
534
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
537
538 if (top <= base)
539 return 0;
540
541 memset(&regs, 0, sizeof(regs));
542
543 ds->bts_index = ds->bts_buffer_base;
544
545 perf_sample_data_init(&data, 0, event->hw.last_period);
546
547 /*
548 * BTS leaks kernel addresses in branches across the cpl boundary,
549 * such as traps or system calls, so unless the user is asking for
550 * kernel tracing (and right now it's not possible), we'd need to
551 * filter them out. But first we need to count how many of those we
552 * have in the current batch. This is an extra O(n) pass, however,
553 * it's much faster than the other one especially considering that
554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
555 * alloc_bts_buffer()).
556 */
557 for (at = base; at < top; at++) {
558 /*
559 * Note that right now *this* BTS code only works if
560 * attr::exclude_kernel is set, but let's keep this extra
561 * check here in case that changes.
562 */
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
565 skip++;
566 }
567
568 /*
569 * Prepare a generic sample, i.e. fill in the invariant fields.
570 * We will overwrite the from and to address before we output
571 * the sample.
572 */
573 rcu_read_lock();
574 perf_prepare_sample(&header, &data, event, &regs);
575
576 if (perf_output_begin(&handle, event, header.size *
577 (top - base - skip)))
578 goto unlock;
579
580 for (at = base; at < top; at++) {
581 /* Filter out any records that contain kernel addresses. */
582 if (event->attr.exclude_kernel &&
583 (kernel_ip(at->from) || kernel_ip(at->to)))
584 continue;
585
586 data.ip = at->from;
587 data.addr = at->to;
588
589 perf_output_sample(&handle, &header, &data, event);
590 }
591
592 perf_output_end(&handle);
593
594 /* There's new data available. */
595 event->hw.interrupts++;
596 event->pending_kill = POLL_IN;
597 unlock:
598 rcu_read_unlock();
599 return 1;
600 }
601
602 static inline void intel_pmu_drain_pebs_buffer(void)
603 {
604 struct pt_regs regs;
605
606 x86_pmu.drain_pebs(&regs);
607 }
608
609 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
610 {
611 if (!sched_in)
612 intel_pmu_drain_pebs_buffer();
613 }
614
615 /*
616 * PEBS
617 */
618 struct event_constraint intel_core2_pebs_event_constraints[] = {
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
620 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
621 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
622 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
623 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
624 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
626 EVENT_CONSTRAINT_END
627 };
628
629 struct event_constraint intel_atom_pebs_event_constraints[] = {
630 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
631 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
632 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
633 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
634 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
635 /* Allow all events as PEBS with no flags */
636 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
637 EVENT_CONSTRAINT_END
638 };
639
640 struct event_constraint intel_slm_pebs_event_constraints[] = {
641 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
642 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
643 /* Allow all events as PEBS with no flags */
644 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
645 EVENT_CONSTRAINT_END
646 };
647
648 struct event_constraint intel_glm_pebs_event_constraints[] = {
649 /* Allow all events as PEBS with no flags */
650 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
651 EVENT_CONSTRAINT_END
652 };
653
654 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
655 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
656 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
657 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
658 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
659 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
660 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
661 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
663 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
665 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
666 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
667 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
668 EVENT_CONSTRAINT_END
669 };
670
671 struct event_constraint intel_westmere_pebs_event_constraints[] = {
672 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
673 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
674 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
675 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
676 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
677 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
678 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
679 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
680 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
681 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
683 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
684 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
685 EVENT_CONSTRAINT_END
686 };
687
688 struct event_constraint intel_snb_pebs_event_constraints[] = {
689 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
690 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
691 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
692 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
693 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
694 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
695 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
696 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
697 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
698 /* Allow all events as PEBS with no flags */
699 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
700 EVENT_CONSTRAINT_END
701 };
702
703 struct event_constraint intel_ivb_pebs_event_constraints[] = {
704 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
705 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
706 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
707 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
708 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
709 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
710 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
711 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
712 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
713 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
714 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
715 /* Allow all events as PEBS with no flags */
716 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
717 EVENT_CONSTRAINT_END
718 };
719
720 struct event_constraint intel_hsw_pebs_event_constraints[] = {
721 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
722 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
723 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
724 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
725 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
726 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
727 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
728 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
729 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
730 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
731 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
732 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
733 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
734 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
735 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
736 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
737 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
738 /* Allow all events as PEBS with no flags */
739 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
740 EVENT_CONSTRAINT_END
741 };
742
743 struct event_constraint intel_bdw_pebs_event_constraints[] = {
744 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
745 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
746 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
747 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
748 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
749 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
750 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
751 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
752 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
753 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
754 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
755 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
756 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
757 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
758 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
759 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
760 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
761 /* Allow all events as PEBS with no flags */
762 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
763 EVENT_CONSTRAINT_END
764 };
765
766
767 struct event_constraint intel_skl_pebs_event_constraints[] = {
768 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
769 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
770 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
771 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
772 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
773 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
774 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
775 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
776 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
777 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
778 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
779 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
780 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
781 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
782 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
783 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
784 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
785 /* Allow all events as PEBS with no flags */
786 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
787 EVENT_CONSTRAINT_END
788 };
789
790 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
791 {
792 struct event_constraint *c;
793
794 if (!event->attr.precise_ip)
795 return NULL;
796
797 if (x86_pmu.pebs_constraints) {
798 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
799 if ((event->hw.config & c->cmask) == c->code) {
800 event->hw.flags |= c->flags;
801 return c;
802 }
803 }
804 }
805
806 return &emptyconstraint;
807 }
808
809 /*
810 * We need the sched_task callback even for per-cpu events when we use
811 * the large interrupt threshold, such that we can provide PID and TID
812 * to PEBS samples.
813 */
814 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
815 {
816 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
817 }
818
819 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
820 {
821 struct debug_store *ds = cpuc->ds;
822 u64 threshold;
823
824 if (cpuc->n_pebs == cpuc->n_large_pebs) {
825 threshold = ds->pebs_absolute_maximum -
826 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
827 } else {
828 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
829 }
830
831 ds->pebs_interrupt_threshold = threshold;
832 }
833
834 static void
835 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
836 {
837 /*
838 * Make sure we get updated with the first PEBS
839 * event. It will trigger also during removal, but
840 * that does not hurt:
841 */
842 bool update = cpuc->n_pebs == 1;
843
844 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
845 if (!needed_cb)
846 perf_sched_cb_inc(pmu);
847 else
848 perf_sched_cb_dec(pmu);
849
850 update = true;
851 }
852
853 if (update)
854 pebs_update_threshold(cpuc);
855 }
856
857 void intel_pmu_pebs_add(struct perf_event *event)
858 {
859 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
860 struct hw_perf_event *hwc = &event->hw;
861 bool needed_cb = pebs_needs_sched_cb(cpuc);
862
863 cpuc->n_pebs++;
864 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
865 cpuc->n_large_pebs++;
866
867 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
868 }
869
870 void intel_pmu_pebs_enable(struct perf_event *event)
871 {
872 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
873 struct hw_perf_event *hwc = &event->hw;
874 struct debug_store *ds = cpuc->ds;
875
876 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
877
878 cpuc->pebs_enabled |= 1ULL << hwc->idx;
879
880 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
881 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
882 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
883 cpuc->pebs_enabled |= 1ULL << 63;
884
885 /*
886 * Use auto-reload if possible to save a MSR write in the PMI.
887 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
888 */
889 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
890 ds->pebs_event_reset[hwc->idx] =
891 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
892 }
893 }
894
895 void intel_pmu_pebs_del(struct perf_event *event)
896 {
897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
898 struct hw_perf_event *hwc = &event->hw;
899 bool needed_cb = pebs_needs_sched_cb(cpuc);
900
901 cpuc->n_pebs--;
902 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
903 cpuc->n_large_pebs--;
904
905 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
906 }
907
908 void intel_pmu_pebs_disable(struct perf_event *event)
909 {
910 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
911 struct hw_perf_event *hwc = &event->hw;
912
913 if (cpuc->n_pebs == cpuc->n_large_pebs)
914 intel_pmu_drain_pebs_buffer();
915
916 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
917
918 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
919 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
920 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
921 cpuc->pebs_enabled &= ~(1ULL << 63);
922
923 if (cpuc->enabled)
924 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
925
926 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
927 }
928
929 void intel_pmu_pebs_enable_all(void)
930 {
931 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
932
933 if (cpuc->pebs_enabled)
934 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
935 }
936
937 void intel_pmu_pebs_disable_all(void)
938 {
939 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
940
941 if (cpuc->pebs_enabled)
942 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
943 }
944
945 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
946 {
947 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
948 unsigned long from = cpuc->lbr_entries[0].from;
949 unsigned long old_to, to = cpuc->lbr_entries[0].to;
950 unsigned long ip = regs->ip;
951 int is_64bit = 0;
952 void *kaddr;
953 int size;
954
955 /*
956 * We don't need to fixup if the PEBS assist is fault like
957 */
958 if (!x86_pmu.intel_cap.pebs_trap)
959 return 1;
960
961 /*
962 * No LBR entry, no basic block, no rewinding
963 */
964 if (!cpuc->lbr_stack.nr || !from || !to)
965 return 0;
966
967 /*
968 * Basic blocks should never cross user/kernel boundaries
969 */
970 if (kernel_ip(ip) != kernel_ip(to))
971 return 0;
972
973 /*
974 * unsigned math, either ip is before the start (impossible) or
975 * the basic block is larger than 1 page (sanity)
976 */
977 if ((ip - to) > PEBS_FIXUP_SIZE)
978 return 0;
979
980 /*
981 * We sampled a branch insn, rewind using the LBR stack
982 */
983 if (ip == to) {
984 set_linear_ip(regs, from);
985 return 1;
986 }
987
988 size = ip - to;
989 if (!kernel_ip(ip)) {
990 int bytes;
991 u8 *buf = this_cpu_read(insn_buffer);
992
993 /* 'size' must fit our buffer, see above */
994 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
995 if (bytes != 0)
996 return 0;
997
998 kaddr = buf;
999 } else {
1000 kaddr = (void *)to;
1001 }
1002
1003 do {
1004 struct insn insn;
1005
1006 old_to = to;
1007
1008 #ifdef CONFIG_X86_64
1009 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1010 #endif
1011 insn_init(&insn, kaddr, size, is_64bit);
1012 insn_get_length(&insn);
1013 /*
1014 * Make sure there was not a problem decoding the
1015 * instruction and getting the length. This is
1016 * doubly important because we have an infinite
1017 * loop if insn.length=0.
1018 */
1019 if (!insn.length)
1020 break;
1021
1022 to += insn.length;
1023 kaddr += insn.length;
1024 size -= insn.length;
1025 } while (to < ip);
1026
1027 if (to == ip) {
1028 set_linear_ip(regs, old_to);
1029 return 1;
1030 }
1031
1032 /*
1033 * Even though we decoded the basic block, the instruction stream
1034 * never matched the given IP, either the TO or the IP got corrupted.
1035 */
1036 return 0;
1037 }
1038
1039 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1040 {
1041 if (pebs->tsx_tuning) {
1042 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
1043 return tsx.cycles_last_block;
1044 }
1045 return 0;
1046 }
1047
1048 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1049 {
1050 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1051
1052 /* For RTM XABORTs also log the abort code from AX */
1053 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1054 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1055 return txn;
1056 }
1057
1058 static void setup_pebs_sample_data(struct perf_event *event,
1059 struct pt_regs *iregs, void *__pebs,
1060 struct perf_sample_data *data,
1061 struct pt_regs *regs)
1062 {
1063 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1064 (PERF_X86_EVENT_PEBS_ST_HSW | \
1065 PERF_X86_EVENT_PEBS_LD_HSW | \
1066 PERF_X86_EVENT_PEBS_NA_HSW)
1067 /*
1068 * We cast to the biggest pebs_record but are careful not to
1069 * unconditionally access the 'extra' entries.
1070 */
1071 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1072 struct pebs_record_skl *pebs = __pebs;
1073 u64 sample_type;
1074 int fll, fst, dsrc;
1075 int fl = event->hw.flags;
1076
1077 if (pebs == NULL)
1078 return;
1079
1080 sample_type = event->attr.sample_type;
1081 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1082
1083 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1084 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1085
1086 perf_sample_data_init(data, 0, event->hw.last_period);
1087
1088 data->period = event->hw.last_period;
1089
1090 /*
1091 * Use latency for weight (only avail with PEBS-LL)
1092 */
1093 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1094 data->weight = pebs->lat;
1095
1096 /*
1097 * data.data_src encodes the data source
1098 */
1099 if (dsrc) {
1100 u64 val = PERF_MEM_NA;
1101 if (fll)
1102 val = load_latency_data(pebs->dse);
1103 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1104 val = precise_datala_hsw(event, pebs->dse);
1105 else if (fst)
1106 val = precise_store_data(pebs->dse);
1107 data->data_src.val = val;
1108 }
1109
1110 /*
1111 * We use the interrupt regs as a base because the PEBS record
1112 * does not contain a full regs set, specifically it seems to
1113 * lack segment descriptors, which get used by things like
1114 * user_mode().
1115 *
1116 * In the simple case fix up only the IP and BP,SP regs, for
1117 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1118 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1119 */
1120 *regs = *iregs;
1121 regs->flags = pebs->flags;
1122 set_linear_ip(regs, pebs->ip);
1123 regs->bp = pebs->bp;
1124 regs->sp = pebs->sp;
1125
1126 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1127 regs->ax = pebs->ax;
1128 regs->bx = pebs->bx;
1129 regs->cx = pebs->cx;
1130 regs->dx = pebs->dx;
1131 regs->si = pebs->si;
1132 regs->di = pebs->di;
1133 regs->bp = pebs->bp;
1134 regs->sp = pebs->sp;
1135
1136 regs->flags = pebs->flags;
1137 #ifndef CONFIG_X86_32
1138 regs->r8 = pebs->r8;
1139 regs->r9 = pebs->r9;
1140 regs->r10 = pebs->r10;
1141 regs->r11 = pebs->r11;
1142 regs->r12 = pebs->r12;
1143 regs->r13 = pebs->r13;
1144 regs->r14 = pebs->r14;
1145 regs->r15 = pebs->r15;
1146 #endif
1147 }
1148
1149 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1150 regs->ip = pebs->real_ip;
1151 regs->flags |= PERF_EFLAGS_EXACT;
1152 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1153 regs->flags |= PERF_EFLAGS_EXACT;
1154 else
1155 regs->flags &= ~PERF_EFLAGS_EXACT;
1156
1157 if ((sample_type & PERF_SAMPLE_ADDR) &&
1158 x86_pmu.intel_cap.pebs_format >= 1)
1159 data->addr = pebs->dla;
1160
1161 if (x86_pmu.intel_cap.pebs_format >= 2) {
1162 /* Only set the TSX weight when no memory weight. */
1163 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1164 data->weight = intel_hsw_weight(pebs);
1165
1166 if (sample_type & PERF_SAMPLE_TRANSACTION)
1167 data->txn = intel_hsw_transaction(pebs);
1168 }
1169
1170 /*
1171 * v3 supplies an accurate time stamp, so we use that
1172 * for the time stamp.
1173 *
1174 * We can only do this for the default trace clock.
1175 */
1176 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1177 event->attr.use_clockid == 0)
1178 data->time = native_sched_clock_from_tsc(pebs->tsc);
1179
1180 if (has_branch_stack(event))
1181 data->br_stack = &cpuc->lbr_stack;
1182 }
1183
1184 static inline void *
1185 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1186 {
1187 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1188 void *at;
1189 u64 pebs_status;
1190
1191 /*
1192 * fmt0 does not have a status bitfield (does not use
1193 * perf_record_nhm format)
1194 */
1195 if (x86_pmu.intel_cap.pebs_format < 1)
1196 return base;
1197
1198 if (base == NULL)
1199 return NULL;
1200
1201 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1202 struct pebs_record_nhm *p = at;
1203
1204 if (test_bit(bit, (unsigned long *)&p->status)) {
1205 /* PEBS v3 has accurate status bits */
1206 if (x86_pmu.intel_cap.pebs_format >= 3)
1207 return at;
1208
1209 if (p->status == (1 << bit))
1210 return at;
1211
1212 /* clear non-PEBS bit and re-check */
1213 pebs_status = p->status & cpuc->pebs_enabled;
1214 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1215 if (pebs_status == (1 << bit))
1216 return at;
1217 }
1218 }
1219 return NULL;
1220 }
1221
1222 static void __intel_pmu_pebs_event(struct perf_event *event,
1223 struct pt_regs *iregs,
1224 void *base, void *top,
1225 int bit, int count)
1226 {
1227 struct perf_sample_data data;
1228 struct pt_regs regs;
1229 void *at = get_next_pebs_record_by_bit(base, top, bit);
1230
1231 if (!intel_pmu_save_and_restart(event) &&
1232 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1233 return;
1234
1235 while (count > 1) {
1236 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1237 perf_event_output(event, &data, &regs);
1238 at += x86_pmu.pebs_record_size;
1239 at = get_next_pebs_record_by_bit(at, top, bit);
1240 count--;
1241 }
1242
1243 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1244
1245 /*
1246 * All but the last records are processed.
1247 * The last one is left to be able to call the overflow handler.
1248 */
1249 if (perf_event_overflow(event, &data, &regs)) {
1250 x86_pmu_stop(event, 0);
1251 return;
1252 }
1253
1254 }
1255
1256 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1257 {
1258 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1259 struct debug_store *ds = cpuc->ds;
1260 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1261 struct pebs_record_core *at, *top;
1262 int n;
1263
1264 if (!x86_pmu.pebs_active)
1265 return;
1266
1267 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1268 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1269
1270 /*
1271 * Whatever else happens, drain the thing
1272 */
1273 ds->pebs_index = ds->pebs_buffer_base;
1274
1275 if (!test_bit(0, cpuc->active_mask))
1276 return;
1277
1278 WARN_ON_ONCE(!event);
1279
1280 if (!event->attr.precise_ip)
1281 return;
1282
1283 n = top - at;
1284 if (n <= 0)
1285 return;
1286
1287 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1288 }
1289
1290 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1291 {
1292 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1293 struct debug_store *ds = cpuc->ds;
1294 struct perf_event *event;
1295 void *base, *at, *top;
1296 short counts[MAX_PEBS_EVENTS] = {};
1297 short error[MAX_PEBS_EVENTS] = {};
1298 int bit, i;
1299
1300 if (!x86_pmu.pebs_active)
1301 return;
1302
1303 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1304 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1305
1306 ds->pebs_index = ds->pebs_buffer_base;
1307
1308 if (unlikely(base >= top))
1309 return;
1310
1311 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1312 struct pebs_record_nhm *p = at;
1313 u64 pebs_status;
1314
1315 pebs_status = p->status & cpuc->pebs_enabled;
1316 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1317
1318 /* PEBS v3 has more accurate status bits */
1319 if (x86_pmu.intel_cap.pebs_format >= 3) {
1320 for_each_set_bit(bit, (unsigned long *)&pebs_status,
1321 x86_pmu.max_pebs_events)
1322 counts[bit]++;
1323
1324 continue;
1325 }
1326
1327 /*
1328 * On some CPUs the PEBS status can be zero when PEBS is
1329 * racing with clearing of GLOBAL_STATUS.
1330 *
1331 * Normally we would drop that record, but in the
1332 * case when there is only a single active PEBS event
1333 * we can assume it's for that event.
1334 */
1335 if (!pebs_status && cpuc->pebs_enabled &&
1336 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1337 pebs_status = cpuc->pebs_enabled;
1338
1339 bit = find_first_bit((unsigned long *)&pebs_status,
1340 x86_pmu.max_pebs_events);
1341 if (bit >= x86_pmu.max_pebs_events)
1342 continue;
1343
1344 /*
1345 * The PEBS hardware does not deal well with the situation
1346 * when events happen near to each other and multiple bits
1347 * are set. But it should happen rarely.
1348 *
1349 * If these events include one PEBS and multiple non-PEBS
1350 * events, it doesn't impact PEBS record. The record will
1351 * be handled normally. (slow path)
1352 *
1353 * If these events include two or more PEBS events, the
1354 * records for the events can be collapsed into a single
1355 * one, and it's not possible to reconstruct all events
1356 * that caused the PEBS record. It's called collision.
1357 * If collision happened, the record will be dropped.
1358 */
1359 if (p->status != (1ULL << bit)) {
1360 for_each_set_bit(i, (unsigned long *)&pebs_status,
1361 x86_pmu.max_pebs_events)
1362 error[i]++;
1363 continue;
1364 }
1365
1366 counts[bit]++;
1367 }
1368
1369 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1370 if ((counts[bit] == 0) && (error[bit] == 0))
1371 continue;
1372
1373 event = cpuc->events[bit];
1374 if (WARN_ON_ONCE(!event))
1375 continue;
1376
1377 if (WARN_ON_ONCE(!event->attr.precise_ip))
1378 continue;
1379
1380 /* log dropped samples number */
1381 if (error[bit])
1382 perf_log_lost_samples(event, error[bit]);
1383
1384 if (counts[bit]) {
1385 __intel_pmu_pebs_event(event, iregs, base,
1386 top, bit, counts[bit]);
1387 }
1388 }
1389 }
1390
1391 /*
1392 * BTS, PEBS probe and setup
1393 */
1394
1395 void __init intel_ds_init(void)
1396 {
1397 /*
1398 * No support for 32bit formats
1399 */
1400 if (!boot_cpu_has(X86_FEATURE_DTES64))
1401 return;
1402
1403 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1404 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1405 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1406 if (x86_pmu.pebs) {
1407 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1408 int format = x86_pmu.intel_cap.pebs_format;
1409
1410 switch (format) {
1411 case 0:
1412 pr_cont("PEBS fmt0%c, ", pebs_type);
1413 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1414 /*
1415 * Using >PAGE_SIZE buffers makes the WRMSR to
1416 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1417 * mysteriously hang on Core2.
1418 *
1419 * As a workaround, we don't do this.
1420 */
1421 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1422 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1423 break;
1424
1425 case 1:
1426 pr_cont("PEBS fmt1%c, ", pebs_type);
1427 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1428 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1429 break;
1430
1431 case 2:
1432 pr_cont("PEBS fmt2%c, ", pebs_type);
1433 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1434 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1435 break;
1436
1437 case 3:
1438 pr_cont("PEBS fmt3%c, ", pebs_type);
1439 x86_pmu.pebs_record_size =
1440 sizeof(struct pebs_record_skl);
1441 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1442 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1443 break;
1444
1445 default:
1446 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1447 x86_pmu.pebs = 0;
1448 }
1449 }
1450 }
1451
1452 void perf_restore_debug_store(void)
1453 {
1454 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1455
1456 if (!x86_pmu.bts && !x86_pmu.pebs)
1457 return;
1458
1459 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1460 }
Linux with added FPC-III support