2 # Intel pin control drivers
5 config PINCTRL_BAYTRAIL
6 bool "Intel Baytrail GPIO pin control"
7 depends on GPIOLIB && ACPI
11 select GENERIC_PINCONF
13 driver for memory mapped GPIO functionality on Intel Baytrail
14 platforms. Supports 3 banks with 102, 28 and 44 gpios.
15 Most pins are usually muxed to some other functionality by firmware,
16 so only a small amount is available for gpio use.
18 Requires ACPI device enumeration code to set up a platform device.
20 config PINCTRL_CHERRYVIEW
21 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
25 select GENERIC_PINCONF
27 select GPIOLIB_IRQCHIP
29 Cherryview/Braswell pinctrl driver provides an interface that
30 allows configuring of SoC pins and using them as GPIOs.
32 config PINCTRL_MERRIFIELD
33 tristate "Intel Merrifield pinctrl driver"
34 depends on X86_INTEL_MID
37 select GENERIC_PINCONF
39 Merrifield Family-Level Interface Shim (FLIS) driver provides an
40 interface that allows configuring of SoC pins and using them as
47 select GENERIC_PINCONF
49 select GPIOLIB_IRQCHIP
51 config PINCTRL_BROXTON
52 tristate "Intel Broxton pinctrl and GPIO driver"
56 Broxton pinctrl driver provides an interface that allows
57 configuring of SoC pins and using them as GPIOs.
59 config PINCTRL_SUNRISEPOINT
60 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
64 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
65 provides an interface that allows configuring of PCH pins and