drivers/pinctrl/tegra/pinctrl-tegra114.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra114 pinmux
   3  *
   4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21
  22 #include "pinctrl-tegra.h"
  23
  24 /*
  25  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26  * These must match how the GPIO driver names/numbers its pins.
  27  */
  28 #define _GPIO(offset)                           (offset)
  29
  30 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  31 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  32 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  33 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  34 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  35 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  36 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  37 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  38 #define TEGRA_PIN_GMI_A17_PB0                   _GPIO(8)
  39 #define TEGRA_PIN_GMI_A18_PB1                   _GPIO(9)
  40 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  41 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  42 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  43 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  44 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  45 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  46 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  47 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  48 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  49 #define TEGRA_PIN_GMI_WP_N_PC7                  _GPIO(23)
  50 #define TEGRA_PIN_GMI_AD0_PG0                   _GPIO(48)
  51 #define TEGRA_PIN_GMI_AD1_PG1                   _GPIO(49)
  52 #define TEGRA_PIN_GMI_AD2_PG2                   _GPIO(50)
  53 #define TEGRA_PIN_GMI_AD3_PG3                   _GPIO(51)
  54 #define TEGRA_PIN_GMI_AD4_PG4                   _GPIO(52)
  55 #define TEGRA_PIN_GMI_AD5_PG5                   _GPIO(53)
  56 #define TEGRA_PIN_GMI_AD6_PG6                   _GPIO(54)
  57 #define TEGRA_PIN_GMI_AD7_PG7                   _GPIO(55)
  58 #define TEGRA_PIN_GMI_AD8_PH0                   _GPIO(56)
  59 #define TEGRA_PIN_GMI_AD9_PH1                   _GPIO(57)
  60 #define TEGRA_PIN_GMI_AD10_PH2                  _GPIO(58)
  61 #define TEGRA_PIN_GMI_AD11_PH3                  _GPIO(59)
  62 #define TEGRA_PIN_GMI_AD12_PH4                  _GPIO(60)
  63 #define TEGRA_PIN_GMI_AD13_PH5                  _GPIO(61)
  64 #define TEGRA_PIN_GMI_AD14_PH6                  _GPIO(62)
  65 #define TEGRA_PIN_GMI_AD15_PH7                  _GPIO(63)
  66 #define TEGRA_PIN_GMI_WR_N_PI0                  _GPIO(64)
  67 #define TEGRA_PIN_GMI_OE_N_PI1                  _GPIO(65)
  68 #define TEGRA_PIN_GMI_CS6_N_PI3                 _GPIO(67)
  69 #define TEGRA_PIN_GMI_RST_N_PI4                 _GPIO(68)
  70 #define TEGRA_PIN_GMI_IORDY_PI5                 _GPIO(69)
  71 #define TEGRA_PIN_GMI_CS7_N_PI6                 _GPIO(70)
  72 #define TEGRA_PIN_GMI_WAIT_PI7                  _GPIO(71)
  73 #define TEGRA_PIN_GMI_CS0_N_PJ0                 _GPIO(72)
  74 #define TEGRA_PIN_GMI_CS1_N_PJ2                 _GPIO(74)
  75 #define TEGRA_PIN_GMI_DQS_P_PJ3                 _GPIO(75)
  76 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  77 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  78 #define TEGRA_PIN_GMI_A16_PJ7                   _GPIO(79)
  79 #define TEGRA_PIN_GMI_ADV_N_PK0                 _GPIO(80)
  80 #define TEGRA_PIN_GMI_CLK_PK1                   _GPIO(81)
  81 #define TEGRA_PIN_GMI_CS4_N_PK2                 _GPIO(82)
  82 #define TEGRA_PIN_GMI_CS2_N_PK3                 _GPIO(83)
  83 #define TEGRA_PIN_GMI_CS3_N_PK4                 _GPIO(84)
  84 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  85 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  86 #define TEGRA_PIN_GMI_A19_PK7                   _GPIO(87)
  87 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  88 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  89 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  90 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  91 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  92 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  93 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  94 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  95 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  96 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  97 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
  98 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
  99 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
 100 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
 101 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
 102 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
 103 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
 104 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
 105 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 106 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 107 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 108 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 109 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 110 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 111 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 112 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 113 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 114 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 115 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 116 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 117 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 118 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 119 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 120 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 121 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 122 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 123 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 124 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 125 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 126 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 127 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 128 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 129 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 130 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 131 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 132 #define TEGRA_PIN_PU0                           _GPIO(160)
 133 #define TEGRA_PIN_PU1                           _GPIO(161)
 134 #define TEGRA_PIN_PU2                           _GPIO(162)
 135 #define TEGRA_PIN_PU3                           _GPIO(163)
 136 #define TEGRA_PIN_PU4                           _GPIO(164)
 137 #define TEGRA_PIN_PU5                           _GPIO(165)
 138 #define TEGRA_PIN_PU6                           _GPIO(166)
 139 #define TEGRA_PIN_PV0                           _GPIO(168)
 140 #define TEGRA_PIN_PV1                           _GPIO(169)
 141 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 142 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 143 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 144 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 145 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 146 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 147 #define TEGRA_PIN_CLK1_OUT_PW4                  _GPIO(180)
 148 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 149 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 150 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 151 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 152 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 153 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 154 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 155 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 156 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 157 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 158 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 159 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 160 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 161 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 162 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 163 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 164 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 165 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 166 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 167 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 168 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 169 #define TEGRA_PIN_SYS_CLK_REQ_PZ5               _GPIO(205)
 170 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 171 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 172 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 173 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 174 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 175 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 176 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 177 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 178 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 179 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 180 #define TEGRA_PIN_PBB0                          _GPIO(216)
 181 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 182 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 183 #define TEGRA_PIN_PBB3                          _GPIO(219)
 184 #define TEGRA_PIN_PBB4                          _GPIO(220)
 185 #define TEGRA_PIN_PBB5                          _GPIO(221)
 186 #define TEGRA_PIN_PBB6                          _GPIO(222)
 187 #define TEGRA_PIN_PBB7                          _GPIO(223)
 188 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 189 #define TEGRA_PIN_PCC1                          _GPIO(225)
 190 #define TEGRA_PIN_PCC2                          _GPIO(226)
 191 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 192 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 193 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 194 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 195 #define TEGRA_PIN_CLK1_REQ_PEE2                 _GPIO(242)
 196 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 197 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 198 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 199
 200 /* All non-GPIO pins follow */
 201 #define NUM_GPIOS                               (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
 202 #define _PIN(offset)                            (NUM_GPIOS + (offset))
 203
 204 /* Non-GPIO pins */
 205 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 206 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 207 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 208 #define TEGRA_PIN_RESET_OUT_N                   _PIN(3)
 209 #define TEGRA_PIN_OWR                           _PIN(4)
 210 #define TEGRA_PIN_JTAG_RTCK                     _PIN(5)
 211 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
 212 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(7)
 213
 214 static const struct pinctrl_pin_desc tegra114_pins[] = {
 215         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 216         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 217         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 218         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 219         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 220         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 221         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 222         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 223         PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
 224         PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
 225         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 226         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 227         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 228         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 229         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 230         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 231         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 232         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 233         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 234         PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 235         PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
 236         PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
 237         PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
 238         PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
 239         PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
 240         PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
 241         PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
 242         PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
 243         PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
 244         PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
 245         PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
 246         PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
 247         PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
 248         PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
 249         PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
 250         PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
 251         PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
 252         PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
 253         PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
 254         PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
 255         PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
 256         PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
 257         PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
 258         PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
 259         PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
 260         PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
 261         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 262         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 263         PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
 264         PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
 265         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
 266         PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
 267         PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
 268         PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
 269         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 270         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 271         PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
 272         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 273         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 274         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 275         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 276         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 277         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 278         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 279         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 280         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 281         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 282         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 283         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 284         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 285         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 286         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 287         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 288         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 289         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 290         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 291         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 292         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 293         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 294         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 295         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 296         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 297         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 298         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 299         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 300         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 301         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 302         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 303         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 304         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 305         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 306         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 307         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 308         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 309         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 310         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 311         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 312         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 313         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 314         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 315         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 316         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 317         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 318         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 319         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 320         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 321         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 322         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 323         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 324         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 325         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 326         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 327         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 328         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 329         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 330         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 331         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 332         PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
 333         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 334         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 335         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 336         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 337         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 338         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 339         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 340         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 341         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 342         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 343         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 344         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 345         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 346         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 347         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 348         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 349         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 350         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 351         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 352         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 353         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 354         PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
 355         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 356         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 357         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 358         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 359         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 360         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 361         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 362         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 363         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 364         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 365         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 366         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 367         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 368         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 369         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 370         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 371         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 372         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 373         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 374         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 375         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 376         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 377         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 378         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 379         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 380         PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
 381         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 382         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 383         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 384         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 385         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 386         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 387         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 388         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 389         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
 390         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 391         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
 392 };
 393
 394 static const unsigned clk_32k_out_pa0_pins[] = {
 395         TEGRA_PIN_CLK_32K_OUT_PA0,
 396 };
 397
 398 static const unsigned uart3_cts_n_pa1_pins[] = {
 399         TEGRA_PIN_UART3_CTS_N_PA1,
 400 };
 401
 402 static const unsigned dap2_fs_pa2_pins[] = {
 403         TEGRA_PIN_DAP2_FS_PA2,
 404 };
 405
 406 static const unsigned dap2_sclk_pa3_pins[] = {
 407         TEGRA_PIN_DAP2_SCLK_PA3,
 408 };
 409
 410 static const unsigned dap2_din_pa4_pins[] = {
 411         TEGRA_PIN_DAP2_DIN_PA4,
 412 };
 413
 414 static const unsigned dap2_dout_pa5_pins[] = {
 415         TEGRA_PIN_DAP2_DOUT_PA5,
 416 };
 417
 418 static const unsigned sdmmc3_clk_pa6_pins[] = {
 419         TEGRA_PIN_SDMMC3_CLK_PA6,
 420 };
 421
 422 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 423         TEGRA_PIN_SDMMC3_CMD_PA7,
 424 };
 425
 426 static const unsigned gmi_a17_pb0_pins[] = {
 427         TEGRA_PIN_GMI_A17_PB0,
 428 };
 429
 430 static const unsigned gmi_a18_pb1_pins[] = {
 431         TEGRA_PIN_GMI_A18_PB1,
 432 };
 433
 434 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 435         TEGRA_PIN_SDMMC3_DAT3_PB4,
 436 };
 437
 438 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 439         TEGRA_PIN_SDMMC3_DAT2_PB5,
 440 };
 441
 442 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 443         TEGRA_PIN_SDMMC3_DAT1_PB6,
 444 };
 445
 446 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 447         TEGRA_PIN_SDMMC3_DAT0_PB7,
 448 };
 449
 450 static const unsigned uart3_rts_n_pc0_pins[] = {
 451         TEGRA_PIN_UART3_RTS_N_PC0,
 452 };
 453
 454 static const unsigned uart2_txd_pc2_pins[] = {
 455         TEGRA_PIN_UART2_TXD_PC2,
 456 };
 457
 458 static const unsigned uart2_rxd_pc3_pins[] = {
 459         TEGRA_PIN_UART2_RXD_PC3,
 460 };
 461
 462 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 463         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 464 };
 465
 466 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 467         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 468 };
 469
 470 static const unsigned gmi_wp_n_pc7_pins[] = {
 471         TEGRA_PIN_GMI_WP_N_PC7,
 472 };
 473
 474 static const unsigned gmi_ad0_pg0_pins[] = {
 475         TEGRA_PIN_GMI_AD0_PG0,
 476 };
 477
 478 static const unsigned gmi_ad1_pg1_pins[] = {
 479         TEGRA_PIN_GMI_AD1_PG1,
 480 };
 481
 482 static const unsigned gmi_ad2_pg2_pins[] = {
 483         TEGRA_PIN_GMI_AD2_PG2,
 484 };
 485
 486 static const unsigned gmi_ad3_pg3_pins[] = {
 487         TEGRA_PIN_GMI_AD3_PG3,
 488 };
 489
 490 static const unsigned gmi_ad4_pg4_pins[] = {
 491         TEGRA_PIN_GMI_AD4_PG4,
 492 };
 493
 494 static const unsigned gmi_ad5_pg5_pins[] = {
 495         TEGRA_PIN_GMI_AD5_PG5,
 496 };
 497
 498 static const unsigned gmi_ad6_pg6_pins[] = {
 499         TEGRA_PIN_GMI_AD6_PG6,
 500 };
 501
 502 static const unsigned gmi_ad7_pg7_pins[] = {
 503         TEGRA_PIN_GMI_AD7_PG7,
 504 };
 505
 506 static const unsigned gmi_ad8_ph0_pins[] = {
 507         TEGRA_PIN_GMI_AD8_PH0,
 508 };
 509
 510 static const unsigned gmi_ad9_ph1_pins[] = {
 511         TEGRA_PIN_GMI_AD9_PH1,
 512 };
 513
 514 static const unsigned gmi_ad10_ph2_pins[] = {
 515         TEGRA_PIN_GMI_AD10_PH2,
 516 };
 517
 518 static const unsigned gmi_ad11_ph3_pins[] = {
 519         TEGRA_PIN_GMI_AD11_PH3,
 520 };
 521
 522 static const unsigned gmi_ad12_ph4_pins[] = {
 523         TEGRA_PIN_GMI_AD12_PH4,
 524 };
 525
 526 static const unsigned gmi_ad13_ph5_pins[] = {
 527         TEGRA_PIN_GMI_AD13_PH5,
 528 };
 529
 530 static const unsigned gmi_ad14_ph6_pins[] = {
 531         TEGRA_PIN_GMI_AD14_PH6,
 532 };
 533
 534 static const unsigned gmi_ad15_ph7_pins[] = {
 535         TEGRA_PIN_GMI_AD15_PH7,
 536 };
 537
 538 static const unsigned gmi_wr_n_pi0_pins[] = {
 539         TEGRA_PIN_GMI_WR_N_PI0,
 540 };
 541
 542 static const unsigned gmi_oe_n_pi1_pins[] = {
 543         TEGRA_PIN_GMI_OE_N_PI1,
 544 };
 545
 546 static const unsigned gmi_cs6_n_pi3_pins[] = {
 547         TEGRA_PIN_GMI_CS6_N_PI3,
 548 };
 549
 550 static const unsigned gmi_rst_n_pi4_pins[] = {
 551         TEGRA_PIN_GMI_RST_N_PI4,
 552 };
 553
 554 static const unsigned gmi_iordy_pi5_pins[] = {
 555         TEGRA_PIN_GMI_IORDY_PI5,
 556 };
 557
 558 static const unsigned gmi_cs7_n_pi6_pins[] = {
 559         TEGRA_PIN_GMI_CS7_N_PI6,
 560 };
 561
 562 static const unsigned gmi_wait_pi7_pins[] = {
 563         TEGRA_PIN_GMI_WAIT_PI7,
 564 };
 565
 566 static const unsigned gmi_cs0_n_pj0_pins[] = {
 567         TEGRA_PIN_GMI_CS0_N_PJ0,
 568 };
 569
 570 static const unsigned gmi_cs1_n_pj2_pins[] = {
 571         TEGRA_PIN_GMI_CS1_N_PJ2,
 572 };
 573
 574 static const unsigned gmi_dqs_p_pj3_pins[] = {
 575         TEGRA_PIN_GMI_DQS_P_PJ3,
 576 };
 577
 578 static const unsigned uart2_cts_n_pj5_pins[] = {
 579         TEGRA_PIN_UART2_CTS_N_PJ5,
 580 };
 581
 582 static const unsigned uart2_rts_n_pj6_pins[] = {
 583         TEGRA_PIN_UART2_RTS_N_PJ6,
 584 };
 585
 586 static const unsigned gmi_a16_pj7_pins[] = {
 587         TEGRA_PIN_GMI_A16_PJ7,
 588 };
 589
 590 static const unsigned gmi_adv_n_pk0_pins[] = {
 591         TEGRA_PIN_GMI_ADV_N_PK0,
 592 };
 593
 594 static const unsigned gmi_clk_pk1_pins[] = {
 595         TEGRA_PIN_GMI_CLK_PK1,
 596 };
 597
 598 static const unsigned gmi_cs4_n_pk2_pins[] = {
 599         TEGRA_PIN_GMI_CS4_N_PK2,
 600 };
 601
 602 static const unsigned gmi_cs2_n_pk3_pins[] = {
 603         TEGRA_PIN_GMI_CS2_N_PK3,
 604 };
 605
 606 static const unsigned gmi_cs3_n_pk4_pins[] = {
 607         TEGRA_PIN_GMI_CS3_N_PK4,
 608 };
 609
 610 static const unsigned spdif_out_pk5_pins[] = {
 611         TEGRA_PIN_SPDIF_OUT_PK5,
 612 };
 613
 614 static const unsigned spdif_in_pk6_pins[] = {
 615         TEGRA_PIN_SPDIF_IN_PK6,
 616 };
 617
 618 static const unsigned gmi_a19_pk7_pins[] = {
 619         TEGRA_PIN_GMI_A19_PK7,
 620 };
 621
 622 static const unsigned dap1_fs_pn0_pins[] = {
 623         TEGRA_PIN_DAP1_FS_PN0,
 624 };
 625
 626 static const unsigned dap1_din_pn1_pins[] = {
 627         TEGRA_PIN_DAP1_DIN_PN1,
 628 };
 629
 630 static const unsigned dap1_dout_pn2_pins[] = {
 631         TEGRA_PIN_DAP1_DOUT_PN2,
 632 };
 633
 634 static const unsigned dap1_sclk_pn3_pins[] = {
 635         TEGRA_PIN_DAP1_SCLK_PN3,
 636 };
 637
 638 static const unsigned usb_vbus_en0_pn4_pins[] = {
 639         TEGRA_PIN_USB_VBUS_EN0_PN4,
 640 };
 641
 642 static const unsigned usb_vbus_en1_pn5_pins[] = {
 643         TEGRA_PIN_USB_VBUS_EN1_PN5,
 644 };
 645
 646 static const unsigned hdmi_int_pn7_pins[] = {
 647         TEGRA_PIN_HDMI_INT_PN7,
 648 };
 649
 650 static const unsigned ulpi_data7_po0_pins[] = {
 651         TEGRA_PIN_ULPI_DATA7_PO0,
 652 };
 653
 654 static const unsigned ulpi_data0_po1_pins[] = {
 655         TEGRA_PIN_ULPI_DATA0_PO1,
 656 };
 657
 658 static const unsigned ulpi_data1_po2_pins[] = {
 659         TEGRA_PIN_ULPI_DATA1_PO2,
 660 };
 661
 662 static const unsigned ulpi_data2_po3_pins[] = {
 663         TEGRA_PIN_ULPI_DATA2_PO3,
 664 };
 665
 666 static const unsigned ulpi_data3_po4_pins[] = {
 667         TEGRA_PIN_ULPI_DATA3_PO4,
 668 };
 669
 670 static const unsigned ulpi_data4_po5_pins[] = {
 671         TEGRA_PIN_ULPI_DATA4_PO5,
 672 };
 673
 674 static const unsigned ulpi_data5_po6_pins[] = {
 675         TEGRA_PIN_ULPI_DATA5_PO6,
 676 };
 677
 678 static const unsigned ulpi_data6_po7_pins[] = {
 679         TEGRA_PIN_ULPI_DATA6_PO7,
 680 };
 681
 682 static const unsigned dap3_fs_pp0_pins[] = {
 683         TEGRA_PIN_DAP3_FS_PP0,
 684 };
 685
 686 static const unsigned dap3_din_pp1_pins[] = {
 687         TEGRA_PIN_DAP3_DIN_PP1,
 688 };
 689
 690 static const unsigned dap3_dout_pp2_pins[] = {
 691         TEGRA_PIN_DAP3_DOUT_PP2,
 692 };
 693
 694 static const unsigned dap3_sclk_pp3_pins[] = {
 695         TEGRA_PIN_DAP3_SCLK_PP3,
 696 };
 697
 698 static const unsigned dap4_fs_pp4_pins[] = {
 699         TEGRA_PIN_DAP4_FS_PP4,
 700 };
 701
 702 static const unsigned dap4_din_pp5_pins[] = {
 703         TEGRA_PIN_DAP4_DIN_PP5,
 704 };
 705
 706 static const unsigned dap4_dout_pp6_pins[] = {
 707         TEGRA_PIN_DAP4_DOUT_PP6,
 708 };
 709
 710 static const unsigned dap4_sclk_pp7_pins[] = {
 711         TEGRA_PIN_DAP4_SCLK_PP7,
 712 };
 713
 714 static const unsigned kb_col0_pq0_pins[] = {
 715         TEGRA_PIN_KB_COL0_PQ0,
 716 };
 717
 718 static const unsigned kb_col1_pq1_pins[] = {
 719         TEGRA_PIN_KB_COL1_PQ1,
 720 };
 721
 722 static const unsigned kb_col2_pq2_pins[] = {
 723         TEGRA_PIN_KB_COL2_PQ2,
 724 };
 725
 726 static const unsigned kb_col3_pq3_pins[] = {
 727         TEGRA_PIN_KB_COL3_PQ3,
 728 };
 729
 730 static const unsigned kb_col4_pq4_pins[] = {
 731         TEGRA_PIN_KB_COL4_PQ4,
 732 };
 733
 734 static const unsigned kb_col5_pq5_pins[] = {
 735         TEGRA_PIN_KB_COL5_PQ5,
 736 };
 737
 738 static const unsigned kb_col6_pq6_pins[] = {
 739         TEGRA_PIN_KB_COL6_PQ6,
 740 };
 741
 742 static const unsigned kb_col7_pq7_pins[] = {
 743         TEGRA_PIN_KB_COL7_PQ7,
 744 };
 745
 746 static const unsigned kb_row0_pr0_pins[] = {
 747         TEGRA_PIN_KB_ROW0_PR0,
 748 };
 749
 750 static const unsigned kb_row1_pr1_pins[] = {
 751         TEGRA_PIN_KB_ROW1_PR1,
 752 };
 753
 754 static const unsigned kb_row2_pr2_pins[] = {
 755         TEGRA_PIN_KB_ROW2_PR2,
 756 };
 757
 758 static const unsigned kb_row3_pr3_pins[] = {
 759         TEGRA_PIN_KB_ROW3_PR3,
 760 };
 761
 762 static const unsigned kb_row4_pr4_pins[] = {
 763         TEGRA_PIN_KB_ROW4_PR4,
 764 };
 765
 766 static const unsigned kb_row5_pr5_pins[] = {
 767         TEGRA_PIN_KB_ROW5_PR5,
 768 };
 769
 770 static const unsigned kb_row6_pr6_pins[] = {
 771         TEGRA_PIN_KB_ROW6_PR6,
 772 };
 773
 774 static const unsigned kb_row7_pr7_pins[] = {
 775         TEGRA_PIN_KB_ROW7_PR7,
 776 };
 777
 778 static const unsigned kb_row8_ps0_pins[] = {
 779         TEGRA_PIN_KB_ROW8_PS0,
 780 };
 781
 782 static const unsigned kb_row9_ps1_pins[] = {
 783         TEGRA_PIN_KB_ROW9_PS1,
 784 };
 785
 786 static const unsigned kb_row10_ps2_pins[] = {
 787         TEGRA_PIN_KB_ROW10_PS2,
 788 };
 789
 790 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 791         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 792 };
 793
 794 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 795         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 796 };
 797
 798 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 799         TEGRA_PIN_SDMMC4_CMD_PT7,
 800 };
 801
 802 static const unsigned pu0_pins[] = {
 803         TEGRA_PIN_PU0,
 804 };
 805
 806 static const unsigned pu1_pins[] = {
 807         TEGRA_PIN_PU1,
 808 };
 809
 810 static const unsigned pu2_pins[] = {
 811         TEGRA_PIN_PU2,
 812 };
 813
 814 static const unsigned pu3_pins[] = {
 815         TEGRA_PIN_PU3,
 816 };
 817
 818 static const unsigned pu4_pins[] = {
 819         TEGRA_PIN_PU4,
 820 };
 821
 822 static const unsigned pu5_pins[] = {
 823         TEGRA_PIN_PU5,
 824 };
 825
 826 static const unsigned pu6_pins[] = {
 827         TEGRA_PIN_PU6,
 828 };
 829
 830 static const unsigned pv0_pins[] = {
 831         TEGRA_PIN_PV0,
 832 };
 833
 834 static const unsigned pv1_pins[] = {
 835         TEGRA_PIN_PV1,
 836 };
 837
 838 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 839         TEGRA_PIN_SDMMC3_CD_N_PV2,
 840 };
 841
 842 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 843         TEGRA_PIN_SDMMC1_WP_N_PV3,
 844 };
 845
 846 static const unsigned ddc_scl_pv4_pins[] = {
 847         TEGRA_PIN_DDC_SCL_PV4,
 848 };
 849
 850 static const unsigned ddc_sda_pv5_pins[] = {
 851         TEGRA_PIN_DDC_SDA_PV5,
 852 };
 853
 854 static const unsigned gpio_w2_aud_pw2_pins[] = {
 855         TEGRA_PIN_GPIO_W2_AUD_PW2,
 856 };
 857
 858 static const unsigned gpio_w3_aud_pw3_pins[] = {
 859         TEGRA_PIN_GPIO_W3_AUD_PW3,
 860 };
 861
 862 static const unsigned clk1_out_pw4_pins[] = {
 863         TEGRA_PIN_CLK1_OUT_PW4,
 864 };
 865
 866 static const unsigned clk2_out_pw5_pins[] = {
 867         TEGRA_PIN_CLK2_OUT_PW5,
 868 };
 869
 870 static const unsigned uart3_txd_pw6_pins[] = {
 871         TEGRA_PIN_UART3_TXD_PW6,
 872 };
 873
 874 static const unsigned uart3_rxd_pw7_pins[] = {
 875         TEGRA_PIN_UART3_RXD_PW7,
 876 };
 877
 878 static const unsigned dvfs_pwm_px0_pins[] = {
 879         TEGRA_PIN_DVFS_PWM_PX0,
 880 };
 881
 882 static const unsigned gpio_x1_aud_px1_pins[] = {
 883         TEGRA_PIN_GPIO_X1_AUD_PX1,
 884 };
 885
 886 static const unsigned dvfs_clk_px2_pins[] = {
 887         TEGRA_PIN_DVFS_CLK_PX2,
 888 };
 889
 890 static const unsigned gpio_x3_aud_px3_pins[] = {
 891         TEGRA_PIN_GPIO_X3_AUD_PX3,
 892 };
 893
 894 static const unsigned gpio_x4_aud_px4_pins[] = {
 895         TEGRA_PIN_GPIO_X4_AUD_PX4,
 896 };
 897
 898 static const unsigned gpio_x5_aud_px5_pins[] = {
 899         TEGRA_PIN_GPIO_X5_AUD_PX5,
 900 };
 901
 902 static const unsigned gpio_x6_aud_px6_pins[] = {
 903         TEGRA_PIN_GPIO_X6_AUD_PX6,
 904 };
 905
 906 static const unsigned gpio_x7_aud_px7_pins[] = {
 907         TEGRA_PIN_GPIO_X7_AUD_PX7,
 908 };
 909
 910 static const unsigned ulpi_clk_py0_pins[] = {
 911         TEGRA_PIN_ULPI_CLK_PY0,
 912 };
 913
 914 static const unsigned ulpi_dir_py1_pins[] = {
 915         TEGRA_PIN_ULPI_DIR_PY1,
 916 };
 917
 918 static const unsigned ulpi_nxt_py2_pins[] = {
 919         TEGRA_PIN_ULPI_NXT_PY2,
 920 };
 921
 922 static const unsigned ulpi_stp_py3_pins[] = {
 923         TEGRA_PIN_ULPI_STP_PY3,
 924 };
 925
 926 static const unsigned sdmmc1_dat3_py4_pins[] = {
 927         TEGRA_PIN_SDMMC1_DAT3_PY4,
 928 };
 929
 930 static const unsigned sdmmc1_dat2_py5_pins[] = {
 931         TEGRA_PIN_SDMMC1_DAT2_PY5,
 932 };
 933
 934 static const unsigned sdmmc1_dat1_py6_pins[] = {
 935         TEGRA_PIN_SDMMC1_DAT1_PY6,
 936 };
 937
 938 static const unsigned sdmmc1_dat0_py7_pins[] = {
 939         TEGRA_PIN_SDMMC1_DAT0_PY7,
 940 };
 941
 942 static const unsigned sdmmc1_clk_pz0_pins[] = {
 943         TEGRA_PIN_SDMMC1_CLK_PZ0,
 944 };
 945
 946 static const unsigned sdmmc1_cmd_pz1_pins[] = {
 947         TEGRA_PIN_SDMMC1_CMD_PZ1,
 948 };
 949
 950 static const unsigned sys_clk_req_pz5_pins[] = {
 951         TEGRA_PIN_SYS_CLK_REQ_PZ5,
 952 };
 953
 954 static const unsigned pwr_i2c_scl_pz6_pins[] = {
 955         TEGRA_PIN_PWR_I2C_SCL_PZ6,
 956 };
 957
 958 static const unsigned pwr_i2c_sda_pz7_pins[] = {
 959         TEGRA_PIN_PWR_I2C_SDA_PZ7,
 960 };
 961
 962 static const unsigned sdmmc4_dat0_paa0_pins[] = {
 963         TEGRA_PIN_SDMMC4_DAT0_PAA0,
 964 };
 965
 966 static const unsigned sdmmc4_dat1_paa1_pins[] = {
 967         TEGRA_PIN_SDMMC4_DAT1_PAA1,
 968 };
 969
 970 static const unsigned sdmmc4_dat2_paa2_pins[] = {
 971         TEGRA_PIN_SDMMC4_DAT2_PAA2,
 972 };
 973
 974 static const unsigned sdmmc4_dat3_paa3_pins[] = {
 975         TEGRA_PIN_SDMMC4_DAT3_PAA3,
 976 };
 977
 978 static const unsigned sdmmc4_dat4_paa4_pins[] = {
 979         TEGRA_PIN_SDMMC4_DAT4_PAA4,
 980 };
 981
 982 static const unsigned sdmmc4_dat5_paa5_pins[] = {
 983         TEGRA_PIN_SDMMC4_DAT5_PAA5,
 984 };
 985
 986 static const unsigned sdmmc4_dat6_paa6_pins[] = {
 987         TEGRA_PIN_SDMMC4_DAT6_PAA6,
 988 };
 989
 990 static const unsigned sdmmc4_dat7_paa7_pins[] = {
 991         TEGRA_PIN_SDMMC4_DAT7_PAA7,
 992 };
 993
 994 static const unsigned pbb0_pins[] = {
 995         TEGRA_PIN_PBB0,
 996 };
 997
 998 static const unsigned cam_i2c_scl_pbb1_pins[] = {
 999         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1000 };
1001
1002 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1003         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1004 };
1005
1006 static const unsigned pbb3_pins[] = {
1007         TEGRA_PIN_PBB3,
1008 };
1009
1010 static const unsigned pbb4_pins[] = {
1011         TEGRA_PIN_PBB4,
1012 };
1013
1014 static const unsigned pbb5_pins[] = {
1015         TEGRA_PIN_PBB5,
1016 };
1017
1018 static const unsigned pbb6_pins[] = {
1019         TEGRA_PIN_PBB6,
1020 };
1021
1022 static const unsigned pbb7_pins[] = {
1023         TEGRA_PIN_PBB7,
1024 };
1025
1026 static const unsigned cam_mclk_pcc0_pins[] = {
1027         TEGRA_PIN_CAM_MCLK_PCC0,
1028 };
1029
1030 static const unsigned pcc1_pins[] = {
1031         TEGRA_PIN_PCC1,
1032 };
1033
1034 static const unsigned pcc2_pins[] = {
1035         TEGRA_PIN_PCC2,
1036 };
1037
1038 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1039         TEGRA_PIN_SDMMC4_CLK_PCC4,
1040 };
1041
1042 static const unsigned clk2_req_pcc5_pins[] = {
1043         TEGRA_PIN_CLK2_REQ_PCC5,
1044 };
1045
1046 static const unsigned clk3_out_pee0_pins[] = {
1047         TEGRA_PIN_CLK3_OUT_PEE0,
1048 };
1049
1050 static const unsigned clk3_req_pee1_pins[] = {
1051         TEGRA_PIN_CLK3_REQ_PEE1,
1052 };
1053
1054 static const unsigned clk1_req_pee2_pins[] = {
1055         TEGRA_PIN_CLK1_REQ_PEE2,
1056 };
1057
1058 static const unsigned hdmi_cec_pee3_pins[] = {
1059         TEGRA_PIN_HDMI_CEC_PEE3,
1060 };
1061
1062 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1063         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1064 };
1065
1066 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1067         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1068 };
1069
1070 static const unsigned core_pwr_req_pins[] = {
1071         TEGRA_PIN_CORE_PWR_REQ,
1072 };
1073
1074 static const unsigned cpu_pwr_req_pins[] = {
1075         TEGRA_PIN_CPU_PWR_REQ,
1076 };
1077
1078 static const unsigned pwr_int_n_pins[] = {
1079         TEGRA_PIN_PWR_INT_N,
1080 };
1081
1082 static const unsigned reset_out_n_pins[] = {
1083         TEGRA_PIN_RESET_OUT_N,
1084 };
1085
1086 static const unsigned owr_pins[] = {
1087         TEGRA_PIN_OWR,
1088 };
1089
1090 static const unsigned jtag_rtck_pins[] = {
1091         TEGRA_PIN_JTAG_RTCK,
1092 };
1093
1094 static const unsigned clk_32k_in_pins[] = {
1095         TEGRA_PIN_CLK_32K_IN,
1096 };
1097
1098 static const unsigned gmi_clk_lb_pins[] = {
1099         TEGRA_PIN_GMI_CLK_LB,
1100 };
1101
1102 static const unsigned drive_ao1_pins[] = {
1103         TEGRA_PIN_KB_ROW0_PR0,
1104         TEGRA_PIN_KB_ROW1_PR1,
1105         TEGRA_PIN_KB_ROW2_PR2,
1106         TEGRA_PIN_KB_ROW3_PR3,
1107         TEGRA_PIN_KB_ROW4_PR4,
1108         TEGRA_PIN_KB_ROW5_PR5,
1109         TEGRA_PIN_KB_ROW6_PR6,
1110         TEGRA_PIN_KB_ROW7_PR7,
1111         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1112         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1113 };
1114
1115 static const unsigned drive_ao2_pins[] = {
1116         TEGRA_PIN_CLK_32K_OUT_PA0,
1117         TEGRA_PIN_KB_COL0_PQ0,
1118         TEGRA_PIN_KB_COL1_PQ1,
1119         TEGRA_PIN_KB_COL2_PQ2,
1120         TEGRA_PIN_KB_COL3_PQ3,
1121         TEGRA_PIN_KB_COL4_PQ4,
1122         TEGRA_PIN_KB_COL5_PQ5,
1123         TEGRA_PIN_KB_COL6_PQ6,
1124         TEGRA_PIN_KB_COL7_PQ7,
1125         TEGRA_PIN_KB_ROW8_PS0,
1126         TEGRA_PIN_KB_ROW9_PS1,
1127         TEGRA_PIN_KB_ROW10_PS2,
1128         TEGRA_PIN_SYS_CLK_REQ_PZ5,
1129         TEGRA_PIN_CORE_PWR_REQ,
1130         TEGRA_PIN_CPU_PWR_REQ,
1131         TEGRA_PIN_RESET_OUT_N,
1132 };
1133
1134 static const unsigned drive_at1_pins[] = {
1135         TEGRA_PIN_GMI_AD8_PH0,
1136         TEGRA_PIN_GMI_AD9_PH1,
1137         TEGRA_PIN_GMI_AD10_PH2,
1138         TEGRA_PIN_GMI_AD11_PH3,
1139         TEGRA_PIN_GMI_AD12_PH4,
1140         TEGRA_PIN_GMI_AD13_PH5,
1141         TEGRA_PIN_GMI_AD14_PH6,
1142         TEGRA_PIN_GMI_AD15_PH7,
1143         TEGRA_PIN_GMI_IORDY_PI5,
1144         TEGRA_PIN_GMI_CS7_N_PI6,
1145 };
1146
1147 static const unsigned drive_at2_pins[] = {
1148         TEGRA_PIN_GMI_AD0_PG0,
1149         TEGRA_PIN_GMI_AD1_PG1,
1150         TEGRA_PIN_GMI_AD2_PG2,
1151         TEGRA_PIN_GMI_AD3_PG3,
1152         TEGRA_PIN_GMI_AD4_PG4,
1153         TEGRA_PIN_GMI_AD5_PG5,
1154         TEGRA_PIN_GMI_AD6_PG6,
1155         TEGRA_PIN_GMI_AD7_PG7,
1156         TEGRA_PIN_GMI_WR_N_PI0,
1157         TEGRA_PIN_GMI_OE_N_PI1,
1158         TEGRA_PIN_GMI_CS6_N_PI3,
1159         TEGRA_PIN_GMI_RST_N_PI4,
1160         TEGRA_PIN_GMI_WAIT_PI7,
1161         TEGRA_PIN_GMI_DQS_P_PJ3,
1162         TEGRA_PIN_GMI_ADV_N_PK0,
1163         TEGRA_PIN_GMI_CLK_PK1,
1164         TEGRA_PIN_GMI_CS4_N_PK2,
1165         TEGRA_PIN_GMI_CS2_N_PK3,
1166         TEGRA_PIN_GMI_CS3_N_PK4,
1167 };
1168
1169 static const unsigned drive_at3_pins[] = {
1170         TEGRA_PIN_GMI_WP_N_PC7,
1171         TEGRA_PIN_GMI_CS0_N_PJ0,
1172 };
1173
1174 static const unsigned drive_at4_pins[] = {
1175         TEGRA_PIN_GMI_A17_PB0,
1176         TEGRA_PIN_GMI_A18_PB1,
1177         TEGRA_PIN_GMI_CS1_N_PJ2,
1178         TEGRA_PIN_GMI_A16_PJ7,
1179         TEGRA_PIN_GMI_A19_PK7,
1180 };
1181
1182 static const unsigned drive_at5_pins[] = {
1183         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1184         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1185 };
1186
1187 static const unsigned drive_cdev1_pins[] = {
1188         TEGRA_PIN_CLK1_OUT_PW4,
1189         TEGRA_PIN_CLK1_REQ_PEE2,
1190 };
1191
1192 static const unsigned drive_cdev2_pins[] = {
1193         TEGRA_PIN_CLK2_OUT_PW5,
1194         TEGRA_PIN_CLK2_REQ_PCC5,
1195         TEGRA_PIN_SDMMC1_WP_N_PV3,
1196 };
1197
1198 static const unsigned drive_dap1_pins[] = {
1199         TEGRA_PIN_DAP1_FS_PN0,
1200         TEGRA_PIN_DAP1_DIN_PN1,
1201         TEGRA_PIN_DAP1_DOUT_PN2,
1202         TEGRA_PIN_DAP1_SCLK_PN3,
1203 };
1204
1205 static const unsigned drive_dap2_pins[] = {
1206         TEGRA_PIN_DAP2_FS_PA2,
1207         TEGRA_PIN_DAP2_SCLK_PA3,
1208         TEGRA_PIN_DAP2_DIN_PA4,
1209         TEGRA_PIN_DAP2_DOUT_PA5,
1210 };
1211
1212 static const unsigned drive_dap3_pins[] = {
1213         TEGRA_PIN_DAP3_FS_PP0,
1214         TEGRA_PIN_DAP3_DIN_PP1,
1215         TEGRA_PIN_DAP3_DOUT_PP2,
1216         TEGRA_PIN_DAP3_SCLK_PP3,
1217 };
1218
1219 static const unsigned drive_dap4_pins[] = {
1220         TEGRA_PIN_DAP4_FS_PP4,
1221         TEGRA_PIN_DAP4_DIN_PP5,
1222         TEGRA_PIN_DAP4_DOUT_PP6,
1223         TEGRA_PIN_DAP4_SCLK_PP7,
1224 };
1225
1226 static const unsigned drive_dbg_pins[] = {
1227         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1228         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1229         TEGRA_PIN_PU0,
1230         TEGRA_PIN_PU1,
1231         TEGRA_PIN_PU2,
1232         TEGRA_PIN_PU3,
1233         TEGRA_PIN_PU4,
1234         TEGRA_PIN_PU5,
1235         TEGRA_PIN_PU6,
1236 };
1237
1238 static const unsigned drive_sdio3_pins[] = {
1239         TEGRA_PIN_SDMMC3_CLK_PA6,
1240         TEGRA_PIN_SDMMC3_CMD_PA7,
1241         TEGRA_PIN_SDMMC3_DAT3_PB4,
1242         TEGRA_PIN_SDMMC3_DAT2_PB5,
1243         TEGRA_PIN_SDMMC3_DAT1_PB6,
1244         TEGRA_PIN_SDMMC3_DAT0_PB7,
1245         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1246         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1247 };
1248
1249 static const unsigned drive_spi_pins[] = {
1250         TEGRA_PIN_DVFS_PWM_PX0,
1251         TEGRA_PIN_GPIO_X1_AUD_PX1,
1252         TEGRA_PIN_DVFS_CLK_PX2,
1253         TEGRA_PIN_GPIO_X3_AUD_PX3,
1254         TEGRA_PIN_GPIO_X4_AUD_PX4,
1255         TEGRA_PIN_GPIO_X5_AUD_PX5,
1256         TEGRA_PIN_GPIO_X6_AUD_PX6,
1257         TEGRA_PIN_GPIO_X7_AUD_PX7,
1258         TEGRA_PIN_GPIO_W2_AUD_PW2,
1259         TEGRA_PIN_GPIO_W3_AUD_PW3,
1260 };
1261
1262 static const unsigned drive_uaa_pins[] = {
1263         TEGRA_PIN_ULPI_DATA0_PO1,
1264         TEGRA_PIN_ULPI_DATA1_PO2,
1265         TEGRA_PIN_ULPI_DATA2_PO3,
1266         TEGRA_PIN_ULPI_DATA3_PO4,
1267 };
1268
1269 static const unsigned drive_uab_pins[] = {
1270         TEGRA_PIN_ULPI_DATA7_PO0,
1271         TEGRA_PIN_ULPI_DATA4_PO5,
1272         TEGRA_PIN_ULPI_DATA5_PO6,
1273         TEGRA_PIN_ULPI_DATA6_PO7,
1274         TEGRA_PIN_PV0,
1275         TEGRA_PIN_PV1,
1276 };
1277
1278 static const unsigned drive_uart2_pins[] = {
1279         TEGRA_PIN_UART2_TXD_PC2,
1280         TEGRA_PIN_UART2_RXD_PC3,
1281         TEGRA_PIN_UART2_CTS_N_PJ5,
1282         TEGRA_PIN_UART2_RTS_N_PJ6,
1283 };
1284
1285 static const unsigned drive_uart3_pins[] = {
1286         TEGRA_PIN_UART3_CTS_N_PA1,
1287         TEGRA_PIN_UART3_RTS_N_PC0,
1288         TEGRA_PIN_UART3_TXD_PW6,
1289         TEGRA_PIN_UART3_RXD_PW7,
1290 };
1291
1292 static const unsigned drive_sdio1_pins[] = {
1293         TEGRA_PIN_SDMMC1_DAT3_PY4,
1294         TEGRA_PIN_SDMMC1_DAT2_PY5,
1295         TEGRA_PIN_SDMMC1_DAT1_PY6,
1296         TEGRA_PIN_SDMMC1_DAT0_PY7,
1297         TEGRA_PIN_SDMMC1_CLK_PZ0,
1298         TEGRA_PIN_SDMMC1_CMD_PZ1,
1299 };
1300
1301 static const unsigned drive_ddc_pins[] = {
1302         TEGRA_PIN_DDC_SCL_PV4,
1303         TEGRA_PIN_DDC_SDA_PV5,
1304 };
1305
1306 static const unsigned drive_gma_pins[] = {
1307         TEGRA_PIN_SDMMC4_CLK_PCC4,
1308         TEGRA_PIN_SDMMC4_CMD_PT7,
1309         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1310         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1311         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1312         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1313         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1314         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1315         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1316         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1317 };
1318
1319 static const unsigned drive_gme_pins[] = {
1320         TEGRA_PIN_PBB0,
1321         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1322         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1323         TEGRA_PIN_PBB3,
1324         TEGRA_PIN_PCC2,
1325 };
1326
1327 static const unsigned drive_gmf_pins[] = {
1328         TEGRA_PIN_PBB4,
1329         TEGRA_PIN_PBB5,
1330         TEGRA_PIN_PBB6,
1331         TEGRA_PIN_PBB7,
1332 };
1333
1334 static const unsigned drive_gmg_pins[] = {
1335         TEGRA_PIN_CAM_MCLK_PCC0,
1336 };
1337
1338 static const unsigned drive_gmh_pins[] = {
1339         TEGRA_PIN_PCC1,
1340 };
1341
1342 static const unsigned drive_owr_pins[] = {
1343         TEGRA_PIN_SDMMC3_CD_N_PV2,
1344 };
1345
1346 static const unsigned drive_uda_pins[] = {
1347         TEGRA_PIN_ULPI_CLK_PY0,
1348         TEGRA_PIN_ULPI_DIR_PY1,
1349         TEGRA_PIN_ULPI_NXT_PY2,
1350         TEGRA_PIN_ULPI_STP_PY3,
1351 };
1352
1353 static const unsigned drive_dev3_pins[] = {
1354 };
1355
1356 static const unsigned drive_cec_pins[] = {
1357 };
1358
1359 static const unsigned drive_at6_pins[] = {
1360 };
1361
1362 static const unsigned drive_dap5_pins[] = {
1363 };
1364
1365 static const unsigned drive_usb_vbus_en_pins[] = {
1366 };
1367
1368 static const unsigned drive_ao3_pins[] = {
1369 };
1370
1371 static const unsigned drive_hv0_pins[] = {
1372 };
1373
1374 static const unsigned drive_sdio4_pins[] = {
1375 };
1376
1377 static const unsigned drive_ao0_pins[] = {
1378 };
1379
1380 enum tegra_mux {
1381         TEGRA_MUX_BLINK,
1382         TEGRA_MUX_CEC,
1383         TEGRA_MUX_CLDVFS,
1384         TEGRA_MUX_CLK,
1385         TEGRA_MUX_CLK12,
1386         TEGRA_MUX_CPU,
1387         TEGRA_MUX_DAP,
1388         TEGRA_MUX_DAP1,
1389         TEGRA_MUX_DAP2,
1390         TEGRA_MUX_DEV3,
1391         TEGRA_MUX_DISPLAYA,
1392         TEGRA_MUX_DISPLAYA_ALT,
1393         TEGRA_MUX_DISPLAYB,
1394         TEGRA_MUX_DTV,
1395         TEGRA_MUX_EMC_DLL,
1396         TEGRA_MUX_EXTPERIPH1,
1397         TEGRA_MUX_EXTPERIPH2,
1398         TEGRA_MUX_EXTPERIPH3,
1399         TEGRA_MUX_GMI,
1400         TEGRA_MUX_GMI_ALT,
1401         TEGRA_MUX_HDA,
1402         TEGRA_MUX_HSI,
1403         TEGRA_MUX_I2C1,
1404         TEGRA_MUX_I2C2,
1405         TEGRA_MUX_I2C3,
1406         TEGRA_MUX_I2C4,
1407         TEGRA_MUX_I2CPWR,
1408         TEGRA_MUX_I2S0,
1409         TEGRA_MUX_I2S1,
1410         TEGRA_MUX_I2S2,
1411         TEGRA_MUX_I2S3,
1412         TEGRA_MUX_I2S4,
1413         TEGRA_MUX_IRDA,
1414         TEGRA_MUX_KBC,
1415         TEGRA_MUX_NAND,
1416         TEGRA_MUX_NAND_ALT,
1417         TEGRA_MUX_OWR,
1418         TEGRA_MUX_PMI,
1419         TEGRA_MUX_PWM0,
1420         TEGRA_MUX_PWM1,
1421         TEGRA_MUX_PWM2,
1422         TEGRA_MUX_PWM3,
1423         TEGRA_MUX_PWRON,
1424         TEGRA_MUX_RESET_OUT_N,
1425         TEGRA_MUX_RSVD1,
1426         TEGRA_MUX_RSVD2,
1427         TEGRA_MUX_RSVD3,
1428         TEGRA_MUX_RSVD4,
1429         TEGRA_MUX_RTCK,
1430         TEGRA_MUX_SDMMC1,
1431         TEGRA_MUX_SDMMC2,
1432         TEGRA_MUX_SDMMC3,
1433         TEGRA_MUX_SDMMC4,
1434         TEGRA_MUX_SOC,
1435         TEGRA_MUX_SPDIF,
1436         TEGRA_MUX_SPI1,
1437         TEGRA_MUX_SPI2,
1438         TEGRA_MUX_SPI3,
1439         TEGRA_MUX_SPI4,
1440         TEGRA_MUX_SPI5,
1441         TEGRA_MUX_SPI6,
1442         TEGRA_MUX_SYSCLK,
1443         TEGRA_MUX_TRACE,
1444         TEGRA_MUX_UARTA,
1445         TEGRA_MUX_UARTB,
1446         TEGRA_MUX_UARTC,
1447         TEGRA_MUX_UARTD,
1448         TEGRA_MUX_ULPI,
1449         TEGRA_MUX_USB,
1450         TEGRA_MUX_VGP1,
1451         TEGRA_MUX_VGP2,
1452         TEGRA_MUX_VGP3,
1453         TEGRA_MUX_VGP4,
1454         TEGRA_MUX_VGP5,
1455         TEGRA_MUX_VGP6,
1456         TEGRA_MUX_VI,
1457         TEGRA_MUX_VI_ALT1,
1458         TEGRA_MUX_VI_ALT3,
1459 };
1460
1461 #define FUNCTION(fname)                                 \
1462         {                                               \
1463                 .name = #fname,                         \
1464         }
1465
1466 static struct tegra_function tegra114_functions[] = {
1467         FUNCTION(blink),
1468         FUNCTION(cec),
1469         FUNCTION(cldvfs),
1470         FUNCTION(clk),
1471         FUNCTION(clk12),
1472         FUNCTION(cpu),
1473         FUNCTION(dap),
1474         FUNCTION(dap1),
1475         FUNCTION(dap2),
1476         FUNCTION(dev3),
1477         FUNCTION(displaya),
1478         FUNCTION(displaya_alt),
1479         FUNCTION(displayb),
1480         FUNCTION(dtv),
1481         FUNCTION(emc_dll),
1482         FUNCTION(extperiph1),
1483         FUNCTION(extperiph2),
1484         FUNCTION(extperiph3),
1485         FUNCTION(gmi),
1486         FUNCTION(gmi_alt),
1487         FUNCTION(hda),
1488         FUNCTION(hsi),
1489         FUNCTION(i2c1),
1490         FUNCTION(i2c2),
1491         FUNCTION(i2c3),
1492         FUNCTION(i2c4),
1493         FUNCTION(i2cpwr),
1494         FUNCTION(i2s0),
1495         FUNCTION(i2s1),
1496         FUNCTION(i2s2),
1497         FUNCTION(i2s3),
1498         FUNCTION(i2s4),
1499         FUNCTION(irda),
1500         FUNCTION(kbc),
1501         FUNCTION(nand),
1502         FUNCTION(nand_alt),
1503         FUNCTION(owr),
1504         FUNCTION(pmi),
1505         FUNCTION(pwm0),
1506         FUNCTION(pwm1),
1507         FUNCTION(pwm2),
1508         FUNCTION(pwm3),
1509         FUNCTION(pwron),
1510         FUNCTION(reset_out_n),
1511         FUNCTION(rsvd1),
1512         FUNCTION(rsvd2),
1513         FUNCTION(rsvd3),
1514         FUNCTION(rsvd4),
1515         FUNCTION(rtck),
1516         FUNCTION(sdmmc1),
1517         FUNCTION(sdmmc2),
1518         FUNCTION(sdmmc3),
1519         FUNCTION(sdmmc4),
1520         FUNCTION(soc),
1521         FUNCTION(spdif),
1522         FUNCTION(spi1),
1523         FUNCTION(spi2),
1524         FUNCTION(spi3),
1525         FUNCTION(spi4),
1526         FUNCTION(spi5),
1527         FUNCTION(spi6),
1528         FUNCTION(sysclk),
1529         FUNCTION(trace),
1530         FUNCTION(uarta),
1531         FUNCTION(uartb),
1532         FUNCTION(uartc),
1533         FUNCTION(uartd),
1534         FUNCTION(ulpi),
1535         FUNCTION(usb),
1536         FUNCTION(vgp1),
1537         FUNCTION(vgp2),
1538         FUNCTION(vgp3),
1539         FUNCTION(vgp4),
1540         FUNCTION(vgp5),
1541         FUNCTION(vgp6),
1542         FUNCTION(vi),
1543         FUNCTION(vi_alt1),
1544         FUNCTION(vi_alt3),
1545 };
1546
1547 #define DRV_PINGROUP_REG_A              0x868   /* bank 0 */
1548 #define PINGROUP_REG_A                  0x3000  /* bank 1 */
1549
1550 #define DRV_PINGROUP_REG(r)             ((r) - DRV_PINGROUP_REG_A)
1551 #define PINGROUP_REG(r)                 ((r) - PINGROUP_REG_A)
1552
1553 #define PINGROUP_BIT_Y(b)               (b)
1554 #define PINGROUP_BIT_N(b)               (-1)
1555
1556 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel)          \
1557         {                                                               \
1558                 .name = #pg_name,                                       \
1559                 .pins = pg_name##_pins,                                 \
1560                 .npins = ARRAY_SIZE(pg_name##_pins),                    \
1561                 .funcs = {                                              \
1562                         TEGRA_MUX_##f0,                                 \
1563                         TEGRA_MUX_##f1,                                 \
1564                         TEGRA_MUX_##f2,                                 \
1565                         TEGRA_MUX_##f3,                                 \
1566                 },                                                      \
1567                 .mux_reg = PINGROUP_REG(r),                             \
1568                 .mux_bank = 1,                                          \
1569                 .mux_bit = 0,                                           \
1570                 .pupd_reg = PINGROUP_REG(r),                            \
1571                 .pupd_bank = 1,                                         \
1572                 .pupd_bit = 2,                                          \
1573                 .tri_reg = PINGROUP_REG(r),                             \
1574                 .tri_bank = 1,                                          \
1575                 .tri_bit = 4,                                           \
1576                 .einput_bit = 5,                                        \
1577                 .odrain_bit = PINGROUP_BIT_##od(6),                     \
1578                 .lock_bit = 7,                                          \
1579                 .ioreset_bit = PINGROUP_BIT_##ior(8),                   \
1580                 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9),               \
1581                 .parked_bit = -1,                                       \
1582                 .drv_reg = -1,                                          \
1583         }
1584
1585 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b,     \
1586                      drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w,         \
1587                      slwf_b, slwf_w, drvtype)                           \
1588         {                                                               \
1589                 .name = "drive_" #pg_name,                              \
1590                 .pins = drive_##pg_name##_pins,                         \
1591                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),            \
1592                 .mux_reg = -1,                                          \
1593                 .pupd_reg = -1,                                         \
1594                 .tri_reg = -1,                                          \
1595                 .einput_bit = -1,                                       \
1596                 .odrain_bit = -1,                                       \
1597                 .lock_bit = -1,                                         \
1598                 .ioreset_bit = -1,                                      \
1599                 .rcv_sel_bit = -1,                                      \
1600                 .drv_reg = DRV_PINGROUP_REG(r),                         \
1601                 .drv_bank = 0,                                          \
1602                 .parked_bit = -1,                                       \
1603                 .hsm_bit = hsm_b,                                       \
1604                 .schmitt_bit = schmitt_b,                               \
1605                 .lpmd_bit = lpmd_b,                                     \
1606                 .drvdn_bit = drvdn_b,                                   \
1607                 .drvdn_width = drvdn_w,                                 \
1608                 .drvup_bit = drvup_b,                                   \
1609                 .drvup_width = drvup_w,                                 \
1610                 .slwr_bit = slwr_b,                                     \
1611                 .slwr_width = slwr_w,                                   \
1612                 .slwf_bit = slwf_b,                                     \
1613                 .slwf_width = slwf_w,                                   \
1614                 .drvtype_bit = PINGROUP_BIT_##drvtype(6),               \
1615         }
1616
1617 static const struct tegra_pingroup tegra114_groups[] = {
1618         /*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
1619         PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
1620         PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        0x3004, N,   N,  N),
1621         PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        0x3008, N,   N,  N),
1622         PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        0x300c, N,   N,  N),
1623         PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        0x3010, N,   N,  N),
1624         PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        0x3014, N,   N,  N),
1625         PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        0x3018, N,   N,  N),
1626         PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        0x301c, N,   N,  N),
1627         PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        0x3020, N,   N,  N),
1628         PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        0x3024, N,   N,  N),
1629         PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        0x3028, N,   N,  N),
1630         PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        0x302c, N,   N,  N),
1631         PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3030, N,   N,  N),
1632         PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3034, N,   N,  N),
1633         PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3038, N,   N,  N),
1634         PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x303c, N,   N,  N),
1635         PINGROUP(pv0,                    USB,        RSVD2,      RSVD3,        RSVD4,       0x3040, N,   N,  N),
1636         PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3044, N,   N,  N),
1637         PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       0x3048, N,   N,  N),
1638         PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       0x304c, N,   N,  N),
1639         PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       0x3050, N,   N,  N),
1640         PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       0x3054, N,   N,  N),
1641         PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       0x3058, N,   N,  N),
1642         PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       0x305c, N,   N,  N),
1643         PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       0x3068, N,   N,  N),
1644         PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       0x306c, N,   N,  N),
1645         PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3110, N,   N,  Y),
1646         PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3114, N,   N,  Y),
1647         PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3118, N,   N,  Y),
1648         PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3164, N,   N,  N),
1649         PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3168, N,   N,  N),
1650         PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      RSVD3,        SPI4,        0x316c, N,   N,  N),
1651         PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      RSVD3,        SPI4,        0x3170, N,   N,  N),
1652         PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      RSVD3,        SPI4,        0x3174, N,   N,  N),
1653         PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      RSVD3,        SPI4,        0x3178, N,   N,  N),
1654         PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          SPI4,        0x317c, N,   N,  N),
1655         PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          DISPLAYA,    0x3180, N,   N,  N),
1656         PINGROUP(pu0,                    OWR,        UARTA,      RSVD3,        RSVD4,       0x3184, N,   N,  N),
1657         PINGROUP(pu1,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       0x3188, N,   N,  N),
1658         PINGROUP(pu2,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       0x318c, N,   N,  N),
1659         PINGROUP(pu3,                    PWM0,       UARTA,      DISPLAYA,     DISPLAYB,    0x3190, N,   N,  N),
1660         PINGROUP(pu4,                    PWM1,       UARTA,      DISPLAYA,     DISPLAYB,    0x3194, N,   N,  N),
1661         PINGROUP(pu5,                    PWM2,       UARTA,      DISPLAYA,     DISPLAYB,    0x3198, N,   N,  N),
1662         PINGROUP(pu6,                    PWM3,       UARTA,      USB,          DISPLAYB,    0x319c, N,   N,  N),
1663         PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a0, Y,   N,  N),
1664         PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a4, Y,   N,  N),
1665         PINGROUP(dap4_fs_pp4,            I2S3,       RSVD2,      DTV,          RSVD4,       0x31a8, N,   N,  N),
1666         PINGROUP(dap4_din_pp5,           I2S3,       RSVD2,      RSVD3,        RSVD4,       0x31ac, N,   N,  N),
1667         PINGROUP(dap4_dout_pp6,          I2S3,       RSVD2,      DTV,          RSVD4,       0x31b0, N,   N,  N),
1668         PINGROUP(dap4_sclk_pp7,          I2S3,       RSVD2,      RSVD3,        RSVD4,       0x31b4, N,   N,  N),
1669         PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       0x31b8, N,   N,  N),
1670         PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       0x31bc, N,   N,  N),
1671         PINGROUP(gmi_wp_n_pc7,           RSVD1,      NAND,       GMI,          GMI_ALT,     0x31c0, N,   N,  N),
1672         PINGROUP(gmi_iordy_pi5,          SDMMC2,     RSVD2,      GMI,          TRACE,       0x31c4, N,   N,  N),
1673         PINGROUP(gmi_wait_pi7,           SPI4,       NAND,       GMI,          DTV,         0x31c8, N,   N,  N),
1674         PINGROUP(gmi_adv_n_pk0,          RSVD1,      NAND,       GMI,          TRACE,       0x31cc, N,   N,  N),
1675         PINGROUP(gmi_clk_pk1,            SDMMC2,     NAND,       GMI,          TRACE,       0x31d0, N,   N,  N),
1676         PINGROUP(gmi_cs0_n_pj0,          RSVD1,      NAND,       GMI,          USB,         0x31d4, N,   N,  N),
1677         PINGROUP(gmi_cs1_n_pj2,          RSVD1,      NAND,       GMI,          SOC,         0x31d8, N,   N,  N),
1678         PINGROUP(gmi_cs2_n_pk3,          SDMMC2,     NAND,       GMI,          TRACE,       0x31dc, N,   N,  N),
1679         PINGROUP(gmi_cs3_n_pk4,          SDMMC2,     NAND,       GMI,          GMI_ALT,     0x31e0, N,   N,  N),
1680         PINGROUP(gmi_cs4_n_pk2,          USB,        NAND,       GMI,          TRACE,       0x31e4, N,   N,  N),
1681         PINGROUP(gmi_cs6_n_pi3,          NAND,       NAND_ALT,   GMI,          SPI4,        0x31e8, N,   N,  N),
1682         PINGROUP(gmi_cs7_n_pi6,          NAND,       NAND_ALT,   GMI,          SDMMC2,      0x31ec, N,   N,  N),
1683         PINGROUP(gmi_ad0_pg0,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f0, N,   N,  N),
1684         PINGROUP(gmi_ad1_pg1,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f4, N,   N,  N),
1685         PINGROUP(gmi_ad2_pg2,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f8, N,   N,  N),
1686         PINGROUP(gmi_ad3_pg3,            RSVD1,      NAND,       GMI,          RSVD4,       0x31fc, N,   N,  N),
1687         PINGROUP(gmi_ad4_pg4,            RSVD1,      NAND,       GMI,          RSVD4,       0x3200, N,   N,  N),
1688         PINGROUP(gmi_ad5_pg5,            RSVD1,      NAND,       GMI,          SPI4,        0x3204, N,   N,  N),
1689         PINGROUP(gmi_ad6_pg6,            RSVD1,      NAND,       GMI,          SPI4,        0x3208, N,   N,  N),
1690         PINGROUP(gmi_ad7_pg7,            RSVD1,      NAND,       GMI,          SPI4,        0x320c, N,   N,  N),
1691         PINGROUP(gmi_ad8_ph0,            PWM0,       NAND,       GMI,          DTV,         0x3210, N,   N,  N),
1692         PINGROUP(gmi_ad9_ph1,            PWM1,       NAND,       GMI,          CLDVFS,      0x3214, N,   N,  N),
1693         PINGROUP(gmi_ad10_ph2,           PWM2,       NAND,       GMI,          CLDVFS,      0x3218, N,   N,  N),
1694         PINGROUP(gmi_ad11_ph3,           PWM3,       NAND,       GMI,          USB,         0x321c, N,   N,  N),
1695         PINGROUP(gmi_ad12_ph4,           SDMMC2,     NAND,       GMI,          RSVD4,       0x3220, N,   N,  N),
1696         PINGROUP(gmi_ad13_ph5,           SDMMC2,     NAND,       GMI,          RSVD4,       0x3224, N,   N,  N),
1697         PINGROUP(gmi_ad14_ph6,           SDMMC2,     NAND,       GMI,          DTV,         0x3228, N,   N,  N),
1698         PINGROUP(gmi_ad15_ph7,           SDMMC2,     NAND,       GMI,          DTV,         0x322c, N,   N,  N),
1699         PINGROUP(gmi_a16_pj7,            UARTD,      TRACE,      GMI,          GMI_ALT,     0x3230, N,   N,  N),
1700         PINGROUP(gmi_a17_pb0,            UARTD,      RSVD2,      GMI,          TRACE,       0x3234, N,   N,  N),
1701         PINGROUP(gmi_a18_pb1,            UARTD,      RSVD2,      GMI,          TRACE,       0x3238, N,   N,  N),
1702         PINGROUP(gmi_a19_pk7,            UARTD,      SPI4,       GMI,          TRACE,       0x323c, N,   N,  N),
1703         PINGROUP(gmi_wr_n_pi0,           RSVD1,      NAND,       GMI,          SPI4,        0x3240, N,   N,  N),
1704         PINGROUP(gmi_oe_n_pi1,           RSVD1,      NAND,       GMI,          SOC,         0x3244, N,   N,  N),
1705         PINGROUP(gmi_dqs_p_pj3,          SDMMC2,     NAND,       GMI,          TRACE,       0x3248, N,   N,  N),
1706         PINGROUP(gmi_rst_n_pi4,          NAND,       NAND_ALT,   GMI,          RSVD4,       0x324c, N,   N,  N),
1707         PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3250, Y,   N,  N),
1708         PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3254, Y,   N,  N),
1709         PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       0x3258, N,   Y,  N),
1710         PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       0x325c, N,   Y,  N),
1711         PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3260, N,   Y,  N),
1712         PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3264, N,   Y,  N),
1713         PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3268, N,   Y,  N),
1714         PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x326c, N,   Y,  N),
1715         PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3270, N,   Y,  N),
1716         PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3274, N,   Y,  N),
1717         PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3278, N,   Y,  N),
1718         PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       0x327c, N,   Y,  N),
1719         PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      RSVD4,       0x3284, N,   N,  N),
1720         PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x3288, N,   N,  N),
1721         PINGROUP(pbb0,                   I2S4,       VI,         VI_ALT1,      VI_ALT3,     0x328c, N,   N,  N),
1722         PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        RSVD4,       0x3290, Y,   N,  N),
1723         PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        RSVD4,       0x3294, Y,   N,  N),
1724         PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     RSVD4,       0x3298, N,   N,  N),
1725         PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     RSVD4,       0x329c, N,   N,  N),
1726         PINGROUP(pbb5,                   VGP5,       DISPLAYA,   DISPLAYB,     RSVD4,       0x32a0, N,   N,  N),
1727         PINGROUP(pbb6,                   VGP6,       DISPLAYA,   DISPLAYB,     RSVD4,       0x32a4, N,   N,  N),
1728         PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x32a8, N,   N,  N),
1729         PINGROUP(pcc2,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x32ac, N,   N,  N),
1730         PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       0x32b0, N,   N,  N),
1731         PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b4, Y,   N,  N),
1732         PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b8, Y,   N,  N),
1733         PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32bc, N,   N,  N),
1734         PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c0, N,   N,  N),
1735         PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c4, N,   N,  N),
1736         PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32c8, N,   N,  N),
1737         PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    0x32cc, N,   N,  N),
1738         PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    0x32d0, N,   N,  N),
1739         PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    0x32d4, N,   N,  N),
1740         PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32d8, N,   N,  N),
1741         PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32dc, N,   N,  N),
1742         PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       0x32e0, N,   N,  N),
1743         PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       0x32e4, N,   N,  N),
1744         PINGROUP(kb_col0_pq0,            KBC,        USB,        SPI2,         EMC_DLL,     0x32fc, N,   N,  N),
1745         PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         EMC_DLL,     0x3300, N,   N,  N),
1746         PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3304, N,   N,  N),
1747         PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       0x3308, N,   N,  N),
1748         PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       0x330c, N,   N,  N),
1749         PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC1,       RSVD4,       0x3310, N,   N,  N),
1750         PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3314, N,   N,  N),
1751         PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3318, N,   N,  N),
1752         PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       0x331c, N,   N,  N),
1753         PINGROUP(sys_clk_req_pz5,        SYSCLK,     RSVD2,      RSVD3,        RSVD4,       0x3320, N,   N,  N),
1754         PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       0x3324, N,   N,  N),
1755         PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       0x3328, N,   N,  N),
1756         PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       0x332c, N,   N,  N),
1757         PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       0x3330, N,   N,  N),
1758         PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       0x3334, N,   N,  Y),
1759         PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       0x3338, N,   N,  N),
1760         PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       0x333c, N,   N,  N),
1761         PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          RSVD4,       0x3340, N,   N,  N),
1762         PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       0x3344, N,   N,  N),
1763         PINGROUP(clk1_req_pee2,          DAP,        DAP1,       RSVD3,        RSVD4,       0x3348, N,   N,  N),
1764         PINGROUP(clk1_out_pw4,           EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       0x334c, N,   N,  N),
1765         PINGROUP(spdif_in_pk6,           SPDIF,      USB,        RSVD3,        RSVD4,       0x3350, N,   N,  N),
1766         PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        RSVD4,       0x3354, N,   N,  N),
1767         PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        RSVD3,        RSVD4,       0x3358, N,   N,  N),
1768         PINGROUP(dap2_din_pa4,           I2S1,       HDA,        RSVD3,        RSVD4,       0x335c, N,   N,  N),
1769         PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        RSVD3,        RSVD4,       0x3360, N,   N,  N),
1770         PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        RSVD3,        RSVD4,       0x3364, N,   N,  N),
1771         PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       0x3368, N,   N,  N),
1772         PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      RSVD3,        RSVD4,       0x336c, N,   N,  N),
1773         PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       RSVD3,        RSVD4,       0x3370, N,   N,  N),
1774         PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       0x3374, N,   N,  N),
1775         PINGROUP(gpio_x4_aud_px4,        RSVD1,      SPI1,       SPI2,         DAP2,        0x3378, N,   N,  N),
1776         PINGROUP(gpio_x5_aud_px5,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x337c, N,   N,  N),
1777         PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         RSVD4,       0x3380, N,   N,  N),
1778         PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x3384, N,   N,  N),
1779         PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3390, N,   N,  N),
1780         PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        0x3394, N,   N,  N),
1781         PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3398, N,   N,  N),
1782         PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        0x339c, N,   N,  N),
1783         PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        0x33a0, N,   N,  N),
1784         PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        0x33a4, N,   N,  N),
1785         PINGROUP(hdmi_cec_pee3,          CEC,        SDMMC3,     RSVD3,        SOC,         0x33e0, Y,   N,  N),
1786         PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       0x33e4, N,   N,  N),
1787         PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       0x33e8, N,   N,  N),
1788         PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        0x33ec, N,   N,  N),
1789         PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        0x33f0, N,   N,  N),
1790         PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f4, Y,   N,  N),
1791         PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f8, Y,   N,  N),
1792         PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x33fc, N,   N,  N),
1793         PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x3400, N,   N,  N),
1794         PINGROUP(gmi_clk_lb,             SDMMC2,     NAND,       GMI,          RSVD4,       0x3404, N,   N,  N),
1795         PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, 0x3408, N,   N,  N),
1796
1797         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1798         DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1799         DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1800         DRV_PINGROUP(at1,         0x870,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1801         DRV_PINGROUP(at2,         0x874,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1802         DRV_PINGROUP(at3,         0x878,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1803         DRV_PINGROUP(at4,         0x87c,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1804         DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1805         DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1806         DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1807         DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1808         DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1809         DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1810         DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1811         DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1812         DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1813         DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1814         DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1815         DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1816         DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1817         DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1818         DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1819         DRV_PINGROUP(ddc,         0x8fc,  2,  3, -1,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1820         DRV_PINGROUP(gma,         0x900,  2,  3, -1,  14,  5,  20,  5,  28,  2,  30,  2,  N),
1821         DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1822         DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1823         DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1824         DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1825         DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1826         DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1827         DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1828         DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1829         DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  Y),
1830         DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1831         DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1832         DRV_PINGROUP(ao3,         0x9a0,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1833         DRV_PINGROUP(hv0,         0x9a4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1834         DRV_PINGROUP(sdio4,       0x9a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1835         DRV_PINGROUP(ao0,         0x9ac,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1836 };
1837
1838 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
1839         .ngpios = NUM_GPIOS,
1840         .pins = tegra114_pins,
1841         .npins = ARRAY_SIZE(tegra114_pins),
1842         .functions = tegra114_functions,
1843         .nfunctions = ARRAY_SIZE(tegra114_functions),
1844         .groups = tegra114_groups,
1845         .ngroups = ARRAY_SIZE(tegra114_groups),
1846         .hsm_in_mux = false,
1847         .schmitt_in_mux = false,
1848         .drvtype_in_mux = false,
1849 };
1850
1851 static int tegra114_pinctrl_probe(struct platform_device *pdev)
1852 {
1853         return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
1854 }
1855
1856 static const struct of_device_id tegra114_pinctrl_of_match[] = {
1857         { .compatible = "nvidia,tegra114-pinmux", },
1858         { },
1859 };
1860 MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
1861
1862 static struct platform_driver tegra114_pinctrl_driver = {
1863         .driver = {
1864                 .name = "tegra114-pinctrl",
1865                 .of_match_table = tegra114_pinctrl_of_match,
1866         },
1867         .probe = tegra114_pinctrl_probe,
1868 };
1869 module_platform_driver(tegra114_pinctrl_driver);
1870
1871 MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
1872 MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver");
1873 MODULE_LICENSE("GPL v2");