2 * Driver for NEC VR4100 series General-purpose I/O Unit.
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
24 #include <linux/gpio.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/spinlock.h>
33 #include <linux/types.h>
35 #include <asm/vr41xx/giu.h>
36 #include <asm/vr41xx/irq.h>
37 #include <asm/vr41xx/vr41xx.h>
39 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
40 MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
41 MODULE_LICENSE("GPL");
43 #define GIUIOSELL 0x00
44 #define GIUIOSELH 0x02
47 #define GIUINTSTATL 0x08
48 #define GIUINTSTATH 0x0a
49 #define GIUINTENL 0x0c
50 #define GIUINTENH 0x0e
51 #define GIUINTTYPL 0x10
52 #define GIUINTTYPH 0x12
53 #define GIUINTALSELL 0x14
54 #define GIUINTALSELH 0x16
55 #define GIUINTHTSELL 0x18
56 #define GIUINTHTSELH 0x1a
57 #define GIUPODATL 0x1c
58 #define GIUPODATEN 0x1c
59 #define GIUPODATH 0x1e
63 #define GIUFEDGEINHL 0x20
64 #define GIUFEDGEINHH 0x22
65 #define GIUREDGEINHL 0x24
66 #define GIUREDGEINHH 0x26
68 #define GIUUSEUPDN 0x1e0
69 #define GIUTERMUPDN 0x1e2
71 #define GPIO_HAS_PULLUPDOWN_IO 0x0001
72 #define GPIO_HAS_OUTPUT_ENABLE 0x0002
73 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
80 static DEFINE_SPINLOCK(giu_lock
);
81 static unsigned long giu_flags
;
83 static void __iomem
*giu_base
;
84 static struct gpio_chip vr41xx_gpio_chip
;
86 #define giu_read(offset) readw(giu_base + (offset))
87 #define giu_write(offset, value) writew((value), giu_base + (offset))
89 #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90 #define GIUINT_HIGH_OFFSET 16
91 #define GIUINT_HIGH_MAX 32
93 static inline u16
giu_set(u16 offset
, u16 set
)
97 data
= giu_read(offset
);
99 giu_write(offset
, data
);
104 static inline u16
giu_clear(u16 offset
, u16 clear
)
108 data
= giu_read(offset
);
110 giu_write(offset
, data
);
115 static void ack_giuint_low(struct irq_data
*d
)
117 giu_write(GIUINTSTATL
, 1 << GPIO_PIN_OF_IRQ(d
->irq
));
120 static void mask_giuint_low(struct irq_data
*d
)
122 giu_clear(GIUINTENL
, 1 << GPIO_PIN_OF_IRQ(d
->irq
));
125 static void mask_ack_giuint_low(struct irq_data
*d
)
129 pin
= GPIO_PIN_OF_IRQ(d
->irq
);
130 giu_clear(GIUINTENL
, 1 << pin
);
131 giu_write(GIUINTSTATL
, 1 << pin
);
134 static void unmask_giuint_low(struct irq_data
*d
)
136 giu_set(GIUINTENL
, 1 << GPIO_PIN_OF_IRQ(d
->irq
));
139 static unsigned int startup_giuint(struct irq_data
*data
)
141 if (gpiochip_lock_as_irq(&vr41xx_gpio_chip
, data
->hwirq
))
142 dev_err(vr41xx_gpio_chip
.parent
,
143 "unable to lock HW IRQ %lu for IRQ\n",
145 /* Satisfy the .enable semantics by unmasking the line */
146 unmask_giuint_low(data
);
150 static void shutdown_giuint(struct irq_data
*data
)
152 mask_giuint_low(data
);
153 gpiochip_unlock_as_irq(&vr41xx_gpio_chip
, data
->hwirq
);
156 static struct irq_chip giuint_low_irq_chip
= {
158 .irq_ack
= ack_giuint_low
,
159 .irq_mask
= mask_giuint_low
,
160 .irq_mask_ack
= mask_ack_giuint_low
,
161 .irq_unmask
= unmask_giuint_low
,
162 .irq_startup
= startup_giuint
,
163 .irq_shutdown
= shutdown_giuint
,
166 static void ack_giuint_high(struct irq_data
*d
)
168 giu_write(GIUINTSTATH
,
169 1 << (GPIO_PIN_OF_IRQ(d
->irq
) - GIUINT_HIGH_OFFSET
));
172 static void mask_giuint_high(struct irq_data
*d
)
174 giu_clear(GIUINTENH
, 1 << (GPIO_PIN_OF_IRQ(d
->irq
) - GIUINT_HIGH_OFFSET
));
177 static void mask_ack_giuint_high(struct irq_data
*d
)
181 pin
= GPIO_PIN_OF_IRQ(d
->irq
) - GIUINT_HIGH_OFFSET
;
182 giu_clear(GIUINTENH
, 1 << pin
);
183 giu_write(GIUINTSTATH
, 1 << pin
);
186 static void unmask_giuint_high(struct irq_data
*d
)
188 giu_set(GIUINTENH
, 1 << (GPIO_PIN_OF_IRQ(d
->irq
) - GIUINT_HIGH_OFFSET
));
191 static struct irq_chip giuint_high_irq_chip
= {
193 .irq_ack
= ack_giuint_high
,
194 .irq_mask
= mask_giuint_high
,
195 .irq_mask_ack
= mask_ack_giuint_high
,
196 .irq_unmask
= unmask_giuint_high
,
199 static int giu_get_irq(unsigned int irq
)
201 u16 pendl
, pendh
, maskl
, maskh
;
204 pendl
= giu_read(GIUINTSTATL
);
205 pendh
= giu_read(GIUINTSTATH
);
206 maskl
= giu_read(GIUINTENL
);
207 maskh
= giu_read(GIUINTENH
);
213 for (i
= 0; i
< 16; i
++) {
214 if (maskl
& (1 << i
))
218 for (i
= 0; i
< 16; i
++) {
219 if (maskh
& (1 << i
))
220 return GIU_IRQ(i
+ GIUINT_HIGH_OFFSET
);
224 printk(KERN_ERR
"spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
225 maskl
, pendl
, maskh
, pendh
);
227 atomic_inc(&irq_err_count
);
232 void vr41xx_set_irq_trigger(unsigned int pin
, irq_trigger_t trigger
,
237 if (pin
< GIUINT_HIGH_OFFSET
) {
239 if (trigger
!= IRQ_TRIGGER_LEVEL
) {
240 giu_set(GIUINTTYPL
, mask
);
241 if (signal
== IRQ_SIGNAL_HOLD
)
242 giu_set(GIUINTHTSELL
, mask
);
244 giu_clear(GIUINTHTSELL
, mask
);
245 if (giu_flags
& GPIO_HAS_INTERRUPT_EDGE_SELECT
) {
247 case IRQ_TRIGGER_EDGE_FALLING
:
248 giu_set(GIUFEDGEINHL
, mask
);
249 giu_clear(GIUREDGEINHL
, mask
);
251 case IRQ_TRIGGER_EDGE_RISING
:
252 giu_clear(GIUFEDGEINHL
, mask
);
253 giu_set(GIUREDGEINHL
, mask
);
256 giu_set(GIUFEDGEINHL
, mask
);
257 giu_set(GIUREDGEINHL
, mask
);
261 irq_set_chip_and_handler(GIU_IRQ(pin
),
262 &giuint_low_irq_chip
,
265 giu_clear(GIUINTTYPL
, mask
);
266 giu_clear(GIUINTHTSELL
, mask
);
267 irq_set_chip_and_handler(GIU_IRQ(pin
),
268 &giuint_low_irq_chip
,
271 giu_write(GIUINTSTATL
, mask
);
272 } else if (pin
< GIUINT_HIGH_MAX
) {
273 mask
= 1 << (pin
- GIUINT_HIGH_OFFSET
);
274 if (trigger
!= IRQ_TRIGGER_LEVEL
) {
275 giu_set(GIUINTTYPH
, mask
);
276 if (signal
== IRQ_SIGNAL_HOLD
)
277 giu_set(GIUINTHTSELH
, mask
);
279 giu_clear(GIUINTHTSELH
, mask
);
280 if (giu_flags
& GPIO_HAS_INTERRUPT_EDGE_SELECT
) {
282 case IRQ_TRIGGER_EDGE_FALLING
:
283 giu_set(GIUFEDGEINHH
, mask
);
284 giu_clear(GIUREDGEINHH
, mask
);
286 case IRQ_TRIGGER_EDGE_RISING
:
287 giu_clear(GIUFEDGEINHH
, mask
);
288 giu_set(GIUREDGEINHH
, mask
);
291 giu_set(GIUFEDGEINHH
, mask
);
292 giu_set(GIUREDGEINHH
, mask
);
296 irq_set_chip_and_handler(GIU_IRQ(pin
),
297 &giuint_high_irq_chip
,
300 giu_clear(GIUINTTYPH
, mask
);
301 giu_clear(GIUINTHTSELH
, mask
);
302 irq_set_chip_and_handler(GIU_IRQ(pin
),
303 &giuint_high_irq_chip
,
306 giu_write(GIUINTSTATH
, mask
);
309 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger
);
311 void vr41xx_set_irq_level(unsigned int pin
, irq_level_t level
)
315 if (pin
< GIUINT_HIGH_OFFSET
) {
317 if (level
== IRQ_LEVEL_HIGH
)
318 giu_set(GIUINTALSELL
, mask
);
320 giu_clear(GIUINTALSELL
, mask
);
321 giu_write(GIUINTSTATL
, mask
);
322 } else if (pin
< GIUINT_HIGH_MAX
) {
323 mask
= 1 << (pin
- GIUINT_HIGH_OFFSET
);
324 if (level
== IRQ_LEVEL_HIGH
)
325 giu_set(GIUINTALSELH
, mask
);
327 giu_clear(GIUINTALSELH
, mask
);
328 giu_write(GIUINTSTATH
, mask
);
331 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level
);
333 static int giu_set_direction(struct gpio_chip
*chip
, unsigned pin
, int dir
)
335 u16 offset
, mask
, reg
;
338 if (pin
>= chip
->ngpio
)
344 } else if (pin
< 32) {
346 mask
= 1 << (pin
- 16);
348 if (giu_flags
& GPIO_HAS_OUTPUT_ENABLE
) {
350 mask
= 1 << (pin
- 32);
367 spin_lock_irqsave(&giu_lock
, flags
);
369 reg
= giu_read(offset
);
370 if (dir
== GPIO_OUTPUT
)
374 giu_write(offset
, reg
);
376 spin_unlock_irqrestore(&giu_lock
, flags
);
381 int vr41xx_gpio_pullupdown(unsigned int pin
, gpio_pull_t pull
)
386 if ((giu_flags
& GPIO_HAS_PULLUPDOWN_IO
) != GPIO_HAS_PULLUPDOWN_IO
)
394 spin_lock_irqsave(&giu_lock
, flags
);
396 if (pull
== GPIO_PULL_UP
|| pull
== GPIO_PULL_DOWN
) {
397 reg
= giu_read(GIUTERMUPDN
);
398 if (pull
== GPIO_PULL_UP
)
402 giu_write(GIUTERMUPDN
, reg
);
404 reg
= giu_read(GIUUSEUPDN
);
406 giu_write(GIUUSEUPDN
, reg
);
408 reg
= giu_read(GIUUSEUPDN
);
410 giu_write(GIUUSEUPDN
, reg
);
413 spin_unlock_irqrestore(&giu_lock
, flags
);
417 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown
);
419 static int vr41xx_gpio_get(struct gpio_chip
*chip
, unsigned pin
)
423 if (pin
>= chip
->ngpio
)
427 reg
= giu_read(GIUPIODL
);
429 } else if (pin
< 32) {
430 reg
= giu_read(GIUPIODH
);
431 mask
= 1 << (pin
- 16);
432 } else if (pin
< 48) {
433 reg
= giu_read(GIUPODATL
);
434 mask
= 1 << (pin
- 32);
436 reg
= giu_read(GIUPODATH
);
437 mask
= 1 << (pin
- 48);
446 static void vr41xx_gpio_set(struct gpio_chip
*chip
, unsigned pin
,
449 u16 offset
, mask
, reg
;
452 if (pin
>= chip
->ngpio
)
458 } else if (pin
< 32) {
460 mask
= 1 << (pin
- 16);
461 } else if (pin
< 48) {
463 mask
= 1 << (pin
- 32);
466 mask
= 1 << (pin
- 48);
469 spin_lock_irqsave(&giu_lock
, flags
);
471 reg
= giu_read(offset
);
476 giu_write(offset
, reg
);
478 spin_unlock_irqrestore(&giu_lock
, flags
);
482 static int vr41xx_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
484 return giu_set_direction(chip
, offset
, GPIO_INPUT
);
487 static int vr41xx_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
490 vr41xx_gpio_set(chip
, offset
, value
);
492 return giu_set_direction(chip
, offset
, GPIO_OUTPUT
);
495 static int vr41xx_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
497 if (offset
>= chip
->ngpio
)
500 return GIU_IRQ_BASE
+ offset
;
503 static struct gpio_chip vr41xx_gpio_chip
= {
505 .owner
= THIS_MODULE
,
506 .direction_input
= vr41xx_gpio_direction_input
,
507 .get
= vr41xx_gpio_get
,
508 .direction_output
= vr41xx_gpio_direction_output
,
509 .set
= vr41xx_gpio_set
,
510 .to_irq
= vr41xx_gpio_to_irq
,
513 static int giu_probe(struct platform_device
*pdev
)
515 struct resource
*res
;
516 unsigned int trigger
, i
, pin
;
517 struct irq_chip
*chip
;
521 case GPIO_50PINS_PULLUPDOWN
:
522 giu_flags
= GPIO_HAS_PULLUPDOWN_IO
;
523 vr41xx_gpio_chip
.ngpio
= 50;
526 vr41xx_gpio_chip
.ngpio
= 36;
528 case GPIO_48PINS_EDGE_SELECT
:
529 giu_flags
= GPIO_HAS_INTERRUPT_EDGE_SELECT
;
530 vr41xx_gpio_chip
.ngpio
= 48;
533 dev_err(&pdev
->dev
, "GIU: unknown ID %d\n", pdev
->id
);
537 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
541 giu_base
= ioremap(res
->start
, resource_size(res
));
545 vr41xx_gpio_chip
.parent
= &pdev
->dev
;
547 ret
= gpiochip_add_data(&vr41xx_gpio_chip
, NULL
);
553 giu_write(GIUINTENL
, 0);
554 giu_write(GIUINTENH
, 0);
556 trigger
= giu_read(GIUINTTYPH
) << 16;
557 trigger
|= giu_read(GIUINTTYPL
);
558 for (i
= GIU_IRQ_BASE
; i
<= GIU_IRQ_LAST
; i
++) {
559 pin
= GPIO_PIN_OF_IRQ(i
);
560 if (pin
< GIUINT_HIGH_OFFSET
)
561 chip
= &giuint_low_irq_chip
;
563 chip
= &giuint_high_irq_chip
;
565 if (trigger
& (1 << pin
))
566 irq_set_chip_and_handler(i
, chip
, handle_edge_irq
);
568 irq_set_chip_and_handler(i
, chip
, handle_level_irq
);
572 irq
= platform_get_irq(pdev
, 0);
573 if (irq
< 0 || irq
>= nr_irqs
)
576 return cascade_irq(irq
, giu_get_irq
);
579 static int giu_remove(struct platform_device
*pdev
)
589 static struct platform_driver giu_device_driver
= {
591 .remove
= giu_remove
,
597 module_platform_driver(giu_device_driver
);