| blob | 7980873525b264c5b8fe327387483d241662f3a1 |
1 config ARM
2 bool
3 default y
4 select ARCH_HAVE_CUSTOM_GPIO_H
5 select HAVE_AOUT
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_ATTRS
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
10 select HAVE_MEMBLOCK
11 select RTC_LIB
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_KGDB
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
30 select HAVE_KERNEL_XZ
31 select HAVE_IRQ_WORK
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_PROBE
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select HARDIRQS_SW_RESEND
44 select CPU_PM if (SUSPEND || CPU_IDLE)
45 select GENERIC_PCI_IOMAP
46 select HAVE_BPF_JIT
47 select GENERIC_SMP_IDLE_THREAD
48 select KTIME_SCALAR
49 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 help
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
62 bool
64 config NEED_SG_DMA_LENGTH
65 bool
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
70 bool
72 config HAVE_PWM
73 bool
75 config MIGHT_HAVE_PCI
76 bool
78 config SYS_SUPPORTS_APM_EMULATION
79 bool
81 config GENERIC_GPIO
82 bool
84 config HAVE_TCM
85 bool
86 select GENERIC_ALLOCATOR
88 config HAVE_PROC_CPU
89 bool
91 config NO_IOPORT
92 bool
94 config EISA
95 bool
96 ---help---
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
107 Otherwise, say N.
109 config SBUS
110 bool
112 config STACKTRACE_SUPPORT
113 bool
114 default y
116 config HAVE_LATENCYTOP_SUPPORT
117 bool
118 depends on !SMP
119 default y
121 config LOCKDEP_SUPPORT
122 bool
123 default y
125 config TRACE_IRQFLAGS_SUPPORT
126 bool
127 default y
129 config GENERIC_LOCKBREAK
130 bool
131 default y
132 depends on SMP && PREEMPT
134 config RWSEM_GENERIC_SPINLOCK
135 bool
136 default y
138 config RWSEM_XCHGADD_ALGORITHM
139 bool
141 config ARCH_HAS_ILOG2_U32
142 bool
144 config ARCH_HAS_ILOG2_U64
145 bool
147 config ARCH_HAS_CPUFREQ
148 bool
149 help
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
152 it.
154 config GENERIC_HWEIGHT
155 bool
156 default y
158 config GENERIC_CALIBRATE_DELAY
159 bool
160 default y
162 config ARCH_MAY_HAVE_PC_FDC
163 bool
165 config ZONE_DMA
166 bool
168 config NEED_DMA_MAP_STATE
169 def_bool y
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
172 bool
174 config GENERIC_ISA_DMA
175 bool
177 config FIQ
178 bool
180 config NEED_RET_TO_USER
181 bool
183 config ARCH_MTD_XIP
184 bool
186 config VECTORS_BASE
187 hex
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
190 default 0x00000000
191 help
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
196 default y
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
199 help
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_IO_H
212 bool
213 help
214 Select this when mach/io.h is required to provide special
215 definitions for this platform. The need for mach/io.h should
216 be avoided when possible.
218 config NEED_MACH_MEMORY_H
219 bool
220 help
221 Select this when mach/memory.h is required to provide special
222 definitions for this platform. The need for mach/memory.h should
223 be avoided when possible.
225 config PHYS_OFFSET
226 hex "Physical address of main memory" if MMU
227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
228 default DRAM_BASE if !MMU
229 help
230 Please provide the physical address corresponding to the
231 location of main memory in your system.
233 config GENERIC_BUG
234 def_bool y
235 depends on BUG
237 source "init/Kconfig"
239 source "kernel/Kconfig.freezer"
241 menu "System Type"
243 config MMU
244 bool "MMU-based Paged Memory Management Support"
245 default y
246 help
247 Select if you want MMU-based virtualised addressing space
248 support by paged memory management. If unsure, say 'Y'.
250 #
251 # The "ARM system type" choice list is ordered alphabetically by option
252 # text. Please add new entries in the option alphabetic order.
253 #
254 choice
255 prompt "ARM system type"
256 default ARCH_VERSATILE
258 config ARCH_SOCFPGA
259 bool "Altera SOCFPGA family"
260 select ARCH_WANT_OPTIONAL_GPIOLIB
261 select ARM_AMBA
262 select ARM_GIC
263 select CACHE_L2X0
264 select CLKDEV_LOOKUP
265 select COMMON_CLK
266 select CPU_V7
267 select DW_APB_TIMER
268 select DW_APB_TIMER_OF
269 select GENERIC_CLOCKEVENTS
270 select GPIO_PL061 if GPIOLIB
271 select HAVE_ARM_SCU
272 select SPARSE_IRQ
273 select USE_OF
274 help
275 This enables support for Altera SOCFPGA Cyclone V platform
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
279 select ARM_AMBA
280 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK
282 select CLK_VERSATILE
283 select HAVE_TCM
284 select ICST
285 select GENERIC_CLOCKEVENTS
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
288 select NEED_MACH_IO_H
289 select NEED_MACH_MEMORY_H
290 select SPARSE_IRQ
291 select MULTI_IRQ_HANDLER
292 help
293 Support for ARM's Integrator platform.
295 config ARCH_REALVIEW
296 bool "ARM Ltd. RealView family"
297 select ARM_AMBA
298 select CLKDEV_LOOKUP
299 select HAVE_MACH_CLKDEV
300 select ICST
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLOCK
305 select PLAT_VERSATILE_CLCD
306 select ARM_TIMER_SP804
307 select GPIO_PL061 if GPIOLIB
308 select NEED_MACH_MEMORY_H
309 help
310 This enables support for ARM Ltd RealView boards.
312 config ARCH_VERSATILE
313 bool "ARM Ltd. Versatile family"
314 select ARM_AMBA
315 select ARM_VIC
316 select CLKDEV_LOOKUP
317 select HAVE_MACH_CLKDEV
318 select ICST
319 select GENERIC_CLOCKEVENTS
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select NEED_MACH_IO_H if PCI
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLOCK
324 select PLAT_VERSATILE_CLCD
325 select PLAT_VERSATILE_FPGA_IRQ
326 select ARM_TIMER_SP804
327 help
328 This enables support for ARM Ltd Versatile board.
330 config ARCH_VEXPRESS
331 bool "ARM Ltd. Versatile Express family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_AMBA
334 select ARM_TIMER_SP804
335 select CLKDEV_LOOKUP
336 select COMMON_CLK
337 select GENERIC_CLOCKEVENTS
338 select HAVE_CLK
339 select HAVE_PATA_PLATFORM
340 select ICST
341 select NO_IOPORT
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
344 select REGULATOR_FIXED_VOLTAGE if REGULATOR
345 help
346 This enables support for the ARM Ltd Versatile Express boards.
348 config ARCH_AT91
349 bool "Atmel AT91"
350 select ARCH_REQUIRE_GPIOLIB
351 select HAVE_CLK
352 select CLKDEV_LOOKUP
353 select IRQ_DOMAIN
354 select NEED_MACH_IO_H if PCCARD
355 help
356 This enables support for systems based on Atmel
357 AT91RM9200 and AT91SAM9* processors.
359 config ARCH_BCMRING
360 bool "Broadcom BCMRING"
361 depends on MMU
362 select CPU_V6
363 select ARM_AMBA
364 select ARM_TIMER_SP804
365 select CLKDEV_LOOKUP
366 select GENERIC_CLOCKEVENTS
367 select ARCH_WANT_OPTIONAL_GPIOLIB
368 help
369 Support for Broadcom's BCMRing platform.
371 config ARCH_HIGHBANK
372 bool "Calxeda Highbank-based"
373 select ARCH_WANT_OPTIONAL_GPIOLIB
374 select ARM_AMBA
375 select ARM_GIC
376 select ARM_TIMER_SP804
377 select CACHE_L2X0
378 select CLKDEV_LOOKUP
379 select COMMON_CLK
380 select CPU_V7
381 select GENERIC_CLOCKEVENTS
382 select HAVE_ARM_SCU
383 select HAVE_SMP
384 select SPARSE_IRQ
385 select USE_OF
386 help
387 Support for the Calxeda Highbank SoC based boards.
389 config ARCH_CLPS711X
390 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
391 select CPU_ARM720T
392 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_MEMORY_H
394 help
395 Support for Cirrus Logic 711x/721x/731x based boards.
397 config ARCH_CNS3XXX
398 bool "Cavium Networks CNS3XXX family"
399 select CPU_V6K
400 select GENERIC_CLOCKEVENTS
401 select ARM_GIC
402 select MIGHT_HAVE_CACHE_L2X0
403 select MIGHT_HAVE_PCI
404 select PCI_DOMAINS if PCI
405 help
406 Support for Cavium Networks CNS3XXX platform.
408 config ARCH_GEMINI
409 bool "Cortina Systems Gemini"
410 select CPU_FA526
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
413 help
414 Support for the Cortina Systems Gemini family SoCs
416 config ARCH_PRIMA2
417 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
418 select CPU_V7
419 select NO_IOPORT
420 select ARCH_REQUIRE_GPIOLIB
421 select GENERIC_CLOCKEVENTS
422 select CLKDEV_LOOKUP
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
425 select PINCTRL
426 select PINCTRL_SIRF
427 select USE_OF
428 select ZONE_DMA
429 help
430 Support for CSR SiRFSoC ARM Cortex A9 Platform
432 config ARCH_EBSA110
433 bool "EBSA-110"
434 select CPU_SA110
435 select ISA
436 select NO_IOPORT
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
440 help
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
444 parallel port.
446 config ARCH_EP93XX
447 bool "EP93xx-based"
448 select CPU_ARM920T
449 select ARM_AMBA
450 select ARM_VIC
451 select CLKDEV_LOOKUP
452 select ARCH_REQUIRE_GPIOLIB
453 select ARCH_HAS_HOLES_MEMORYMODEL
454 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
456 help
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
460 bool "FootBridge"
461 select CPU_SA110
462 select FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
464 select HAVE_IDE
465 select NEED_MACH_IO_H
466 select NEED_MACH_MEMORY_H
467 help
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
471 config ARCH_MXC
472 bool "Freescale MXC/iMX-based"
473 select GENERIC_CLOCKEVENTS
474 select ARCH_REQUIRE_GPIOLIB
475 select CLKDEV_LOOKUP
476 select CLKSRC_MMIO
477 select GENERIC_IRQ_CHIP
478 select MULTI_IRQ_HANDLER
479 select SPARSE_IRQ
480 select USE_OF
481 help
482 Support for Freescale MXC/iMX-based family of processors
484 config ARCH_MXS
485 bool "Freescale MXS-based"
486 select GENERIC_CLOCKEVENTS
487 select ARCH_REQUIRE_GPIOLIB
488 select CLKDEV_LOOKUP
489 select CLKSRC_MMIO
490 select COMMON_CLK
491 select HAVE_CLK_PREPARE
492 select PINCTRL
493 select USE_OF
494 help
495 Support for Freescale MXS-based family of processors
497 config ARCH_NETX
498 bool "Hilscher NetX based"
499 select CLKSRC_MMIO
500 select CPU_ARM926T
501 select ARM_VIC
502 select GENERIC_CLOCKEVENTS
503 help
504 This enables support for systems based on the Hilscher NetX Soc
506 config ARCH_H720X
507 bool "Hynix HMS720x-based"
508 select CPU_ARM720T
509 select ISA_DMA_API
510 select ARCH_USES_GETTIMEOFFSET
511 help
512 This enables support for systems based on the Hynix HMS720x
514 config ARCH_IOP13XX
515 bool "IOP13xx-based"
516 depends on MMU
517 select CPU_XSC3
518 select PLAT_IOP
519 select PCI
520 select ARCH_SUPPORTS_MSI
521 select VMSPLIT_1G
522 select NEED_MACH_IO_H
523 select NEED_MACH_MEMORY_H
524 select NEED_RET_TO_USER
525 help
526 Support for Intel's IOP13XX (XScale) family of processors.
528 config ARCH_IOP32X
529 bool "IOP32x-based"
530 depends on MMU
531 select CPU_XSCALE
532 select NEED_MACH_IO_H
533 select NEED_RET_TO_USER
534 select PLAT_IOP
535 select PCI
536 select ARCH_REQUIRE_GPIOLIB
537 help
538 Support for Intel's 80219 and IOP32X (XScale) family of
539 processors.
541 config ARCH_IOP33X
542 bool "IOP33x-based"
543 depends on MMU
544 select CPU_XSCALE
545 select NEED_MACH_IO_H
546 select NEED_RET_TO_USER
547 select PLAT_IOP
548 select PCI
549 select ARCH_REQUIRE_GPIOLIB
550 help
551 Support for Intel's IOP33X (XScale) family of processors.
553 config ARCH_IXP4XX
554 bool "IXP4xx-based"
555 depends on MMU
556 select ARCH_HAS_DMA_SET_COHERENT_MASK
557 select CLKSRC_MMIO
558 select CPU_XSCALE
559 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
562 select NEED_MACH_IO_H
563 select DMABOUNCE if PCI
564 help
565 Support for Intel's IXP4XX (XScale) family of processors.
567 config ARCH_MVEBU
568 bool "Marvell SOCs with Device Tree support"
569 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
571 select SPARSE_IRQ
572 select CLKSRC_MMIO
573 select GENERIC_IRQ_CHIP
574 select IRQ_DOMAIN
575 select COMMON_CLK
576 help
577 Support for the Marvell SoC Family with device tree support
579 config ARCH_DOVE
580 bool "Marvell Dove"
581 select CPU_V7
582 select PCI
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_IO_H
586 select PLAT_ORION
587 help
588 Support for the Marvell Dove SoC 88AP510
590 config ARCH_KIRKWOOD
591 bool "Marvell Kirkwood"
592 select CPU_FEROCEON
593 select PCI
594 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select NEED_MACH_IO_H
597 select PLAT_ORION
598 help
599 Support for the following Marvell Kirkwood series SoCs:
600 88F6180, 88F6192 and 88F6281.
602 config ARCH_LPC32XX
603 bool "NXP LPC32XX"
604 select CLKSRC_MMIO
605 select CPU_ARM926T
606 select ARCH_REQUIRE_GPIOLIB
607 select HAVE_IDE
608 select ARM_AMBA
609 select USB_ARCH_HAS_OHCI
610 select CLKDEV_LOOKUP
611 select GENERIC_CLOCKEVENTS
612 select USE_OF
613 select HAVE_PWM
614 help
615 Support for the NXP LPC32XX family of processors
617 config ARCH_MV78XX0
618 bool "Marvell MV78xx0"
619 select CPU_FEROCEON
620 select PCI
621 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
623 select NEED_MACH_IO_H
624 select PLAT_ORION
625 help
626 Support for the following Marvell MV78xx0 series SoCs:
627 MV781x0, MV782x0.
629 config ARCH_ORION5X
630 bool "Marvell Orion"
631 depends on MMU
632 select CPU_FEROCEON
633 select PCI
634 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
636 select NEED_MACH_IO_H
637 select PLAT_ORION
638 help
639 Support for the following Marvell Orion 5x series SoCs:
640 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
641 Orion-2 (5281), Orion-1-90 (6183).
643 config ARCH_MMP
644 bool "Marvell PXA168/910/MMP2"
645 depends on MMU
646 select ARCH_REQUIRE_GPIOLIB
647 select CLKDEV_LOOKUP
648 select GENERIC_CLOCKEVENTS
649 select GPIO_PXA
650 select IRQ_DOMAIN
651 select PLAT_PXA
652 select SPARSE_IRQ
653 select GENERIC_ALLOCATOR
654 help
655 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
657 config ARCH_KS8695
658 bool "Micrel/Kendin KS8695"
659 select CPU_ARM922T
660 select ARCH_REQUIRE_GPIOLIB
661 select ARCH_USES_GETTIMEOFFSET
662 select NEED_MACH_MEMORY_H
663 help
664 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
665 System-on-Chip devices.
667 config ARCH_W90X900
668 bool "Nuvoton W90X900 CPU"
669 select CPU_ARM926T
670 select ARCH_REQUIRE_GPIOLIB
671 select CLKDEV_LOOKUP
672 select CLKSRC_MMIO
673 select GENERIC_CLOCKEVENTS
674 help
675 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
676 At present, the w90x900 has been renamed nuc900, regarding
677 the ARM series product line, you can login the following
678 link address to know more.
680 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
681 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
683 config ARCH_TEGRA
684 bool "NVIDIA Tegra"
685 select CLKDEV_LOOKUP
686 select CLKSRC_MMIO
687 select GENERIC_CLOCKEVENTS
688 select GENERIC_GPIO
689 select HAVE_CLK
690 select HAVE_SMP
691 select MIGHT_HAVE_CACHE_L2X0
692 select NEED_MACH_IO_H if PCI
693 select ARCH_HAS_CPUFREQ
694 select USE_OF
695 help
696 This enables support for NVIDIA Tegra based systems (Tegra APX,
697 Tegra 6xx and Tegra 2 series).
699 config ARCH_PICOXCELL
700 bool "Picochip picoXcell"
701 select ARCH_REQUIRE_GPIOLIB
702 select ARM_PATCH_PHYS_VIRT
703 select ARM_VIC
704 select CPU_V6K
705 select DW_APB_TIMER
706 select DW_APB_TIMER_OF
707 select GENERIC_CLOCKEVENTS
708 select GENERIC_GPIO
709 select HAVE_TCM
710 select NO_IOPORT
711 select SPARSE_IRQ
712 select USE_OF
713 help
714 This enables support for systems based on the Picochip picoXcell
715 family of Femtocell devices. The picoxcell support requires device tree
716 for all boards.
718 config ARCH_PNX4008
719 bool "Philips Nexperia PNX4008 Mobile"
720 select CPU_ARM926T
721 select CLKDEV_LOOKUP
722 select ARCH_USES_GETTIMEOFFSET
723 help
724 This enables support for Philips PNX4008 mobile platform.
726 config ARCH_PXA
727 bool "PXA2xx/PXA3xx-based"
728 depends on MMU
729 select ARCH_MTD_XIP
730 select ARCH_HAS_CPUFREQ
731 select CLKDEV_LOOKUP
732 select CLKSRC_MMIO
733 select ARCH_REQUIRE_GPIOLIB
734 select GENERIC_CLOCKEVENTS
735 select GPIO_PXA
736 select PLAT_PXA
737 select SPARSE_IRQ
738 select AUTO_ZRELADDR
739 select MULTI_IRQ_HANDLER
740 select ARM_CPU_SUSPEND if PM
741 select HAVE_IDE
742 help
743 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
745 config ARCH_MSM
746 bool "Qualcomm MSM"
747 select HAVE_CLK
748 select GENERIC_CLOCKEVENTS
749 select ARCH_REQUIRE_GPIOLIB
750 select CLKDEV_LOOKUP
751 help
752 Support for Qualcomm MSM/QSD based systems. This runs on the
753 apps processor of the MSM/QSD and depends on a shared memory
754 interface to the modem processor which runs the baseband
755 stack and controls some vital subsystems
756 (clock and power control, etc).
758 config ARCH_SHMOBILE
759 bool "Renesas SH-Mobile / R-Mobile"
760 select HAVE_CLK
761 select CLKDEV_LOOKUP
762 select HAVE_MACH_CLKDEV
763 select HAVE_SMP
764 select GENERIC_CLOCKEVENTS
765 select MIGHT_HAVE_CACHE_L2X0
766 select NO_IOPORT
767 select SPARSE_IRQ
768 select MULTI_IRQ_HANDLER
769 select PM_GENERIC_DOMAINS if PM
770 select NEED_MACH_MEMORY_H
771 help
772 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
774 config ARCH_RPC
775 bool "RiscPC"
776 select ARCH_ACORN
777 select FIQ
778 select ARCH_MAY_HAVE_PC_FDC
779 select HAVE_PATA_PLATFORM
780 select ISA_DMA_API
781 select NO_IOPORT
782 select ARCH_SPARSEMEM_ENABLE
783 select ARCH_USES_GETTIMEOFFSET
784 select HAVE_IDE
785 select NEED_MACH_IO_H
786 select NEED_MACH_MEMORY_H
787 help
788 On the Acorn Risc-PC, Linux can support the internal IDE disk and
789 CD-ROM interface, serial and parallel port, and the floppy drive.
791 config ARCH_SA1100
792 bool "SA1100-based"
793 select CLKSRC_MMIO
794 select CPU_SA1100
795 select ISA
796 select ARCH_SPARSEMEM_ENABLE
797 select ARCH_MTD_XIP
798 select ARCH_HAS_CPUFREQ
799 select CPU_FREQ
800 select GENERIC_CLOCKEVENTS
801 select CLKDEV_LOOKUP
802 select ARCH_REQUIRE_GPIOLIB
803 select HAVE_IDE
804 select NEED_MACH_MEMORY_H
805 select SPARSE_IRQ
806 help
807 Support for StrongARM 11x0 based boards.
809 config ARCH_S3C24XX
810 bool "Samsung S3C24XX SoCs"
811 select GENERIC_GPIO
812 select ARCH_HAS_CPUFREQ
813 select HAVE_CLK
814 select CLKDEV_LOOKUP
815 select ARCH_USES_GETTIMEOFFSET
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 select NEED_MACH_IO_H
820 help
821 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
822 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
823 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
824 Samsung SMDK2410 development board (and derivatives).
826 config ARCH_S3C64XX
827 bool "Samsung S3C64XX"
828 select PLAT_SAMSUNG
829 select CPU_V6
830 select ARM_VIC
831 select HAVE_CLK
832 select HAVE_TCM
833 select CLKDEV_LOOKUP
834 select NO_IOPORT
835 select ARCH_USES_GETTIMEOFFSET
836 select ARCH_HAS_CPUFREQ
837 select ARCH_REQUIRE_GPIOLIB
838 select SAMSUNG_CLKSRC
839 select SAMSUNG_IRQ_VIC_TIMER
840 select S3C_GPIO_TRACK
841 select S3C_DEV_NAND
842 select USB_ARCH_HAS_OHCI
843 select SAMSUNG_GPIOLIB_4BIT
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C2410_WATCHDOG if WATCHDOG
846 help
847 Samsung S3C64XX series based systems
849 config ARCH_S5P64X0
850 bool "Samsung S5P6440 S5P6450"
851 select CPU_V6
852 select GENERIC_GPIO
853 select HAVE_CLK
854 select CLKDEV_LOOKUP
855 select CLKSRC_MMIO
856 select HAVE_S3C2410_WATCHDOG if WATCHDOG
857 select GENERIC_CLOCKEVENTS
858 select HAVE_S3C2410_I2C if I2C
859 select HAVE_S3C_RTC if RTC_CLASS
860 help
861 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
862 SMDK6450.
864 config ARCH_S5PC100
865 bool "Samsung S5PC100"
866 select GENERIC_GPIO
867 select HAVE_CLK
868 select CLKDEV_LOOKUP
869 select CPU_V7
870 select ARCH_USES_GETTIMEOFFSET
871 select HAVE_S3C2410_I2C if I2C
872 select HAVE_S3C_RTC if RTC_CLASS
873 select HAVE_S3C2410_WATCHDOG if WATCHDOG
874 help
875 Samsung S5PC100 series based systems
877 config ARCH_S5PV210
878 bool "Samsung S5PV210/S5PC110"
879 select CPU_V7
880 select ARCH_SPARSEMEM_ENABLE
881 select ARCH_HAS_HOLES_MEMORYMODEL
882 select GENERIC_GPIO
883 select HAVE_CLK
884 select CLKDEV_LOOKUP
885 select CLKSRC_MMIO
886 select ARCH_HAS_CPUFREQ
887 select GENERIC_CLOCKEVENTS
888 select HAVE_S3C2410_I2C if I2C
889 select HAVE_S3C_RTC if RTC_CLASS
890 select HAVE_S3C2410_WATCHDOG if WATCHDOG
891 select NEED_MACH_MEMORY_H
892 help
893 Samsung S5PV210/S5PC110 series based systems
895 config ARCH_EXYNOS
896 bool "SAMSUNG EXYNOS"
897 select CPU_V7
898 select ARCH_SPARSEMEM_ENABLE
899 select ARCH_HAS_HOLES_MEMORYMODEL
900 select GENERIC_GPIO
901 select HAVE_CLK
902 select CLKDEV_LOOKUP
903 select ARCH_HAS_CPUFREQ
904 select GENERIC_CLOCKEVENTS
905 select HAVE_S3C_RTC if RTC_CLASS
906 select HAVE_S3C2410_I2C if I2C
907 select HAVE_S3C2410_WATCHDOG if WATCHDOG
908 select NEED_MACH_MEMORY_H
909 help
910 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
912 config ARCH_SHARK
913 bool "Shark"
914 select CPU_SA110
915 select ISA
916 select ISA_DMA
917 select ZONE_DMA
918 select PCI
919 select ARCH_USES_GETTIMEOFFSET
920 select NEED_MACH_MEMORY_H
921 select NEED_MACH_IO_H
922 help
923 Support for the StrongARM based Digital DNARD machine, also known
924 as "Shark" (<http://www.shark-linux.de/shark.html>).
926 config ARCH_U300
927 bool "ST-Ericsson U300 Series"
928 depends on MMU
929 select CLKSRC_MMIO
930 select CPU_ARM926T
931 select HAVE_TCM
932 select ARM_AMBA
933 select ARM_PATCH_PHYS_VIRT
934 select ARM_VIC
935 select GENERIC_CLOCKEVENTS
936 select CLKDEV_LOOKUP
937 select COMMON_CLK
938 select GENERIC_GPIO
939 select ARCH_REQUIRE_GPIOLIB
940 help
941 Support for ST-Ericsson U300 series mobile platforms.
943 config ARCH_U8500
944 bool "ST-Ericsson U8500 Series"
945 depends on MMU
946 select CPU_V7
947 select ARM_AMBA
948 select GENERIC_CLOCKEVENTS
949 select CLKDEV_LOOKUP
950 select ARCH_REQUIRE_GPIOLIB
951 select ARCH_HAS_CPUFREQ
952 select HAVE_SMP
953 select MIGHT_HAVE_CACHE_L2X0
954 help
955 Support for ST-Ericsson's Ux500 architecture
957 config ARCH_NOMADIK
958 bool "STMicroelectronics Nomadik"
959 select ARM_AMBA
960 select ARM_VIC
961 select CPU_ARM926T
962 select COMMON_CLK
963 select GENERIC_CLOCKEVENTS
964 select PINCTRL
965 select MIGHT_HAVE_CACHE_L2X0
966 select ARCH_REQUIRE_GPIOLIB
967 help
968 Support for the Nomadik platform by ST-Ericsson
970 config ARCH_DAVINCI
971 bool "TI DaVinci"
972 select GENERIC_CLOCKEVENTS
973 select ARCH_REQUIRE_GPIOLIB
974 select ZONE_DMA
975 select HAVE_IDE
976 select CLKDEV_LOOKUP
977 select GENERIC_ALLOCATOR
978 select GENERIC_IRQ_CHIP
979 select ARCH_HAS_HOLES_MEMORYMODEL
980 help
981 Support for TI's DaVinci platform.
983 config ARCH_OMAP
984 bool "TI OMAP"
985 depends on MMU
986 select HAVE_CLK
987 select ARCH_REQUIRE_GPIOLIB
988 select ARCH_HAS_CPUFREQ
989 select CLKSRC_MMIO
990 select GENERIC_CLOCKEVENTS
991 select ARCH_HAS_HOLES_MEMORYMODEL
992 help
993 Support for TI's OMAP platform (OMAP1/2/3/4).
995 config PLAT_SPEAR
996 bool "ST SPEAr"
997 select ARM_AMBA
998 select ARCH_REQUIRE_GPIOLIB
999 select CLKDEV_LOOKUP
1000 select COMMON_CLK
1001 select CLKSRC_MMIO
1002 select GENERIC_CLOCKEVENTS
1003 select HAVE_CLK
1004 help
1005 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1007 config ARCH_VT8500
1008 bool "VIA/WonderMedia 85xx"
1009 select CPU_ARM926T
1010 select GENERIC_GPIO
1011 select ARCH_HAS_CPUFREQ
1012 select GENERIC_CLOCKEVENTS
1013 select ARCH_REQUIRE_GPIOLIB
1014 help
1015 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1017 config ARCH_ZYNQ
1018 bool "Xilinx Zynq ARM Cortex A9 Platform"
1019 select CPU_V7
1020 select GENERIC_CLOCKEVENTS
1021 select CLKDEV_LOOKUP
1022 select ARM_GIC
1023 select ARM_AMBA
1024 select ICST
1025 select MIGHT_HAVE_CACHE_L2X0
1026 select USE_OF
1027 help
1028 Support for Xilinx Zynq ARM Cortex A9 Platform
1029 endchoice
1031 #
1032 # This is sorted alphabetically by mach-* pathname. However, plat-*
1033 # Kconfigs may be included either alphabetically (according to the
1034 # plat- suffix) or along side the corresponding mach-* source.
1035 #
1036 source "arch/arm/mach-mvebu/Kconfig"
1038 source "arch/arm/mach-at91/Kconfig"
1040 source "arch/arm/mach-bcmring/Kconfig"
1042 source "arch/arm/mach-clps711x/Kconfig"
1044 source "arch/arm/mach-cns3xxx/Kconfig"
1046 source "arch/arm/mach-davinci/Kconfig"
1048 source "arch/arm/mach-dove/Kconfig"
1050 source "arch/arm/mach-ep93xx/Kconfig"
1052 source "arch/arm/mach-footbridge/Kconfig"
1054 source "arch/arm/mach-gemini/Kconfig"
1056 source "arch/arm/mach-h720x/Kconfig"
1058 source "arch/arm/mach-integrator/Kconfig"
1060 source "arch/arm/mach-iop32x/Kconfig"
1062 source "arch/arm/mach-iop33x/Kconfig"
1064 source "arch/arm/mach-iop13xx/Kconfig"
1066 source "arch/arm/mach-ixp4xx/Kconfig"
1068 source "arch/arm/mach-kirkwood/Kconfig"
1070 source "arch/arm/mach-ks8695/Kconfig"
1072 source "arch/arm/mach-msm/Kconfig"
1074 source "arch/arm/mach-mv78xx0/Kconfig"
1076 source "arch/arm/plat-mxc/Kconfig"
1078 source "arch/arm/mach-mxs/Kconfig"
1080 source "arch/arm/mach-netx/Kconfig"
1082 source "arch/arm/mach-nomadik/Kconfig"
1083 source "arch/arm/plat-nomadik/Kconfig"
1085 source "arch/arm/plat-omap/Kconfig"
1087 source "arch/arm/mach-omap1/Kconfig"
1089 source "arch/arm/mach-omap2/Kconfig"
1091 source "arch/arm/mach-orion5x/Kconfig"
1093 source "arch/arm/mach-pxa/Kconfig"
1094 source "arch/arm/plat-pxa/Kconfig"
1096 source "arch/arm/mach-mmp/Kconfig"
1098 source "arch/arm/mach-realview/Kconfig"
1100 source "arch/arm/mach-sa1100/Kconfig"
1102 source "arch/arm/plat-samsung/Kconfig"
1103 source "arch/arm/plat-s3c24xx/Kconfig"
1105 source "arch/arm/plat-spear/Kconfig"
1107 source "arch/arm/mach-s3c24xx/Kconfig"
1108 if ARCH_S3C24XX
1109 source "arch/arm/mach-s3c2412/Kconfig"
1110 source "arch/arm/mach-s3c2440/Kconfig"
1111 endif
1113 if ARCH_S3C64XX
1114 source "arch/arm/mach-s3c64xx/Kconfig"
1115 endif
1117 source "arch/arm/mach-s5p64x0/Kconfig"
1119 source "arch/arm/mach-s5pc100/Kconfig"
1121 source "arch/arm/mach-s5pv210/Kconfig"
1123 source "arch/arm/mach-exynos/Kconfig"
1125 source "arch/arm/mach-shmobile/Kconfig"
1127 source "arch/arm/mach-tegra/Kconfig"
1129 source "arch/arm/mach-u300/Kconfig"
1131 source "arch/arm/mach-ux500/Kconfig"
1133 source "arch/arm/mach-versatile/Kconfig"
1135 source "arch/arm/mach-vexpress/Kconfig"
1136 source "arch/arm/plat-versatile/Kconfig"
1138 source "arch/arm/mach-vt8500/Kconfig"
1140 source "arch/arm/mach-w90x900/Kconfig"
1142 # Definitions to make life easier
1143 config ARCH_ACORN
1144 bool
1146 config PLAT_IOP
1147 bool
1148 select GENERIC_CLOCKEVENTS
1150 config PLAT_ORION
1151 bool
1152 select CLKSRC_MMIO
1153 select GENERIC_IRQ_CHIP
1154 select COMMON_CLK
1156 config PLAT_PXA
1157 bool
1159 config PLAT_VERSATILE
1160 bool
1162 config ARM_TIMER_SP804
1163 bool
1164 select CLKSRC_MMIO
1165 select HAVE_SCHED_CLOCK
1167 source arch/arm/mm/Kconfig
1169 config ARM_NR_BANKS
1170 int
1171 default 16 if ARCH_EP93XX
1172 default 8
1174 config IWMMXT
1175 bool "Enable iWMMXt support"
1176 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1177 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1178 help
1179 Enable support for iWMMXt context switching at run time if
1180 running on a CPU that supports it.
1182 config XSCALE_PMU
1183 bool
1184 depends on CPU_XSCALE
1185 default y
1187 config CPU_HAS_PMU
1188 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1189 (!ARCH_OMAP3 || OMAP3_EMU)
1190 default y
1191 bool
1193 config MULTI_IRQ_HANDLER
1194 bool
1195 help
1196 Allow each machine to specify it's own IRQ handler at run time.
1198 if !MMU
1199 source "arch/arm/Kconfig-nommu"
1200 endif
1202 config ARM_ERRATA_326103
1203 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1204 depends on CPU_V6
1205 help
1206 Executing a SWP instruction to read-only memory does not set bit 11
1207 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1208 treat the access as a read, preventing a COW from occurring and
1209 causing the faulting task to livelock.
1211 config ARM_ERRATA_411920
1212 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1213 depends on CPU_V6 || CPU_V6K
1214 help
1215 Invalidation of the Instruction Cache operation can
1216 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1217 It does not affect the MPCore. This option enables the ARM Ltd.
1218 recommended workaround.
1220 config ARM_ERRATA_430973
1221 bool "ARM errata: Stale prediction on replaced interworking branch"
1222 depends on CPU_V7
1223 help
1224 This option enables the workaround for the 430973 Cortex-A8
1225 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1226 interworking branch is replaced with another code sequence at the
1227 same virtual address, whether due to self-modifying code or virtual
1228 to physical address re-mapping, Cortex-A8 does not recover from the
1229 stale interworking branch prediction. This results in Cortex-A8
1230 executing the new code sequence in the incorrect ARM or Thumb state.
1231 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1232 and also flushes the branch target cache at every context switch.
1233 Note that setting specific bits in the ACTLR register may not be
1234 available in non-secure mode.
1236 config ARM_ERRATA_458693
1237 bool "ARM errata: Processor deadlock when a false hazard is created"
1238 depends on CPU_V7
1239 help
1240 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1241 erratum. For very specific sequences of memory operations, it is
1242 possible for a hazard condition intended for a cache line to instead
1243 be incorrectly associated with a different cache line. This false
1244 hazard might then cause a processor deadlock. The workaround enables
1245 the L1 caching of the NEON accesses and disables the PLD instruction
1246 in the ACTLR register. Note that setting specific bits in the ACTLR
1247 register may not be available in non-secure mode.
1249 config ARM_ERRATA_460075
1250 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1251 depends on CPU_V7
1252 help
1253 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1254 erratum. Any asynchronous access to the L2 cache may encounter a
1255 situation in which recent store transactions to the L2 cache are lost
1256 and overwritten with stale memory contents from external memory. The
1257 workaround disables the write-allocate mode for the L2 cache via the
1258 ACTLR register. Note that setting specific bits in the ACTLR register
1259 may not be available in non-secure mode.
1261 config ARM_ERRATA_742230
1262 bool "ARM errata: DMB operation may be faulty"
1263 depends on CPU_V7 && SMP
1264 help
1265 This option enables the workaround for the 742230 Cortex-A9
1266 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1267 between two write operations may not ensure the correct visibility
1268 ordering of the two writes. This workaround sets a specific bit in
1269 the diagnostic register of the Cortex-A9 which causes the DMB
1270 instruction to behave as a DSB, ensuring the correct behaviour of
1271 the two writes.
1273 config ARM_ERRATA_742231
1274 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1275 depends on CPU_V7 && SMP
1276 help
1277 This option enables the workaround for the 742231 Cortex-A9
1278 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1279 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1280 accessing some data located in the same cache line, may get corrupted
1281 data due to bad handling of the address hazard when the line gets
1282 replaced from one of the CPUs at the same time as another CPU is
1283 accessing it. This workaround sets specific bits in the diagnostic
1284 register of the Cortex-A9 which reduces the linefill issuing
1285 capabilities of the processor.
1287 config PL310_ERRATA_588369
1288 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1289 depends on CACHE_L2X0
1290 help
1291 The PL310 L2 cache controller implements three types of Clean &
1292 Invalidate maintenance operations: by Physical Address
1293 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1294 They are architecturally defined to behave as the execution of a
1295 clean operation followed immediately by an invalidate operation,
1296 both performing to the same memory location. This functionality
1297 is not correctly implemented in PL310 as clean lines are not
1298 invalidated as a result of these operations.
1300 config ARM_ERRATA_720789
1301 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1302 depends on CPU_V7
1303 help
1304 This option enables the workaround for the 720789 Cortex-A9 (prior to
1305 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1306 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1307 As a consequence of this erratum, some TLB entries which should be
1308 invalidated are not, resulting in an incoherency in the system page
1309 tables. The workaround changes the TLB flushing routines to invalidate
1310 entries regardless of the ASID.
1312 config PL310_ERRATA_727915
1313 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1314 depends on CACHE_L2X0
1315 help
1316 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1317 operation (offset 0x7FC). This operation runs in background so that
1318 PL310 can handle normal accesses while it is in progress. Under very
1319 rare circumstances, due to this erratum, write data can be lost when
1320 PL310 treats a cacheable write transaction during a Clean &
1321 Invalidate by Way operation.
1323 config ARM_ERRATA_743622
1324 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1325 depends on CPU_V7
1326 help
1327 This option enables the workaround for the 743622 Cortex-A9
1328 (r2p*) erratum. Under very rare conditions, a faulty
1329 optimisation in the Cortex-A9 Store Buffer may lead to data
1330 corruption. This workaround sets a specific bit in the diagnostic
1331 register of the Cortex-A9 which disables the Store Buffer
1332 optimisation, preventing the defect from occurring. This has no
1333 visible impact on the overall performance or power consumption of the
1334 processor.
1336 config ARM_ERRATA_751472
1337 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1338 depends on CPU_V7
1339 help
1340 This option enables the workaround for the 751472 Cortex-A9 (prior
1341 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1342 completion of a following broadcasted operation if the second
1343 operation is received by a CPU before the ICIALLUIS has completed,
1344 potentially leading to corrupted entries in the cache or TLB.
1346 config PL310_ERRATA_753970
1347 bool "PL310 errata: cache sync operation may be faulty"
1348 depends on CACHE_PL310
1349 help
1350 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1352 Under some condition the effect of cache sync operation on
1353 the store buffer still remains when the operation completes.
1354 This means that the store buffer is always asked to drain and
1355 this prevents it from merging any further writes. The workaround
1356 is to replace the normal offset of cache sync operation (0x730)
1357 by another offset targeting an unmapped PL310 register 0x740.
1358 This has the same effect as the cache sync operation: store buffer
1359 drain and waiting for all buffers empty.
1361 config ARM_ERRATA_754322
1362 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1363 depends on CPU_V7
1364 help
1365 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1366 r3p*) erratum. A speculative memory access may cause a page table walk
1367 which starts prior to an ASID switch but completes afterwards. This
1368 can populate the micro-TLB with a stale entry which may be hit with
1369 the new ASID. This workaround places two dsb instructions in the mm
1370 switching code so that no page table walks can cross the ASID switch.
1372 config ARM_ERRATA_754327
1373 bool "ARM errata: no automatic Store Buffer drain"
1374 depends on CPU_V7 && SMP
1375 help
1376 This option enables the workaround for the 754327 Cortex-A9 (prior to
1377 r2p0) erratum. The Store Buffer does not have any automatic draining
1378 mechanism and therefore a livelock may occur if an external agent
1379 continuously polls a memory location waiting to observe an update.
1380 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1381 written polling loops from denying visibility of updates to memory.
1383 config ARM_ERRATA_364296
1384 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1385 depends on CPU_V6 && !SMP
1386 help
1387 This options enables the workaround for the 364296 ARM1136
1388 r0p2 erratum (possible cache data corruption with
1389 hit-under-miss enabled). It sets the undocumented bit 31 in
1390 the auxiliary control register and the FI bit in the control
1391 register, thus disabling hit-under-miss without putting the
1392 processor into full low interrupt latency mode. ARM11MPCore
1393 is not affected.
1395 config ARM_ERRATA_764369
1396 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1397 depends on CPU_V7 && SMP
1398 help
1399 This option enables the workaround for erratum 764369
1400 affecting Cortex-A9 MPCore with two or more processors (all
1401 current revisions). Under certain timing circumstances, a data
1402 cache line maintenance operation by MVA targeting an Inner
1403 Shareable memory region may fail to proceed up to either the
1404 Point of Coherency or to the Point of Unification of the
1405 system. This workaround adds a DSB instruction before the
1406 relevant cache maintenance functions and sets a specific bit
1407 in the diagnostic control register of the SCU.
1409 config PL310_ERRATA_769419
1410 bool "PL310 errata: no automatic Store Buffer drain"
1411 depends on CACHE_L2X0
1412 help
1413 On revisions of the PL310 prior to r3p2, the Store Buffer does
1414 not automatically drain. This can cause normal, non-cacheable
1415 writes to be retained when the memory system is idle, leading
1416 to suboptimal I/O performance for drivers using coherent DMA.
1417 This option adds a write barrier to the cpu_idle loop so that,
1418 on systems with an outer cache, the store buffer is drained
1419 explicitly.
1421 endmenu
1423 source "arch/arm/common/Kconfig"
1425 menu "Bus support"
1427 config ARM_AMBA
1428 bool
1430 config ISA
1431 bool
1432 help
1433 Find out whether you have ISA slots on your motherboard. ISA is the
1434 name of a bus system, i.e. the way the CPU talks to the other stuff
1435 inside your box. Other bus systems are PCI, EISA, MicroChannel
1436 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1437 newer boards don't support it. If you have ISA, say Y, otherwise N.
1439 # Select ISA DMA controller support
1440 config ISA_DMA
1441 bool
1442 select ISA_DMA_API
1444 # Select ISA DMA interface
1445 config ISA_DMA_API
1446 bool
1448 config PCI
1449 bool "PCI support" if MIGHT_HAVE_PCI
1450 help
1451 Find out whether you have a PCI motherboard. PCI is the name of a
1452 bus system, i.e. the way the CPU talks to the other stuff inside
1453 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1454 VESA. If you have PCI, say Y, otherwise N.
1456 config PCI_DOMAINS
1457 bool
1458 depends on PCI
1460 config PCI_NANOENGINE
1461 bool "BSE nanoEngine PCI support"
1462 depends on SA1100_NANOENGINE
1463 help
1464 Enable PCI on the BSE nanoEngine board.
1466 config PCI_SYSCALL
1467 def_bool PCI
1469 # Select the host bridge type
1470 config PCI_HOST_VIA82C505
1471 bool
1472 depends on PCI && ARCH_SHARK
1473 default y
1475 config PCI_HOST_ITE8152
1476 bool
1477 depends on PCI && MACH_ARMCORE
1478 default y
1479 select DMABOUNCE
1481 source "drivers/pci/Kconfig"
1483 source "drivers/pcmcia/Kconfig"
1485 endmenu
1487 menu "Kernel Features"
1489 config HAVE_SMP
1490 bool
1491 help
1492 This option should be selected by machines which have an SMP-
1493 capable CPU.
1495 The only effect of this option is to make the SMP-related
1496 options available to the user for configuration.
1498 config SMP
1499 bool "Symmetric Multi-Processing"
1500 depends on CPU_V6K || CPU_V7
1501 depends on GENERIC_CLOCKEVENTS
1502 depends on HAVE_SMP
1503 depends on MMU
1504 select USE_GENERIC_SMP_HELPERS
1505 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1506 help
1507 This enables support for systems with more than one CPU. If you have
1508 a system with only one CPU, like most personal computers, say N. If
1509 you have a system with more than one CPU, say Y.
1511 If you say N here, the kernel will run on single and multiprocessor
1512 machines, but will use only one CPU of a multiprocessor machine. If
1513 you say Y here, the kernel will run on many, but not all, single
1514 processor machines. On a single processor machine, the kernel will
1515 run faster if you say N here.
1517 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1518 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1519 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1521 If you don't know what to do here, say N.
1523 config SMP_ON_UP
1524 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1525 depends on EXPERIMENTAL
1526 depends on SMP && !XIP_KERNEL
1527 default y
1528 help
1529 SMP kernels contain instructions which fail on non-SMP processors.
1530 Enabling this option allows the kernel to modify itself to make
1531 these instructions safe. Disabling it allows about 1K of space
1532 savings.
1534 If you don't know what to do here, say Y.
1536 config ARM_CPU_TOPOLOGY
1537 bool "Support cpu topology definition"
1538 depends on SMP && CPU_V7
1539 default y
1540 help
1541 Support ARM cpu topology definition. The MPIDR register defines
1542 affinity between processors which is then used to describe the cpu
1543 topology of an ARM System.
1545 config SCHED_MC
1546 bool "Multi-core scheduler support"
1547 depends on ARM_CPU_TOPOLOGY
1548 help
1549 Multi-core scheduler support improves the CPU scheduler's decision
1550 making when dealing with multi-core CPU chips at a cost of slightly
1551 increased overhead in some places. If unsure say N here.
1553 config SCHED_SMT
1554 bool "SMT scheduler support"
1555 depends on ARM_CPU_TOPOLOGY
1556 help
1557 Improves the CPU scheduler's decision making when dealing with
1558 MultiThreading at a cost of slightly increased overhead in some
1559 places. If unsure say N here.
1561 config HAVE_ARM_SCU
1562 bool
1563 help
1564 This option enables support for the ARM system coherency unit
1566 config ARM_ARCH_TIMER
1567 bool "Architected timer support"
1568 depends on CPU_V7
1569 help
1570 This option enables support for the ARM architected timer
1572 config HAVE_ARM_TWD
1573 bool
1574 depends on SMP
1575 help
1576 This options enables support for the ARM timer and watchdog unit
1578 choice
1579 prompt "Memory split"
1580 default VMSPLIT_3G
1581 help
1582 Select the desired split between kernel and user memory.
1584 If you are not absolutely sure what you are doing, leave this
1585 option alone!
1587 config VMSPLIT_3G
1588 bool "3G/1G user/kernel split"
1589 config VMSPLIT_2G
1590 bool "2G/2G user/kernel split"
1591 config VMSPLIT_1G
1592 bool "1G/3G user/kernel split"
1593 endchoice
1595 config PAGE_OFFSET
1596 hex
1597 default 0x40000000 if VMSPLIT_1G
1598 default 0x80000000 if VMSPLIT_2G
1599 default 0xC0000000
1601 config NR_CPUS
1602 int "Maximum number of CPUs (2-32)"
1603 range 2 32
1604 depends on SMP
1605 default "4"
1607 config HOTPLUG_CPU
1608 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1609 depends on SMP && HOTPLUG && EXPERIMENTAL
1610 help
1611 Say Y here to experiment with turning CPUs off and on. CPUs
1612 can be controlled through /sys/devices/system/cpu.
1614 config LOCAL_TIMERS
1615 bool "Use local timer interrupts"
1616 depends on SMP
1617 default y
1618 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1619 help
1620 Enable support for local timers on SMP platforms, rather then the
1621 legacy IPI broadcast method. Local timers allows the system
1622 accounting to be spread across the timer interval, preventing a
1623 "thundering herd" at every timer tick.
1625 config ARCH_NR_GPIO
1626 int
1627 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1628 default 355 if ARCH_U8500
1629 default 264 if MACH_H4700
1630 default 512 if SOC_OMAP5
1631 default 0
1632 help
1633 Maximum number of GPIOs in the system.
1635 If unsure, leave the default value.
1637 source kernel/Kconfig.preempt
1639 config HZ
1640 int
1641 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1642 ARCH_S5PV210 || ARCH_EXYNOS4
1643 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1644 default AT91_TIMER_HZ if ARCH_AT91
1645 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1646 default 100
1648 config THUMB2_KERNEL
1649 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1650 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1651 select AEABI
1652 select ARM_ASM_UNIFIED
1653 select ARM_UNWIND
1654 help
1655 By enabling this option, the kernel will be compiled in
1656 Thumb-2 mode. A compiler/assembler that understand the unified
1657 ARM-Thumb syntax is needed.
1659 If unsure, say N.
1661 config THUMB2_AVOID_R_ARM_THM_JUMP11
1662 bool "Work around buggy Thumb-2 short branch relocations in gas"
1663 depends on THUMB2_KERNEL && MODULES
1664 default y
1665 help
1666 Various binutils versions can resolve Thumb-2 branches to
1667 locally-defined, preemptible global symbols as short-range "b.n"
1668 branch instructions.
1670 This is a problem, because there's no guarantee the final
1671 destination of the symbol, or any candidate locations for a
1672 trampoline, are within range of the branch. For this reason, the
1673 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1674 relocation in modules at all, and it makes little sense to add
1675 support.
1677 The symptom is that the kernel fails with an "unsupported
1678 relocation" error when loading some modules.
1680 Until fixed tools are available, passing
1681 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1682 code which hits this problem, at the cost of a bit of extra runtime
1683 stack usage in some cases.
1685 The problem is described in more detail at:
1686 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1688 Only Thumb-2 kernels are affected.
1690 Unless you are sure your tools don't have this problem, say Y.
1692 config ARM_ASM_UNIFIED
1693 bool
1695 config AEABI
1696 bool "Use the ARM EABI to compile the kernel"
1697 help
1698 This option allows for the kernel to be compiled using the latest
1699 ARM ABI (aka EABI). This is only useful if you are using a user
1700 space environment that is also compiled with EABI.
1702 Since there are major incompatibilities between the legacy ABI and
1703 EABI, especially with regard to structure member alignment, this
1704 option also changes the kernel syscall calling convention to
1705 disambiguate both ABIs and allow for backward compatibility support
1706 (selected with CONFIG_OABI_COMPAT).
1708 To use this you need GCC version 4.0.0 or later.
1710 config OABI_COMPAT
1711 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1712 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1713 default y
1714 help
1715 This option preserves the old syscall interface along with the
1716 new (ARM EABI) one. It also provides a compatibility layer to
1717 intercept syscalls that have structure arguments which layout
1718 in memory differs between the legacy ABI and the new ARM EABI
1719 (only for non "thumb" binaries). This option adds a tiny
1720 overhead to all syscalls and produces a slightly larger kernel.
1721 If you know you'll be using only pure EABI user space then you
1722 can say N here. If this option is not selected and you attempt
1723 to execute a legacy ABI binary then the result will be
1724 UNPREDICTABLE (in fact it can be predicted that it won't work
1725 at all). If in doubt say Y.
1727 config ARCH_HAS_HOLES_MEMORYMODEL
1728 bool
1730 config ARCH_SPARSEMEM_ENABLE
1731 bool
1733 config ARCH_SPARSEMEM_DEFAULT
1734 def_bool ARCH_SPARSEMEM_ENABLE
1736 config ARCH_SELECT_MEMORY_MODEL
1737 def_bool ARCH_SPARSEMEM_ENABLE
1739 config HAVE_ARCH_PFN_VALID
1740 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1742 config HIGHMEM
1743 bool "High Memory Support"
1744 depends on MMU
1745 help
1746 The address space of ARM processors is only 4 Gigabytes large
1747 and it has to accommodate user address space, kernel address
1748 space as well as some memory mapped IO. That means that, if you
1749 have a large amount of physical memory and/or IO, not all of the
1750 memory can be "permanently mapped" by the kernel. The physical
1751 memory that is not permanently mapped is called "high memory".
1753 Depending on the selected kernel/user memory split, minimum
1754 vmalloc space and actual amount of RAM, you may not need this
1755 option which should result in a slightly faster kernel.
1757 If unsure, say n.
1759 config HIGHPTE
1760 bool "Allocate 2nd-level pagetables from highmem"
1761 depends on HIGHMEM
1763 config HW_PERF_EVENTS
1764 bool "Enable hardware performance counter support for perf events"
1765 depends on PERF_EVENTS && CPU_HAS_PMU
1766 default y
1767 help
1768 Enable hardware performance counter support for perf events. If
1769 disabled, perf events will use software events only.
1771 source "mm/Kconfig"
1773 config FORCE_MAX_ZONEORDER
1774 int "Maximum zone order" if ARCH_SHMOBILE
1775 range 11 64 if ARCH_SHMOBILE
1776 default "9" if SA1111
1777 default "11"
1778 help
1779 The kernel memory allocator divides physically contiguous memory
1780 blocks into "zones", where each zone is a power of two number of
1781 pages. This option selects the largest power of two that the kernel
1782 keeps in the memory allocator. If you need to allocate very large
1783 blocks of physically contiguous memory, then you may need to
1784 increase this value.
1786 This config option is actually maximum order plus one. For example,
1787 a value of 11 means that the largest free memory block is 2^10 pages.
1789 config LEDS
1790 bool "Timer and CPU usage LEDs"
1791 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1792 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1793 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1794 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1795 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1796 ARCH_AT91 || ARCH_DAVINCI || \
1797 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1798 help
1799 If you say Y here, the LEDs on your machine will be used
1800 to provide useful information about your current system status.
1802 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1803 be able to select which LEDs are active using the options below. If
1804 you are compiling a kernel for the EBSA-110 or the LART however, the
1805 red LED will simply flash regularly to indicate that the system is
1806 still functional. It is safe to say Y here if you have a CATS
1807 system, but the driver will do nothing.
1809 config LEDS_TIMER
1810 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1811 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1812 || MACH_OMAP_PERSEUS2
1813 depends on LEDS
1814 depends on !GENERIC_CLOCKEVENTS
1815 default y if ARCH_EBSA110
1816 help
1817 If you say Y here, one of the system LEDs (the green one on the
1818 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1819 will flash regularly to indicate that the system is still
1820 operational. This is mainly useful to kernel hackers who are
1821 debugging unstable kernels.
1823 The LART uses the same LED for both Timer LED and CPU usage LED
1824 functions. You may choose to use both, but the Timer LED function
1825 will overrule the CPU usage LED.
1827 config LEDS_CPU
1828 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1829 !ARCH_OMAP) \
1830 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1831 || MACH_OMAP_PERSEUS2
1832 depends on LEDS
1833 help
1834 If you say Y here, the red LED will be used to give a good real
1835 time indication of CPU usage, by lighting whenever the idle task
1836 is not currently executing.
1838 The LART uses the same LED for both Timer LED and CPU usage LED
1839 functions. You may choose to use both, but the Timer LED function
1840 will overrule the CPU usage LED.
1842 config ALIGNMENT_TRAP
1843 bool
1844 depends on CPU_CP15_MMU
1845 default y if !ARCH_EBSA110
1846 select HAVE_PROC_CPU if PROC_FS
1847 help
1848 ARM processors cannot fetch/store information which is not
1849 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1850 address divisible by 4. On 32-bit ARM processors, these non-aligned
1851 fetch/store instructions will be emulated in software if you say
1852 here, which has a severe performance impact. This is necessary for
1853 correct operation of some network protocols. With an IP-only
1854 configuration it is safe to say N, otherwise say Y.
1856 config UACCESS_WITH_MEMCPY
1857 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1858 depends on MMU && EXPERIMENTAL
1859 default y if CPU_FEROCEON
1860 help
1861 Implement faster copy_to_user and clear_user methods for CPU
1862 cores where a 8-word STM instruction give significantly higher
1863 memory write throughput than a sequence of individual 32bit stores.
1865 A possible side effect is a slight increase in scheduling latency
1866 between threads sharing the same address space if they invoke
1867 such copy operations with large buffers.
1869 However, if the CPU data cache is using a write-allocate mode,
1870 this option is unlikely to provide any performance gain.
1872 config SECCOMP
1873 bool
1874 prompt "Enable seccomp to safely compute untrusted bytecode"
1875 ---help---
1876 This kernel feature is useful for number crunching applications
1877 that may need to compute untrusted bytecode during their
1878 execution. By using pipes or other transports made available to
1879 the process as file descriptors supporting the read/write
1880 syscalls, it's possible to isolate those applications in
1881 their own address space using seccomp. Once seccomp is
1882 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1883 and the task is only allowed to execute a few safe syscalls
1884 defined by each seccomp mode.
1886 config CC_STACKPROTECTOR
1887 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1888 depends on EXPERIMENTAL
1889 help
1890 This option turns on the -fstack-protector GCC feature. This
1891 feature puts, at the beginning of functions, a canary value on
1892 the stack just before the return address, and validates
1893 the value just before actually returning. Stack based buffer
1894 overflows (that need to overwrite this return address) now also
1895 overwrite the canary, which gets detected and the attack is then
1896 neutralized via a kernel panic.
1897 This feature requires gcc version 4.2 or above.
1899 config DEPRECATED_PARAM_STRUCT
1900 bool "Provide old way to pass kernel parameters"
1901 help
1902 This was deprecated in 2001 and announced to live on for 5 years.
1903 Some old boot loaders still use this way.
1905 endmenu
1907 menu "Boot options"
1909 config USE_OF
1910 bool "Flattened Device Tree support"
1911 select OF
1912 select OF_EARLY_FLATTREE
1913 select IRQ_DOMAIN
1914 help
1915 Include support for flattened device tree machine descriptions.
1917 # Compressed boot loader in ROM. Yes, we really want to ask about
1918 # TEXT and BSS so we preserve their values in the config files.
1919 config ZBOOT_ROM_TEXT
1920 hex "Compressed ROM boot loader base address"
1921 default "0"
1922 help
1923 The physical address at which the ROM-able zImage is to be
1924 placed in the target. Platforms which normally make use of
1925 ROM-able zImage formats normally set this to a suitable
1926 value in their defconfig file.
1928 If ZBOOT_ROM is not enabled, this has no effect.
1930 config ZBOOT_ROM_BSS
1931 hex "Compressed ROM boot loader BSS address"
1932 default "0"
1933 help
1934 The base address of an area of read/write memory in the target
1935 for the ROM-able zImage which must be available while the
1936 decompressor is running. It must be large enough to hold the
1937 entire decompressed kernel plus an additional 128 KiB.
1938 Platforms which normally make use of ROM-able zImage formats
1939 normally set this to a suitable value in their defconfig file.
1941 If ZBOOT_ROM is not enabled, this has no effect.
1943 config ZBOOT_ROM
1944 bool "Compressed boot loader in ROM/flash"
1945 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1946 help
1947 Say Y here if you intend to execute your compressed kernel image
1948 (zImage) directly from ROM or flash. If unsure, say N.
1950 choice
1951 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1952 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1953 default ZBOOT_ROM_NONE
1954 help
1955 Include experimental SD/MMC loading code in the ROM-able zImage.
1956 With this enabled it is possible to write the ROM-able zImage
1957 kernel image to an MMC or SD card and boot the kernel straight
1958 from the reset vector. At reset the processor Mask ROM will load
1959 the first part of the ROM-able zImage which in turn loads the
1960 rest the kernel image to RAM.
1962 config ZBOOT_ROM_NONE
1963 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1964 help
1965 Do not load image from SD or MMC
1967 config ZBOOT_ROM_MMCIF
1968 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1969 help
1970 Load image from MMCIF hardware block.
1972 config ZBOOT_ROM_SH_MOBILE_SDHI
1973 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1974 help
1975 Load image from SDHI hardware block
1977 endchoice
1979 config ARM_APPENDED_DTB
1980 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1981 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1982 help
1983 With this option, the boot code will look for a device tree binary
1984 (DTB) appended to zImage
1985 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1987 This is meant as a backward compatibility convenience for those
1988 systems with a bootloader that can't be upgraded to accommodate
1989 the documented boot protocol using a device tree.
1991 Beware that there is very little in terms of protection against
1992 this option being confused by leftover garbage in memory that might
1993 look like a DTB header after a reboot if no actual DTB is appended
1994 to zImage. Do not leave this option active in a production kernel
1995 if you don't intend to always append a DTB. Proper passing of the
1996 location into r2 of a bootloader provided DTB is always preferable
1997 to this option.
1999 config ARM_ATAG_DTB_COMPAT
2000 bool "Supplement the appended DTB with traditional ATAG information"
2001 depends on ARM_APPENDED_DTB
2002 help
2003 Some old bootloaders can't be updated to a DTB capable one, yet
2004 they provide ATAGs with memory configuration, the ramdisk address,
2005 the kernel cmdline string, etc. Such information is dynamically
2006 provided by the bootloader and can't always be stored in a static
2007 DTB. To allow a device tree enabled kernel to be used with such
2008 bootloaders, this option allows zImage to extract the information
2009 from the ATAG list and store it at run time into the appended DTB.
2011 choice
2012 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2013 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2015 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2016 bool "Use bootloader kernel arguments if available"
2017 help
2018 Uses the command-line options passed by the boot loader instead of
2019 the device tree bootargs property. If the boot loader doesn't provide
2020 any, the device tree bootargs property will be used.
2022 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2023 bool "Extend with bootloader kernel arguments"
2024 help
2025 The command-line arguments provided by the boot loader will be
2026 appended to the the device tree bootargs property.
2028 endchoice
2030 config CMDLINE
2031 string "Default kernel command string"
2032 default ""
2033 help
2034 On some architectures (EBSA110 and CATS), there is currently no way
2035 for the boot loader to pass arguments to the kernel. For these
2036 architectures, you should supply some command-line options at build
2037 time by entering them here. As a minimum, you should specify the
2038 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2040 choice
2041 prompt "Kernel command line type" if CMDLINE != ""
2042 default CMDLINE_FROM_BOOTLOADER
2044 config CMDLINE_FROM_BOOTLOADER
2045 bool "Use bootloader kernel arguments if available"
2046 help
2047 Uses the command-line options passed by the boot loader. If
2048 the boot loader doesn't provide any, the default kernel command
2049 string provided in CMDLINE will be used.
2051 config CMDLINE_EXTEND
2052 bool "Extend bootloader kernel arguments"
2053 help
2054 The command-line arguments provided by the boot loader will be
2055 appended to the default kernel command string.
2057 config CMDLINE_FORCE
2058 bool "Always use the default kernel command string"
2059 help
2060 Always use the default kernel command string, even if the boot
2061 loader passes other arguments to the kernel.
2062 This is useful if you cannot or don't want to change the
2063 command-line options your boot loader passes to the kernel.
2064 endchoice
2066 config XIP_KERNEL
2067 bool "Kernel Execute-In-Place from ROM"
2068 depends on !ZBOOT_ROM && !ARM_LPAE
2069 help
2070 Execute-In-Place allows the kernel to run from non-volatile storage
2071 directly addressable by the CPU, such as NOR flash. This saves RAM
2072 space since the text section of the kernel is not loaded from flash
2073 to RAM. Read-write sections, such as the data section and stack,
2074 are still copied to RAM. The XIP kernel is not compressed since
2075 it has to run directly from flash, so it will take more space to
2076 store it. The flash address used to link the kernel object files,
2077 and for storing it, is configuration dependent. Therefore, if you
2078 say Y here, you must know the proper physical address where to
2079 store the kernel image depending on your own flash memory usage.
2081 Also note that the make target becomes "make xipImage" rather than
2082 "make zImage" or "make Image". The final kernel binary to put in
2083 ROM memory will be arch/arm/boot/xipImage.
2085 If unsure, say N.
2087 config XIP_PHYS_ADDR
2088 hex "XIP Kernel Physical Location"
2089 depends on XIP_KERNEL
2090 default "0x00080000"
2091 help
2092 This is the physical address in your flash memory the kernel will
2093 be linked for and stored to. This address is dependent on your
2094 own flash usage.
2096 config KEXEC
2097 bool "Kexec system call (EXPERIMENTAL)"
2098 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2099 help
2100 kexec is a system call that implements the ability to shutdown your
2101 current kernel, and to start another kernel. It is like a reboot
2102 but it is independent of the system firmware. And like a reboot
2103 you can start any kernel with it, not just Linux.
2105 It is an ongoing process to be certain the hardware in a machine
2106 is properly shutdown, so do not be surprised if this code does not
2107 initially work for you. It may help to enable device hotplugging
2108 support.
2110 config ATAGS_PROC
2111 bool "Export atags in procfs"
2112 depends on KEXEC
2113 default y
2114 help
2115 Should the atags used to boot the kernel be exported in an "atags"
2116 file in procfs. Useful with kexec.
2118 config CRASH_DUMP
2119 bool "Build kdump crash kernel (EXPERIMENTAL)"
2120 depends on EXPERIMENTAL
2121 help
2122 Generate crash dump after being started by kexec. This should
2123 be normally only set in special crash dump kernels which are
2124 loaded in the main kernel with kexec-tools into a specially
2125 reserved region and then later executed after a crash by
2126 kdump/kexec. The crash dump kernel must be compiled to a
2127 memory address not used by the main kernel
2129 For more details see Documentation/kdump/kdump.txt
2131 config AUTO_ZRELADDR
2132 bool "Auto calculation of the decompressed kernel image address"
2133 depends on !ZBOOT_ROM && !ARCH_U300
2134 help
2135 ZRELADDR is the physical address where the decompressed kernel
2136 image will be placed. If AUTO_ZRELADDR is selected, the address
2137 will be determined at run-time by masking the current IP with
2138 0xf8000000. This assumes the zImage being placed in the first 128MB
2139 from start of memory.
2141 endmenu
2143 menu "CPU Power Management"
2145 if ARCH_HAS_CPUFREQ
2147 source "drivers/cpufreq/Kconfig"
2149 config CPU_FREQ_IMX
2150 tristate "CPUfreq driver for i.MX CPUs"
2151 depends on ARCH_MXC && CPU_FREQ
2152 help
2153 This enables the CPUfreq driver for i.MX CPUs.
2155 config CPU_FREQ_SA1100
2156 bool
2158 config CPU_FREQ_SA1110
2159 bool
2161 config CPU_FREQ_INTEGRATOR
2162 tristate "CPUfreq driver for ARM Integrator CPUs"
2163 depends on ARCH_INTEGRATOR && CPU_FREQ
2164 default y
2165 help
2166 This enables the CPUfreq driver for ARM Integrator CPUs.
2168 For details, take a look at <file:Documentation/cpu-freq>.
2170 If in doubt, say Y.
2172 config CPU_FREQ_PXA
2173 bool
2174 depends on CPU_FREQ && ARCH_PXA && PXA25x
2175 default y
2176 select CPU_FREQ_TABLE
2177 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2179 config CPU_FREQ_S3C
2180 bool
2181 help
2182 Internal configuration node for common cpufreq on Samsung SoC
2184 config CPU_FREQ_S3C24XX
2185 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2186 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2187 select CPU_FREQ_S3C
2188 help
2189 This enables the CPUfreq driver for the Samsung S3C24XX family
2190 of CPUs.
2192 For details, take a look at <file:Documentation/cpu-freq>.
2194 If in doubt, say N.
2196 config CPU_FREQ_S3C24XX_PLL
2197 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2198 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2199 help
2200 Compile in support for changing the PLL frequency from the
2201 S3C24XX series CPUfreq driver. The PLL takes time to settle
2202 after a frequency change, so by default it is not enabled.
2204 This also means that the PLL tables for the selected CPU(s) will
2205 be built which may increase the size of the kernel image.
2207 config CPU_FREQ_S3C24XX_DEBUG
2208 bool "Debug CPUfreq Samsung driver core"
2209 depends on CPU_FREQ_S3C24XX
2210 help
2211 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2213 config CPU_FREQ_S3C24XX_IODEBUG
2214 bool "Debug CPUfreq Samsung driver IO timing"
2215 depends on CPU_FREQ_S3C24XX
2216 help
2217 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2219 config CPU_FREQ_S3C24XX_DEBUGFS
2220 bool "Export debugfs for CPUFreq"
2221 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2222 help
2223 Export status information via debugfs.
2225 endif
2227 source "drivers/cpuidle/Kconfig"
2229 endmenu
2231 menu "Floating point emulation"
2233 comment "At least one emulation must be selected"
2235 config FPE_NWFPE
2236 bool "NWFPE math emulation"
2237 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2238 ---help---
2239 Say Y to include the NWFPE floating point emulator in the kernel.
2240 This is necessary to run most binaries. Linux does not currently
2241 support floating point hardware so you need to say Y here even if
2242 your machine has an FPA or floating point co-processor podule.
2244 You may say N here if you are going to load the Acorn FPEmulator
2245 early in the bootup.
2247 config FPE_NWFPE_XP
2248 bool "Support extended precision"
2249 depends on FPE_NWFPE
2250 help
2251 Say Y to include 80-bit support in the kernel floating-point
2252 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2253 Note that gcc does not generate 80-bit operations by default,
2254 so in most cases this option only enlarges the size of the
2255 floating point emulator without any good reason.
2257 You almost surely want to say N here.
2259 config FPE_FASTFPE
2260 bool "FastFPE math emulation (EXPERIMENTAL)"
2261 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2262 ---help---
2263 Say Y here to include the FAST floating point emulator in the kernel.
2264 This is an experimental much faster emulator which now also has full
2265 precision for the mantissa. It does not support any exceptions.
2266 It is very simple, and approximately 3-6 times faster than NWFPE.
2268 It should be sufficient for most programs. It may be not suitable
2269 for scientific calculations, but you have to check this for yourself.
2270 If you do not feel you need a faster FP emulation you should better
2271 choose NWFPE.
2273 config VFP
2274 bool "VFP-format floating point maths"
2275 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2276 help
2277 Say Y to include VFP support code in the kernel. This is needed
2278 if your hardware includes a VFP unit.
2280 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2281 release notes and additional status information.
2283 Say N if your target does not have VFP hardware.
2285 config VFPv3
2286 bool
2287 depends on VFP
2288 default y if CPU_V7
2290 config NEON
2291 bool "Advanced SIMD (NEON) Extension support"
2292 depends on VFPv3 && CPU_V7
2293 help
2294 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2295 Extension.
2297 endmenu
2299 menu "Userspace binary formats"
2301 source "fs/Kconfig.binfmt"
2303 config ARTHUR
2304 tristate "RISC OS personality"
2305 depends on !AEABI
2306 help
2307 Say Y here to include the kernel code necessary if you want to run
2308 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2309 experimental; if this sounds frightening, say N and sleep in peace.
2310 You can also say M here to compile this support as a module (which
2311 will be called arthur).
2313 endmenu
2315 menu "Power management options"
2317 source "kernel/power/Kconfig"
2319 config ARCH_SUSPEND_POSSIBLE
2320 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2321 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2322 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2323 def_bool y
2325 config ARM_CPU_SUSPEND
2326 def_bool PM_SLEEP
2328 endmenu
2330 source "net/Kconfig"
2332 source "drivers/Kconfig"
2334 source "fs/Kconfig"
2336 source "arch/arm/Kconfig.debug"
2338 source "security/Kconfig"
2340 source "crypto/Kconfig"
2342 source "lib/Kconfig"