arch/arm/mach-imx/ehci-imx35.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/mxc_ehci.h>
  21
  22 #define USBCTRL_OTGBASE_OFFSET  0x600
  23
  24 #define MX35_OTG_SIC_SHIFT      29
  25 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
  26 #define MX35_OTG_PM_BIT         (1 << 24)
  27 #define MX35_OTG_PP_BIT         (1 << 11)
  28 #define MX35_OTG_OCPOL_BIT      (1 << 3)
  29
  30 #define MX35_H1_SIC_SHIFT       21
  31 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
  32 #define MX35_H1_PP_BIT          (1 << 18)
  33 #define MX35_H1_PM_BIT          (1 << 8)
  34 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
  35 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
  36 #define MX35_H1_TLL_BIT         (1 << 5)
  37 #define MX35_H1_USBTE_BIT       (1 << 4)
  38 #define MX35_H1_OCPOL_BIT       (1 << 2)
  39
  40 int mx35_initialize_usb_hw(int port, unsigned int flags)
  41 {
  42         unsigned int v;
  43
  44         v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  45
  46         switch (port) {
  47         case 0: /* OTG port */
  48                 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
  49                         MX35_OTG_OCPOL_BIT);
  50                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
  51
  52                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  53                         v |= MX35_OTG_PM_BIT;
  54
  55                 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  56                         v |= MX35_OTG_PP_BIT;
  57
  58                 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  59                         v |= MX35_OTG_OCPOL_BIT;
  60
  61                 break;
  62         case 1: /* H1 port */
  63                 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
  64                         MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
  65                         MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
  66                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
  67
  68                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  69                         v |= MX35_H1_PM_BIT;
  70
  71                 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  72                         v |= MX35_H1_PP_BIT;
  73
  74                 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  75                         v |= MX35_H1_OCPOL_BIT;
  76
  77                 if (!(flags & MXC_EHCI_TTL_ENABLED))
  78                         v |= MX35_H1_TLL_BIT;
  79
  80                 if (flags & MXC_EHCI_INTERNAL_PHY)
  81                         v |= MX35_H1_USBTE_BIT;
  82
  83                 if (flags & MXC_EHCI_IPPUE_DOWN)
  84                         v |= MX35_H1_IPPUE_DOWN_BIT;
  85
  86                 if (flags & MXC_EHCI_IPPUE_UP)
  87                         v |= MX35_H1_IPPUE_UP_BIT;
  88
  89                 break;
  90         default:
  91                 return -EINVAL;
  92         }
  93
  94         writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  95
  96         return 0;
  97 }