arch/arm/mach-imx/mach-mx31ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/clk.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/gpio.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24 #include <linux/irqdomain.h>
  25
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/memory.h>
  30 #include <asm/mach/map.h>
  31 #include <mach/common.h>
  32 #include <mach/iomux-mx3.h>
  33
  34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
  35 #include <linux/mfd/wm8350/audio.h>
  36 #include <linux/mfd/wm8350/core.h>
  37 #include <linux/mfd/wm8350/pmic.h>
  38 #endif
  39
  40 #include "devices-imx31.h"
  41
  42 /* Base address of PBC controller */
  43 #define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
  44
  45 /* PBC Board interrupt status register */
  46 #define PBC_INTSTATUS           0x000016
  47
  48 /* PBC Board interrupt current status register */
  49 #define PBC_INTCURR_STATUS      0x000018
  50
  51 /* PBC Interrupt mask register set address */
  52 #define PBC_INTMASK_SET         0x00001A
  53
  54 /* PBC Interrupt mask register clear address */
  55 #define PBC_INTMASK_CLEAR       0x00001C
  56
  57 /* External UART A */
  58 #define PBC_SC16C652_UARTA      0x010000
  59
  60 /* External UART B */
  61 #define PBC_SC16C652_UARTB      0x010010
  62
  63 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
  64 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
  65 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
  66
  67 #define EXPIO_INT_XUART_INTA    10
  68 #define EXPIO_INT_XUART_INTB    11
  69
  70 #define MXC_MAX_EXP_IO_LINES    16
  71
  72 /* CS8900 */
  73 #define EXPIO_INT_ENET_INT      8
  74 #define CS4_CS8900_MMIO_START   0x20000
  75
  76 static struct irq_domain *domain;
  77
  78 /*
  79  * The serial port definition structure.
  80  */
  81 static struct plat_serial8250_port serial_platform_data[] = {
  82         {
  83                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
  84                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
  85                 .uartclk  = 14745600,
  86                 .regshift = 0,
  87                 .iotype   = UPIO_MEM,
  88                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  89         }, {
  90                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
  91                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
  92                 .uartclk  = 14745600,
  93                 .regshift = 0,
  94                 .iotype   = UPIO_MEM,
  95                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  96         },
  97         {},
  98 };
  99
 100 static struct platform_device serial_device = {
 101         .name   = "serial8250",
 102         .id     = 0,
 103         .dev    = {
 104                 .platform_data = serial_platform_data,
 105         },
 106 };
 107
 108 static struct resource mx31ads_cs8900_resources[] __initdata = {
 109         DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
 110         DEFINE_RES_IRQ(-1),
 111 };
 112
 113 static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
 114         .name = "cs89x0",
 115         .id = 0,
 116         .res = mx31ads_cs8900_resources,
 117         .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
 118 };
 119
 120 static int __init mxc_init_extuart(void)
 121 {
 122         serial_platform_data[0].irq = irq_find_mapping(domain,
 123                                                        EXPIO_INT_XUART_INTA);
 124         serial_platform_data[1].irq = irq_find_mapping(domain,
 125                                                        EXPIO_INT_XUART_INTB);
 126         return platform_device_register(&serial_device);
 127 }
 128
 129 static void __init mxc_init_ext_ethernet(void)
 130 {
 131         mx31ads_cs8900_resources[1].start =
 132                         irq_find_mapping(domain, EXPIO_INT_ENET_INT);
 133         mx31ads_cs8900_resources[1].end =
 134                         irq_find_mapping(domain, EXPIO_INT_ENET_INT);
 135         platform_device_register_full(
 136                 (struct platform_device_info *)&mx31ads_cs8900_devinfo);
 137 }
 138
 139 static const struct imxuart_platform_data uart_pdata __initconst = {
 140         .flags = IMXUART_HAVE_RTSCTS,
 141 };
 142
 143 static unsigned int uart_pins[] = {
 144         MX31_PIN_CTS1__CTS1,
 145         MX31_PIN_RTS1__RTS1,
 146         MX31_PIN_TXD1__TXD1,
 147         MX31_PIN_RXD1__RXD1
 148 };
 149
 150 static inline void mxc_init_imx_uart(void)
 151 {
 152         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
 153         imx31_add_imx_uart0(&uart_pdata);
 154 }
 155
 156 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 157 {
 158         u32 imr_val;
 159         u32 int_valid;
 160         u32 expio_irq;
 161
 162         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
 163         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 164
 165         expio_irq = 0;
 166         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
 167                 if ((int_valid & 1) == 0)
 168                         continue;
 169
 170                 generic_handle_irq(irq_find_mapping(domain, expio_irq));
 171         }
 172 }
 173
 174 /*
 175  * Disable an expio pin's interrupt by setting the bit in the imr.
 176  * @param d     an expio virtual irq description
 177  */
 178 static void expio_mask_irq(struct irq_data *d)
 179 {
 180         u32 expio = d->hwirq;
 181         /* mask the interrupt */
 182         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
 183         __raw_readw(PBC_INTMASK_CLEAR_REG);
 184 }
 185
 186 /*
 187  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 188  * @param d     an expio virtual irq description
 189  */
 190 static void expio_ack_irq(struct irq_data *d)
 191 {
 192         u32 expio = d->hwirq;
 193         /* clear the interrupt status */
 194         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 195 }
 196
 197 /*
 198  * Enable a expio pin's interrupt by clearing the bit in the imr.
 199  * @param d     an expio virtual irq description
 200  */
 201 static void expio_unmask_irq(struct irq_data *d)
 202 {
 203         u32 expio = d->hwirq;
 204         /* unmask the interrupt */
 205         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 206 }
 207
 208 static struct irq_chip expio_irq_chip = {
 209         .name = "EXPIO(CPLD)",
 210         .irq_ack = expio_ack_irq,
 211         .irq_mask = expio_mask_irq,
 212         .irq_unmask = expio_unmask_irq,
 213 };
 214
 215 static void __init mx31ads_init_expio(void)
 216 {
 217         int irq_base;
 218         int i, irq;
 219
 220         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 221
 222         /*
 223          * Configure INT line as GPIO input
 224          */
 225         mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
 226
 227         /* disable the interrupt and clear the status */
 228         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
 229         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
 230
 231         irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
 232         WARN_ON(irq_base < 0);
 233
 234         domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
 235                                        &irq_domain_simple_ops, NULL);
 236         WARN_ON(!domain);
 237
 238         for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
 239                 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
 240                 set_irq_flags(i, IRQF_VALID);
 241         }
 242         irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
 243         irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
 244         irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
 245 }
 246
 247 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 248 /* This section defines setup for the Wolfson Microelectronics
 249  * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 250  * regulator definitions may be shared with them, but for now they can
 251  * only be used with this board so would generate warnings about
 252  * unused statics and some of the configuration is specific to this
 253  * module.
 254  */
 255
 256 /* CPU */
 257 static struct regulator_consumer_supply sw1a_consumers[] = {
 258         {
 259                 .supply = "cpu_vcc",
 260         }
 261 };
 262
 263 static struct regulator_init_data sw1a_data = {
 264         .constraints = {
 265                 .name = "SW1A",
 266                 .min_uV = 1275000,
 267                 .max_uV = 1600000,
 268                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 269                                   REGULATOR_CHANGE_MODE,
 270                 .valid_modes_mask = REGULATOR_MODE_NORMAL |
 271                                     REGULATOR_MODE_FAST,
 272                 .state_mem = {
 273                          .uV = 1400000,
 274                          .mode = REGULATOR_MODE_NORMAL,
 275                          .enabled = 1,
 276                  },
 277                 .initial_state = PM_SUSPEND_MEM,
 278                 .always_on = 1,
 279                 .boot_on = 1,
 280         },
 281         .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
 282         .consumer_supplies = sw1a_consumers,
 283 };
 284
 285 /* System IO - High */
 286 static struct regulator_init_data viohi_data = {
 287         .constraints = {
 288                 .name = "VIOHO",
 289                 .min_uV = 2800000,
 290                 .max_uV = 2800000,
 291                 .state_mem = {
 292                          .uV = 2800000,
 293                          .mode = REGULATOR_MODE_NORMAL,
 294                          .enabled = 1,
 295                  },
 296                 .initial_state = PM_SUSPEND_MEM,
 297                 .always_on = 1,
 298                 .boot_on = 1,
 299         },
 300 };
 301
 302 /* System IO - Low */
 303 static struct regulator_init_data violo_data = {
 304         .constraints = {
 305                 .name = "VIOLO",
 306                 .min_uV = 1800000,
 307                 .max_uV = 1800000,
 308                 .state_mem = {
 309                          .uV = 1800000,
 310                          .mode = REGULATOR_MODE_NORMAL,
 311                          .enabled = 1,
 312                  },
 313                 .initial_state = PM_SUSPEND_MEM,
 314                 .always_on = 1,
 315                 .boot_on = 1,
 316         },
 317 };
 318
 319 /* DDR RAM */
 320 static struct regulator_init_data sw2a_data = {
 321         .constraints = {
 322                 .name = "SW2A",
 323                 .min_uV = 1800000,
 324                 .max_uV = 1800000,
 325                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 326                 .state_mem = {
 327                          .uV = 1800000,
 328                          .mode = REGULATOR_MODE_NORMAL,
 329                          .enabled = 1,
 330                  },
 331                 .state_disk = {
 332                          .mode = REGULATOR_MODE_NORMAL,
 333                          .enabled = 0,
 334                  },
 335                 .always_on = 1,
 336                 .boot_on = 1,
 337                 .initial_state = PM_SUSPEND_MEM,
 338         },
 339 };
 340
 341 static struct regulator_init_data ldo1_data = {
 342         .constraints = {
 343                 .name = "VCAM/VMMC1/VMMC2",
 344                 .min_uV = 2800000,
 345                 .max_uV = 2800000,
 346                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 347                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 348                 .apply_uV = 1,
 349         },
 350 };
 351
 352 static struct regulator_consumer_supply ldo2_consumers[] = {
 353         { .supply = "AVDD", .dev_name = "1-001a" },
 354         { .supply = "HPVDD", .dev_name = "1-001a" },
 355 };
 356
 357 /* CODEC and SIM */
 358 static struct regulator_init_data ldo2_data = {
 359         .constraints = {
 360                 .name = "VESIM/VSIM/AVDD",
 361                 .min_uV = 3300000,
 362                 .max_uV = 3300000,
 363                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 364                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 365                 .apply_uV = 1,
 366         },
 367         .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
 368         .consumer_supplies = ldo2_consumers,
 369 };
 370
 371 /* General */
 372 static struct regulator_init_data vdig_data = {
 373         .constraints = {
 374                 .name = "VDIG",
 375                 .min_uV = 1500000,
 376                 .max_uV = 1500000,
 377                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 378                 .apply_uV = 1,
 379                 .always_on = 1,
 380                 .boot_on = 1,
 381         },
 382 };
 383
 384 /* Tranceivers */
 385 static struct regulator_init_data ldo4_data = {
 386         .constraints = {
 387                 .name = "VRF1/CVDD_2.775",
 388                 .min_uV = 2500000,
 389                 .max_uV = 2500000,
 390                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 391                 .apply_uV = 1,
 392                 .always_on = 1,
 393                 .boot_on = 1,
 394         },
 395 };
 396
 397 static struct wm8350_led_platform_data wm8350_led_data = {
 398         .name            = "wm8350:white",
 399         .default_trigger = "heartbeat",
 400         .max_uA          = 27899,
 401 };
 402
 403 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
 404         .vmid_discharge_msecs = 1000,
 405         .drain_msecs = 30,
 406         .cap_discharge_msecs = 700,
 407         .vmid_charge_msecs = 700,
 408         .vmid_s_curve = WM8350_S_CURVE_SLOW,
 409         .dis_out4 = WM8350_DISCHARGE_SLOW,
 410         .dis_out3 = WM8350_DISCHARGE_SLOW,
 411         .dis_out2 = WM8350_DISCHARGE_SLOW,
 412         .dis_out1 = WM8350_DISCHARGE_SLOW,
 413         .vroi_out4 = WM8350_TIE_OFF_500R,
 414         .vroi_out3 = WM8350_TIE_OFF_500R,
 415         .vroi_out2 = WM8350_TIE_OFF_500R,
 416         .vroi_out1 = WM8350_TIE_OFF_500R,
 417         .vroi_enable = 0,
 418         .codec_current_on = WM8350_CODEC_ISEL_1_0,
 419         .codec_current_standby = WM8350_CODEC_ISEL_0_5,
 420         .codec_current_charge = WM8350_CODEC_ISEL_1_5,
 421 };
 422
 423 static int mx31_wm8350_init(struct wm8350 *wm8350)
 424 {
 425         wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
 426                            WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
 427                            WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
 428                            WM8350_GPIO_DEBOUNCE_ON);
 429
 430         wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
 431                            WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
 432                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 433                            WM8350_GPIO_DEBOUNCE_ON);
 434
 435         wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
 436                            WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
 437                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 438                            WM8350_GPIO_DEBOUNCE_OFF);
 439
 440         wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
 441                            WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
 442                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 443                            WM8350_GPIO_DEBOUNCE_OFF);
 444
 445         wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
 446                            WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
 447                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 448                            WM8350_GPIO_DEBOUNCE_OFF);
 449
 450         wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
 451                            WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 452                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 453                            WM8350_GPIO_DEBOUNCE_OFF);
 454
 455         wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
 456                            WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 457                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 458                            WM8350_GPIO_DEBOUNCE_OFF);
 459
 460         wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
 461         wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
 462         wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
 463         wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
 464         wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
 465         wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
 466         wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
 467         wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
 468
 469         /* LEDs */
 470         wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
 471                              WM8350_DC5_ERRACT_SHUTDOWN_CONV);
 472         wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
 473                                WM8350_ISINK_FLASH_DISABLE,
 474                                WM8350_ISINK_FLASH_TRIG_BIT,
 475                                WM8350_ISINK_FLASH_DUR_32MS,
 476                                WM8350_ISINK_FLASH_ON_INSTANT,
 477                                WM8350_ISINK_FLASH_OFF_INSTANT,
 478                                WM8350_ISINK_FLASH_MODE_EN);
 479         wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
 480                                WM8350_ISINK_MODE_BOOST,
 481                                WM8350_ISINK_ILIM_NORMAL,
 482                                WM8350_DC5_RMP_20V,
 483                                WM8350_DC5_FBSRC_ISINKA);
 484         wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
 485                             &wm8350_led_data);
 486
 487         wm8350->codec.platform_data = &imx32ads_wm8350_setup;
 488
 489         regulator_has_full_constraints();
 490
 491         return 0;
 492 }
 493
 494 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 495         .init = mx31_wm8350_init,
 496 };
 497 #endif
 498
 499 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 500 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 501         {
 502                 I2C_BOARD_INFO("wm8350", 0x1a),
 503                 .platform_data = &mx31_wm8350_pdata,
 504                 /* irq number is run-time assigned */
 505         },
 506 #endif
 507 };
 508
 509 static void __init mxc_init_i2c(void)
 510 {
 511 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 512         mx31ads_i2c1_devices[0].irq =
 513                         gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 514 #endif
 515         i2c_register_board_info(1, mx31ads_i2c1_devices,
 516                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 517
 518         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
 519         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 520
 521         imx31_add_imx_i2c1(NULL);
 522 }
 523
 524 static unsigned int ssi_pins[] = {
 525         MX31_PIN_SFS5__SFS5,
 526         MX31_PIN_SCK5__SCK5,
 527         MX31_PIN_SRXD5__SRXD5,
 528         MX31_PIN_STXD5__STXD5,
 529 };
 530
 531 static void __init mxc_init_audio(void)
 532 {
 533         imx31_add_imx_ssi(0, NULL);
 534         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 535 }
 536
 537 /*
 538  * Static mappings, starting from the CS4 start address up to the start address
 539  * of the CS8900.
 540  */
 541 static struct map_desc mx31ads_io_desc[] __initdata = {
 542         {
 543                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
 544                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
 545                 .length         = CS4_CS8900_MMIO_START,
 546                 .type           = MT_DEVICE
 547         },
 548 };
 549
 550 static void __init mx31ads_map_io(void)
 551 {
 552         mx31_map_io();
 553         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 554 }
 555
 556 static void __init mx31ads_init_irq(void)
 557 {
 558         mx31_init_irq();
 559         mx31ads_init_expio();
 560 }
 561
 562 static void __init mx31ads_init(void)
 563 {
 564         imx31_soc_init();
 565
 566         mxc_init_extuart();
 567         mxc_init_imx_uart();
 568         mxc_init_i2c();
 569         mxc_init_audio();
 570         mxc_init_ext_ethernet();
 571 }
 572
 573 static void __init mx31ads_timer_init(void)
 574 {
 575         mx31_clocks_init(26000000);
 576 }
 577
 578 static struct sys_timer mx31ads_timer = {
 579         .init   = mx31ads_timer_init,
 580 };
 581
 582 MACHINE_START(MX31ADS, "Freescale MX31ADS")
 583         /* Maintainer: Freescale Semiconductor, Inc. */
 584         .atag_offset = 0x100,
 585         .map_io = mx31ads_map_io,
 586         .init_early = imx31_init_early,
 587         .init_irq = mx31ads_init_irq,
 588         .handle_irq = imx31_handle_irq,
 589         .timer = &mx31ads_timer,
 590         .init_machine = mx31ads_init,
 591         .restart        = mxc_restart,
 592 MACHINE_END