arch/arm/mach-imx/mach-mx51_babbage.c

   1 /*
   2  * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/i2c.h>
  16 #include <linux/gpio.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/input.h>
  20 #include <linux/spi/flash.h>
  21 #include <linux/spi/spi.h>
  22
  23 #include <mach/common.h>
  24 #include <mach/hardware.h>
  25 #include <mach/iomux-mx51.h>
  26
  27 #include <asm/setup.h>
  28 #include <asm/mach-types.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/time.h>
  31
  32 #include "devices-imx51.h"
  33 #include "cpu_op-mx51.h"
  34
  35 #define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
  36 #define BABBAGE_USBH1_STP       IMX_GPIO_NR(1, 27)
  37 #define BABBAGE_USB_PHY_RESET   IMX_GPIO_NR(2, 5)
  38 #define BABBAGE_FEC_PHY_RESET   IMX_GPIO_NR(2, 14)
  39 #define BABBAGE_POWER_KEY       IMX_GPIO_NR(2, 21)
  40 #define BABBAGE_ECSPI1_CS0      IMX_GPIO_NR(4, 24)
  41 #define BABBAGE_ECSPI1_CS1      IMX_GPIO_NR(4, 25)
  42 #define BABBAGE_SD2_CD          IMX_GPIO_NR(1, 6)
  43 #define BABBAGE_SD2_WP          IMX_GPIO_NR(1, 5)
  44
  45 /* USB_CTRL_1 */
  46 #define MX51_USB_CTRL_1_OFFSET                  0x10
  47 #define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
  48
  49 #define MX51_USB_PLLDIV_12_MHZ          0x00
  50 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  51 #define MX51_USB_PLL_DIV_24_MHZ 0x02
  52
  53 static struct gpio_keys_button babbage_buttons[] = {
  54         {
  55                 .gpio           = BABBAGE_POWER_KEY,
  56                 .code           = BTN_0,
  57                 .desc           = "PWR",
  58                 .active_low     = 1,
  59                 .wakeup         = 1,
  60         },
  61 };
  62
  63 static const struct gpio_keys_platform_data imx_button_data __initconst = {
  64         .buttons        = babbage_buttons,
  65         .nbuttons       = ARRAY_SIZE(babbage_buttons),
  66 };
  67
  68 static iomux_v3_cfg_t mx51babbage_pads[] = {
  69         /* UART1 */
  70         MX51_PAD_UART1_RXD__UART1_RXD,
  71         MX51_PAD_UART1_TXD__UART1_TXD,
  72         MX51_PAD_UART1_RTS__UART1_RTS,
  73         MX51_PAD_UART1_CTS__UART1_CTS,
  74
  75         /* UART2 */
  76         MX51_PAD_UART2_RXD__UART2_RXD,
  77         MX51_PAD_UART2_TXD__UART2_TXD,
  78
  79         /* UART3 */
  80         MX51_PAD_EIM_D25__UART3_RXD,
  81         MX51_PAD_EIM_D26__UART3_TXD,
  82         MX51_PAD_EIM_D27__UART3_RTS,
  83         MX51_PAD_EIM_D24__UART3_CTS,
  84
  85         /* I2C1 */
  86         MX51_PAD_EIM_D16__I2C1_SDA,
  87         MX51_PAD_EIM_D19__I2C1_SCL,
  88
  89         /* I2C2 */
  90         MX51_PAD_KEY_COL4__I2C2_SCL,
  91         MX51_PAD_KEY_COL5__I2C2_SDA,
  92
  93         /* HSI2C */
  94         MX51_PAD_I2C1_CLK__I2C1_CLK,
  95         MX51_PAD_I2C1_DAT__I2C1_DAT,
  96
  97         /* USB HOST1 */
  98         MX51_PAD_USBH1_CLK__USBH1_CLK,
  99         MX51_PAD_USBH1_DIR__USBH1_DIR,
 100         MX51_PAD_USBH1_NXT__USBH1_NXT,
 101         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 102         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 103         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 104         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 105         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 106         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 107         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 108         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 109
 110         /* USB HUB reset line*/
 111         MX51_PAD_GPIO1_7__GPIO1_7,
 112
 113         /* USB PHY reset line */
 114         MX51_PAD_EIM_D21__GPIO2_5,
 115
 116         /* FEC */
 117         MX51_PAD_EIM_EB2__FEC_MDIO,
 118         MX51_PAD_EIM_EB3__FEC_RDATA1,
 119         MX51_PAD_EIM_CS2__FEC_RDATA2,
 120         MX51_PAD_EIM_CS3__FEC_RDATA3,
 121         MX51_PAD_EIM_CS4__FEC_RX_ER,
 122         MX51_PAD_EIM_CS5__FEC_CRS,
 123         MX51_PAD_NANDF_RB2__FEC_COL,
 124         MX51_PAD_NANDF_RB3__FEC_RX_CLK,
 125         MX51_PAD_NANDF_D9__FEC_RDATA0,
 126         MX51_PAD_NANDF_D8__FEC_TDATA0,
 127         MX51_PAD_NANDF_CS2__FEC_TX_ER,
 128         MX51_PAD_NANDF_CS3__FEC_MDC,
 129         MX51_PAD_NANDF_CS4__FEC_TDATA1,
 130         MX51_PAD_NANDF_CS5__FEC_TDATA2,
 131         MX51_PAD_NANDF_CS6__FEC_TDATA3,
 132         MX51_PAD_NANDF_CS7__FEC_TX_EN,
 133         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 134
 135         /* FEC PHY reset line */
 136         MX51_PAD_EIM_A20__GPIO2_14,
 137
 138         /* SD 1 */
 139         MX51_PAD_SD1_CMD__SD1_CMD,
 140         MX51_PAD_SD1_CLK__SD1_CLK,
 141         MX51_PAD_SD1_DATA0__SD1_DATA0,
 142         MX51_PAD_SD1_DATA1__SD1_DATA1,
 143         MX51_PAD_SD1_DATA2__SD1_DATA2,
 144         MX51_PAD_SD1_DATA3__SD1_DATA3,
 145         /* CD/WP from controller */
 146         MX51_PAD_GPIO1_0__SD1_CD,
 147         MX51_PAD_GPIO1_1__SD1_WP,
 148
 149         /* SD 2 */
 150         MX51_PAD_SD2_CMD__SD2_CMD,
 151         MX51_PAD_SD2_CLK__SD2_CLK,
 152         MX51_PAD_SD2_DATA0__SD2_DATA0,
 153         MX51_PAD_SD2_DATA1__SD2_DATA1,
 154         MX51_PAD_SD2_DATA2__SD2_DATA2,
 155         MX51_PAD_SD2_DATA3__SD2_DATA3,
 156         /* CD/WP gpio */
 157         MX51_PAD_GPIO1_6__GPIO1_6,
 158         MX51_PAD_GPIO1_5__GPIO1_5,
 159
 160         /* eCSPI1 */
 161         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 162         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
 163         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 164         MX51_PAD_CSPI1_SS0__GPIO4_24,
 165         MX51_PAD_CSPI1_SS1__GPIO4_25,
 166
 167         /* Audio */
 168         MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
 169         MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
 170         MX51_PAD_AUD3_BB_CK__AUD3_TXC,
 171         MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
 172 };
 173
 174 /* Serial ports */
 175 static const struct imxuart_platform_data uart_pdata __initconst = {
 176         .flags = IMXUART_HAVE_RTSCTS,
 177 };
 178
 179 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
 180         .bitrate = 100000,
 181 };
 182
 183 static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
 184         .bitrate = 400000,
 185 };
 186
 187 static struct gpio mx51_babbage_usbh1_gpios[] = {
 188         { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
 189         { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
 190 };
 191
 192 static int gpio_usbh1_active(void)
 193 {
 194         iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
 195         int ret;
 196
 197         /* Set USBH1_STP to GPIO and toggle it */
 198         mxc_iomux_v3_setup_pad(usbh1stp_gpio);
 199         ret = gpio_request_array(mx51_babbage_usbh1_gpios,
 200                                         ARRAY_SIZE(mx51_babbage_usbh1_gpios));
 201
 202         if (ret) {
 203                 pr_debug("failed to get USBH1 pins: %d\n", ret);
 204                 return ret;
 205         }
 206
 207         msleep(100);
 208         gpio_set_value(BABBAGE_USBH1_STP, 1);
 209         gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
 210         gpio_free_array(mx51_babbage_usbh1_gpios,
 211                                         ARRAY_SIZE(mx51_babbage_usbh1_gpios));
 212         return 0;
 213 }
 214
 215 static inline void babbage_usbhub_reset(void)
 216 {
 217         int ret;
 218
 219         /* Reset USB hub */
 220         ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
 221                                         GPIOF_OUT_INIT_LOW, "GPIO1_7");
 222         if (ret) {
 223                 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
 224                 return;
 225         }
 226
 227         msleep(2);
 228         /* Deassert reset */
 229         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 230 }
 231
 232 static inline void babbage_fec_reset(void)
 233 {
 234         int ret;
 235
 236         /* reset FEC PHY */
 237         ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
 238                                         GPIOF_OUT_INIT_LOW, "fec-phy-reset");
 239         if (ret) {
 240                 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
 241                 return;
 242         }
 243         msleep(1);
 244         gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
 245 }
 246
 247 /* This function is board specific as the bit mask for the plldiv will also
 248 be different for other Freescale SoCs, thus a common bitmask is not
 249 possible and cannot get place in /plat-mxc/ehci.c.*/
 250 static int initialize_otg_port(struct platform_device *pdev)
 251 {
 252         u32 v;
 253         void __iomem *usb_base;
 254         void __iomem *usbother_base;
 255
 256         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 257         if (!usb_base)
 258                 return -ENOMEM;
 259         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 260
 261         /* Set the PHY clock to 19.2MHz */
 262         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 263         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 264         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 265         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 266         iounmap(usb_base);
 267
 268         mdelay(10);
 269
 270         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 271 }
 272
 273 static int initialize_usbh1_port(struct platform_device *pdev)
 274 {
 275         u32 v;
 276         void __iomem *usb_base;
 277         void __iomem *usbother_base;
 278
 279         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 280         if (!usb_base)
 281                 return -ENOMEM;
 282         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 283
 284         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 285         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 286         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 287         iounmap(usb_base);
 288
 289         mdelay(10);
 290
 291         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 292                         MXC_EHCI_ITC_NO_THRESHOLD);
 293 }
 294
 295 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
 296         .init           = initialize_otg_port,
 297         .portsc = MXC_EHCI_UTMI_16BIT,
 298 };
 299
 300 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 301         .operating_mode = FSL_USB2_DR_DEVICE,
 302         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 303 };
 304
 305 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
 306         .init           = initialize_usbh1_port,
 307         .portsc = MXC_EHCI_MODE_ULPI,
 308 };
 309
 310 static bool otg_mode_host __initdata;
 311
 312 static int __init babbage_otg_mode(char *options)
 313 {
 314         if (!strcmp(options, "host"))
 315                 otg_mode_host = true;
 316         else if (!strcmp(options, "device"))
 317                 otg_mode_host = false;
 318         else
 319                 pr_info("otg_mode neither \"host\" nor \"device\". "
 320                         "Defaulting to device\n");
 321         return 1;
 322 }
 323 __setup("otg_mode=", babbage_otg_mode);
 324
 325 static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
 326         {
 327                 .modalias = "mtd_dataflash",
 328                 .max_speed_hz = 25000000,
 329                 .bus_num = 0,
 330                 .chip_select = 1,
 331                 .mode = SPI_MODE_0,
 332                 .platform_data = NULL,
 333         },
 334 };
 335
 336 static int mx51_babbage_spi_cs[] = {
 337         BABBAGE_ECSPI1_CS0,
 338         BABBAGE_ECSPI1_CS1,
 339 };
 340
 341 static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
 342         .chipselect     = mx51_babbage_spi_cs,
 343         .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
 344 };
 345
 346 static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
 347         .cd_type = ESDHC_CD_CONTROLLER,
 348         .wp_type = ESDHC_WP_CONTROLLER,
 349 };
 350
 351 static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
 352         .cd_gpio = BABBAGE_SD2_CD,
 353         .wp_gpio = BABBAGE_SD2_WP,
 354         .cd_type = ESDHC_CD_GPIO,
 355         .wp_type = ESDHC_WP_GPIO,
 356 };
 357
 358 void __init imx51_babbage_common_init(void)
 359 {
 360         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
 361                                          ARRAY_SIZE(mx51babbage_pads));
 362 }
 363
 364 /*
 365  * Board specific initialization.
 366  */
 367 static void __init mx51_babbage_init(void)
 368 {
 369         iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
 370         iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
 371                 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
 372
 373         imx51_soc_init();
 374
 375 #if defined(CONFIG_CPU_FREQ_IMX)
 376         get_cpu_op = mx51_get_cpu_op;
 377 #endif
 378         imx51_babbage_common_init();
 379
 380         imx51_add_imx_uart(0, &uart_pdata);
 381         imx51_add_imx_uart(1, NULL);
 382         imx51_add_imx_uart(2, &uart_pdata);
 383
 384         babbage_fec_reset();
 385         imx51_add_fec(NULL);
 386
 387         /* Set the PAD settings for the pwr key. */
 388         mxc_iomux_v3_setup_pad(power_key);
 389         imx_add_gpio_keys(&imx_button_data);
 390
 391         imx51_add_imx_i2c(0, &babbage_i2c_data);
 392         imx51_add_imx_i2c(1, &babbage_i2c_data);
 393         imx51_add_hsi2c(&babbage_hsi2c_data);
 394
 395         if (otg_mode_host)
 396                 imx51_add_mxc_ehci_otg(&dr_utmi_config);
 397         else {
 398                 initialize_otg_port(NULL);
 399                 imx51_add_fsl_usb2_udc(&usb_pdata);
 400         }
 401
 402         gpio_usbh1_active();
 403         imx51_add_mxc_ehci_hs(1, &usbh1_config);
 404         /* setback USBH1_STP to be function */
 405         mxc_iomux_v3_setup_pad(usbh1stp);
 406         babbage_usbhub_reset();
 407
 408         imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
 409         imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
 410
 411         spi_register_board_info(mx51_babbage_spi_board_info,
 412                 ARRAY_SIZE(mx51_babbage_spi_board_info));
 413         imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
 414         imx51_add_imx2_wdt(0);
 415 }
 416
 417 static void __init mx51_babbage_timer_init(void)
 418 {
 419         mx51_clocks_init(32768, 24000000, 22579200, 0);
 420 }
 421
 422 static struct sys_timer mx51_babbage_timer = {
 423         .init = mx51_babbage_timer_init,
 424 };
 425
 426 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
 427         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
 428         .atag_offset = 0x100,
 429         .map_io = mx51_map_io,
 430         .init_early = imx51_init_early,
 431         .init_irq = mx51_init_irq,
 432         .handle_irq = imx51_handle_irq,
 433         .timer = &mx51_babbage_timer,
 434         .init_machine = mx51_babbage_init,
 435         .init_late      = imx51_init_late,
 436         .restart        = mxc_restart,
 437 MACHINE_END