vmalloc: walk vmap_areas by sorted list instead of rb_next()
[linux/fpc-iii.git] / arch / arm / mach-orion5x / rd88f5182-setup.c
blob399130fac0b611cf50e6948d6990b56cc8297fe8
1 /*
2 * arch/arm/mach-orion5x/rd88f5182-setup.c
4 * Marvell Orion-NAS Reference Design Setup
6 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 #include <linux/gpio.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci.h>
17 #include <linux/irq.h>
18 #include <linux/mtd/physmap.h>
19 #include <linux/mv643xx_eth.h>
20 #include <linux/ata_platform.h>
21 #include <linux/i2c.h>
22 #include <asm/mach-types.h>
23 #include <asm/leds.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/pci.h>
26 #include <mach/orion5x.h>
27 #include "common.h"
28 #include "mpp.h"
30 /*****************************************************************************
31 * RD-88F5182 Info
32 ****************************************************************************/
35 * 512K NOR flash Device bus boot chip select
38 #define RD88F5182_NOR_BOOT_BASE 0xf4000000
39 #define RD88F5182_NOR_BOOT_SIZE SZ_512K
42 * 16M NOR flash on Device bus chip select 1
45 #define RD88F5182_NOR_BASE 0xfc000000
46 #define RD88F5182_NOR_SIZE SZ_16M
49 * PCI
52 #define RD88F5182_PCI_SLOT0_OFFS 7
53 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
54 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
57 * GPIO Debug LED
60 #define RD88F5182_GPIO_DBG_LED 0
62 /*****************************************************************************
63 * 16M NOR Flash on Device bus CS1
64 ****************************************************************************/
66 static struct physmap_flash_data rd88f5182_nor_flash_data = {
67 .width = 1,
70 static struct resource rd88f5182_nor_flash_resource = {
71 .flags = IORESOURCE_MEM,
72 .start = RD88F5182_NOR_BASE,
73 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
76 static struct platform_device rd88f5182_nor_flash = {
77 .name = "physmap-flash",
78 .id = 0,
79 .dev = {
80 .platform_data = &rd88f5182_nor_flash_data,
82 .num_resources = 1,
83 .resource = &rd88f5182_nor_flash_resource,
86 #ifdef CONFIG_LEDS
88 /*****************************************************************************
89 * Use GPIO debug led as CPU active indication
90 ****************************************************************************/
92 static void rd88f5182_dbgled_event(led_event_t evt)
94 int val;
96 if (evt == led_idle_end)
97 val = 1;
98 else if (evt == led_idle_start)
99 val = 0;
100 else
101 return;
103 gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
106 static int __init rd88f5182_dbgled_init(void)
108 int pin;
110 if (machine_is_rd88f5182()) {
111 pin = RD88F5182_GPIO_DBG_LED;
113 if (gpio_request(pin, "DBGLED") == 0) {
114 if (gpio_direction_output(pin, 0) != 0) {
115 printk(KERN_ERR "rd88f5182_dbgled_init failed "
116 "to set output pin %d\n", pin);
117 gpio_free(pin);
118 return 0;
120 } else {
121 printk(KERN_ERR "rd88f5182_dbgled_init failed "
122 "to request gpio %d\n", pin);
123 return 0;
126 leds_event = rd88f5182_dbgled_event;
129 return 0;
132 __initcall(rd88f5182_dbgled_init);
134 #endif
136 /*****************************************************************************
137 * PCI
138 ****************************************************************************/
140 void __init rd88f5182_pci_preinit(void)
142 int pin;
145 * Configure PCI GPIO IRQ pins
147 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
148 if (gpio_request(pin, "PCI IntA") == 0) {
149 if (gpio_direction_input(pin) == 0) {
150 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
151 } else {
152 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
153 "set_irq_type pin %d\n", pin);
154 gpio_free(pin);
156 } else {
157 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
160 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
161 if (gpio_request(pin, "PCI IntB") == 0) {
162 if (gpio_direction_input(pin) == 0) {
163 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
164 } else {
165 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
166 "set_irq_type pin %d\n", pin);
167 gpio_free(pin);
169 } else {
170 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
174 static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
175 u8 pin)
177 int irq;
180 * Check for devices with hard-wired IRQs.
182 irq = orion5x_pci_map_irq(dev, slot, pin);
183 if (irq != -1)
184 return irq;
187 * PCI IRQs are connected via GPIOs
189 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
190 case 0:
191 if (pin == 1)
192 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
193 else
194 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
195 default:
196 return -1;
200 static struct hw_pci rd88f5182_pci __initdata = {
201 .nr_controllers = 2,
202 .preinit = rd88f5182_pci_preinit,
203 .setup = orion5x_pci_sys_setup,
204 .scan = orion5x_pci_sys_scan_bus,
205 .map_irq = rd88f5182_pci_map_irq,
208 static int __init rd88f5182_pci_init(void)
210 if (machine_is_rd88f5182())
211 pci_common_init(&rd88f5182_pci);
213 return 0;
216 subsys_initcall(rd88f5182_pci_init);
218 /*****************************************************************************
219 * Ethernet
220 ****************************************************************************/
222 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
223 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
226 /*****************************************************************************
227 * RTC DS1338 on I2C bus
228 ****************************************************************************/
229 static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
230 I2C_BOARD_INFO("ds1338", 0x68),
233 /*****************************************************************************
234 * Sata
235 ****************************************************************************/
236 static struct mv_sata_platform_data rd88f5182_sata_data = {
237 .n_ports = 2,
240 /*****************************************************************************
241 * General Setup
242 ****************************************************************************/
243 static unsigned int rd88f5182_mpp_modes[] __initdata = {
244 MPP0_GPIO, /* Debug Led */
245 MPP1_GPIO, /* Reset Switch */
246 MPP2_UNUSED,
247 MPP3_GPIO, /* RTC Int */
248 MPP4_GPIO,
249 MPP5_GPIO,
250 MPP6_GPIO, /* PCI_intA */
251 MPP7_GPIO, /* PCI_intB */
252 MPP8_UNUSED,
253 MPP9_UNUSED,
254 MPP10_UNUSED,
255 MPP11_UNUSED,
256 MPP12_SATA_LED, /* SATA 0 presence */
257 MPP13_SATA_LED, /* SATA 1 presence */
258 MPP14_SATA_LED, /* SATA 0 active */
259 MPP15_SATA_LED, /* SATA 1 active */
260 MPP16_UNUSED,
261 MPP17_UNUSED,
262 MPP18_UNUSED,
263 MPP19_UNUSED,
267 static void __init rd88f5182_init(void)
270 * Setup basic Orion functions. Need to be called early.
272 orion5x_init();
274 orion5x_mpp_conf(rd88f5182_mpp_modes);
277 * MPP[20] PCI Clock to MV88F5182
278 * MPP[21] PCI Clock to mini PCI CON11
279 * MPP[22] USB 0 over current indication
280 * MPP[23] USB 1 over current indication
281 * MPP[24] USB 1 over current enable
282 * MPP[25] USB 0 over current enable
286 * Configure peripherals.
288 orion5x_ehci0_init();
289 orion5x_ehci1_init();
290 orion5x_eth_init(&rd88f5182_eth_data);
291 orion5x_i2c_init();
292 orion5x_sata_init(&rd88f5182_sata_data);
293 orion5x_uart0_init();
294 orion5x_xor_init();
296 orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
297 RD88F5182_NOR_BOOT_SIZE);
299 orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
300 platform_device_register(&rd88f5182_nor_flash);
302 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
305 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
306 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
307 .atag_offset = 0x100,
308 .init_machine = rd88f5182_init,
309 .map_io = orion5x_map_io,
310 .init_early = orion5x_init_early,
311 .init_irq = orion5x_init_irq,
312 .timer = &orion5x_timer,
313 .restart = orion5x_restart,
314 MACHINE_END