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vmalloc: walk vmap_areas by sorted list instead of rb_next()
[linux/fpc-iii.git] / arch / arm / mach-realview / core.c
blob45868bb43cbd2fbcbfcdfff638dc15f1cbd7d38b
1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/device.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/io.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/gfp.h>
33 #include <linux/clkdev.h>
34 #include <linux/mtd/physmap.h>
35
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/map.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/platform.h>
50 #include <mach/irqs.h>
51 #include <asm/hardware/timer-sp.h>
52
53 #include <plat/clcd.h>
54 #include <plat/sched_clock.h>
55
56 #include "core.h"
57
58 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
59
60 static void realview_flash_set_vpp(struct platform_device *pdev, int on)
61 {
62 u32 val;
63
64 val = __raw_readl(REALVIEW_FLASHCTRL);
65 if (on)
66 val |= REALVIEW_FLASHPROG_FLVPPEN;
67 else
68 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
69 __raw_writel(val, REALVIEW_FLASHCTRL);
70 }
71
72 static struct physmap_flash_data realview_flash_data = {
73 .width = 4,
74 .set_vpp = realview_flash_set_vpp,
75 };
76
77 struct platform_device realview_flash_device = {
78 .name = "physmap-flash",
79 .id = 0,
80 .dev = {
81 .platform_data = &realview_flash_data,
82 },
83 };
84
85 int realview_flash_register(struct resource *res, u32 num)
86 {
87 realview_flash_device.resource = res;
88 realview_flash_device.num_resources = num;
89 return platform_device_register(&realview_flash_device);
90 }
91
92 static struct smsc911x_platform_config smsc911x_config = {
93 .flags = SMSC911X_USE_32BIT,
94 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
95 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
96 .phy_interface = PHY_INTERFACE_MODE_MII,
97 };
98
99 static struct platform_device realview_eth_device = {
100 .name = "smsc911x",
101 .id = 0,
102 .num_resources = 2,
103 };
104
105 int realview_eth_register(const char *name, struct resource *res)
106 {
107 if (name)
108 realview_eth_device.name = name;
109 realview_eth_device.resource = res;
110 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
111 realview_eth_device.dev.platform_data = &smsc911x_config;
112
113 return platform_device_register(&realview_eth_device);
114 }
115
116 struct platform_device realview_usb_device = {
117 .name = "isp1760",
118 .num_resources = 2,
119 };
120
121 int realview_usb_register(struct resource *res)
122 {
123 realview_usb_device.resource = res;
124 return platform_device_register(&realview_usb_device);
125 }
126
127 static struct pata_platform_info pata_platform_data = {
128 .ioport_shift = 1,
129 };
130
131 static struct resource pata_resources[] = {
132 [0] = {
133 .start = REALVIEW_CF_BASE,
134 .end = REALVIEW_CF_BASE + 0xff,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = REALVIEW_CF_BASE + 0x100,
139 .end = REALVIEW_CF_BASE + SZ_4K - 1,
140 .flags = IORESOURCE_MEM,
141 },
142 };
143
144 struct platform_device realview_cf_device = {
145 .name = "pata_platform",
146 .id = -1,
147 .num_resources = ARRAY_SIZE(pata_resources),
148 .resource = pata_resources,
149 .dev = {
150 .platform_data = &pata_platform_data,
151 },
152 };
153
154 static struct resource realview_i2c_resource = {
155 .start = REALVIEW_I2C_BASE,
156 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
157 .flags = IORESOURCE_MEM,
158 };
159
160 struct platform_device realview_i2c_device = {
161 .name = "versatile-i2c",
162 .id = 0,
163 .num_resources = 1,
164 .resource = &realview_i2c_resource,
165 };
166
167 static struct i2c_board_info realview_i2c_board_info[] = {
168 {
169 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
170 },
171 };
172
173 static int __init realview_i2c_init(void)
174 {
175 return i2c_register_board_info(0, realview_i2c_board_info,
176 ARRAY_SIZE(realview_i2c_board_info));
177 }
178 arch_initcall(realview_i2c_init);
179
180 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
181
182 /*
183 * This is only used if GPIOLIB support is disabled
184 */
185 static unsigned int realview_mmc_status(struct device *dev)
186 {
187 struct amba_device *adev = container_of(dev, struct amba_device, dev);
188 u32 mask;
189
190 if (machine_is_realview_pb1176()) {
191 static bool inserted = false;
192
193 /*
194 * The PB1176 does not have the status register,
195 * assume it is inserted at startup, then invert
196 * for each call so card insertion/removal will
197 * be detected anyway. This will not be called if
198 * GPIO on PL061 is active, which is the proper
199 * way to do this on the PB1176.
200 */
201 inserted = !inserted;
202 return inserted ? 0 : 1;
203 }
204
205 if (adev->res.start == REALVIEW_MMCI0_BASE)
206 mask = 1;
207 else
208 mask = 2;
209
210 return readl(REALVIEW_SYSMCI) & mask;
211 }
212
213 struct mmci_platform_data realview_mmc0_plat_data = {
214 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
215 .status = realview_mmc_status,
216 .gpio_wp = 17,
217 .gpio_cd = 16,
218 .cd_invert = true,
219 };
220
221 struct mmci_platform_data realview_mmc1_plat_data = {
222 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
223 .status = realview_mmc_status,
224 .gpio_wp = 19,
225 .gpio_cd = 18,
226 .cd_invert = true,
227 };
228
229 /*
230 * Clock handling
231 */
232 static const struct icst_params realview_oscvco_params = {
233 .ref = 24000000,
234 .vco_max = ICST307_VCO_MAX,
235 .vco_min = ICST307_VCO_MIN,
236 .vd_min = 4 + 8,
237 .vd_max = 511 + 8,
238 .rd_min = 1 + 2,
239 .rd_max = 127 + 2,
240 .s2div = icst307_s2div,
241 .idx2s = icst307_idx2s,
242 };
243
244 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
245 {
246 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
247 u32 val;
248
249 val = readl(clk->vcoreg) & ~0x7ffff;
250 val |= vco.v | (vco.r << 9) | (vco.s << 16);
251
252 writel(0xa05f, sys_lock);
253 writel(val, clk->vcoreg);
254 writel(0, sys_lock);
255 }
256
257 static const struct clk_ops oscvco_clk_ops = {
258 .round = icst_clk_round,
259 .set = icst_clk_set,
260 .setvco = realview_oscvco_set,
261 };
262
263 static struct clk oscvco_clk = {
264 .ops = &oscvco_clk_ops,
265 .params = &realview_oscvco_params,
266 };
267
268 /*
269 * These are fixed clocks.
270 */
271 static struct clk ref24_clk = {
272 .rate = 24000000,
273 };
274
275 static struct clk sp804_clk = {
276 .rate = 1000000,
277 };
278
279 static struct clk dummy_apb_pclk;
280
281 static struct clk_lookup lookups[] = {
282 { /* Bus clock */
283 .con_id = "apb_pclk",
284 .clk = &dummy_apb_pclk,
285 }, { /* UART0 */
286 .dev_id = "dev:uart0",
287 .clk = &ref24_clk,
288 }, { /* UART1 */
289 .dev_id = "dev:uart1",
290 .clk = &ref24_clk,
291 }, { /* UART2 */
292 .dev_id = "dev:uart2",
293 .clk = &ref24_clk,
294 }, { /* UART3 */
295 .dev_id = "fpga:uart3",
296 .clk = &ref24_clk,
297 }, { /* UART3 is on the dev chip in PB1176 */
298 .dev_id = "dev:uart3",
299 .clk = &ref24_clk,
300 }, { /* UART4 only exists in PB1176 */
301 .dev_id = "fpga:uart4",
302 .clk = &ref24_clk,
303 }, { /* KMI0 */
304 .dev_id = "fpga:kmi0",
305 .clk = &ref24_clk,
306 }, { /* KMI1 */
307 .dev_id = "fpga:kmi1",
308 .clk = &ref24_clk,
309 }, { /* MMC0 */
310 .dev_id = "fpga:mmc0",
311 .clk = &ref24_clk,
312 }, { /* CLCD is in the PB1176 and EB DevChip */
313 .dev_id = "dev:clcd",
314 .clk = &oscvco_clk,
315 }, { /* PB:CLCD */
316 .dev_id = "issp:clcd",
317 .clk = &oscvco_clk,
318 }, { /* SSP */
319 .dev_id = "dev:ssp0",
320 .clk = &ref24_clk,
321 }, { /* SP804 timers */
322 .dev_id = "sp804",
323 .clk = &sp804_clk,
324 },
325 };
326
327 void __init realview_init_early(void)
328 {
329 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
330
331 if (machine_is_realview_pb1176())
332 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
333 else
334 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
335
336 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
337
338 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
339 }
340
341 /*
342 * CLCD support.
343 */
344 #define SYS_CLCD_NLCDIOON (1 << 2)
345 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
346 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
347 #define SYS_CLCD_ID_MASK (0x1f << 8)
348 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
349 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
350 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
351 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
352 #define SYS_CLCD_ID_VGA (0x1f << 8)
353
354 /*
355 * Disable all display connectors on the interface module.
356 */
357 static void realview_clcd_disable(struct clcd_fb *fb)
358 {
359 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
360 u32 val;
361
362 val = readl(sys_clcd);
363 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
364 writel(val, sys_clcd);
365 }
366
367 /*
368 * Enable the relevant connector on the interface module.
369 */
370 static void realview_clcd_enable(struct clcd_fb *fb)
371 {
372 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
373 u32 val;
374
375 /*
376 * Enable the PSUs
377 */
378 val = readl(sys_clcd);
379 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
380 writel(val, sys_clcd);
381 }
382
383 /*
384 * Detect which LCD panel is connected, and return the appropriate
385 * clcd_panel structure. Note: we do not have any information on
386 * the required timings for the 8.4in panel, so we presently assume
387 * VGA timings.
388 */
389 static int realview_clcd_setup(struct clcd_fb *fb)
390 {
391 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
392 const char *panel_name, *vga_panel_name;
393 unsigned long framesize;
394 u32 val;
395
396 if (machine_is_realview_eb()) {
397 /* VGA, 16bpp */
398 framesize = 640 * 480 * 2;
399 vga_panel_name = "VGA";
400 } else {
401 /* XVGA, 16bpp */
402 framesize = 1024 * 768 * 2;
403 vga_panel_name = "XVGA";
404 }
405
406 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
407 if (val == SYS_CLCD_ID_SANYO_3_8)
408 panel_name = "Sanyo TM38QV67A02A";
409 else if (val == SYS_CLCD_ID_SANYO_2_5)
410 panel_name = "Sanyo QVGA Portrait";
411 else if (val == SYS_CLCD_ID_EPSON_2_2)
412 panel_name = "Epson L2F50113T00";
413 else if (val == SYS_CLCD_ID_VGA)
414 panel_name = vga_panel_name;
415 else {
416 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
417 panel_name = vga_panel_name;
418 }
419
420 fb->panel = versatile_clcd_get_panel(panel_name);
421 if (!fb->panel)
422 return -EINVAL;
423
424 return versatile_clcd_setup_dma(fb, framesize);
425 }
426
427 struct clcd_board clcd_plat_data = {
428 .name = "RealView",
429 .caps = CLCD_CAP_ALL,
430 .check = clcdfb_check,
431 .decode = clcdfb_decode,
432 .disable = realview_clcd_disable,
433 .enable = realview_clcd_enable,
434 .setup = realview_clcd_setup,
435 .mmap = versatile_clcd_mmap_dma,
436 .remove = versatile_clcd_remove_dma,
437 };
438
439 #ifdef CONFIG_LEDS
440 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
441
442 void realview_leds_event(led_event_t ledevt)
443 {
444 unsigned long flags;
445 u32 val;
446 u32 led = 1 << smp_processor_id();
447
448 local_irq_save(flags);
449 val = readl(VA_LEDS_BASE);
450
451 switch (ledevt) {
452 case led_idle_start:
453 val = val & ~led;
454 break;
455
456 case led_idle_end:
457 val = val | led;
458 break;
459
460 case led_timer:
461 val = val ^ REALVIEW_SYS_LED7;
462 break;
463
464 case led_halted:
465 val = 0;
466 break;
467
468 default:
469 break;
470 }
471
472 writel(val, VA_LEDS_BASE);
473 local_irq_restore(flags);
474 }
475 #endif /* CONFIG_LEDS */
476
477 /*
478 * Where is the timer (VA)?
479 */
480 void __iomem *timer0_va_base;
481 void __iomem *timer1_va_base;
482 void __iomem *timer2_va_base;
483 void __iomem *timer3_va_base;
484
485 /*
486 * Set up the clock source and clock events devices
487 */
488 void __init realview_timer_init(unsigned int timer_irq)
489 {
490 u32 val;
491
492 /*
493 * set clock frequency:
494 * REALVIEW_REFCLK is 32KHz
495 * REALVIEW_TIMCLK is 1MHz
496 */
497 val = readl(__io_address(REALVIEW_SCTL_BASE));
498 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
499 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
500 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
501 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
502 __io_address(REALVIEW_SCTL_BASE));
503
504 /*
505 * Initialise to a known state (all timers off)
506 */
507 writel(0, timer0_va_base + TIMER_CTRL);
508 writel(0, timer1_va_base + TIMER_CTRL);
509 writel(0, timer2_va_base + TIMER_CTRL);
510 writel(0, timer3_va_base + TIMER_CTRL);
511
512 sp804_clocksource_init(timer3_va_base, "timer3");
513 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
514 }
515
516 /*
517 * Setup the memory banks.
518 */
519 void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo)
520 {
521 /*
522 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
523 * Half of this is mirrored at 0.
524 */
525 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
526 meminfo->bank[0].start = 0x70000000;
527 meminfo->bank[0].size = SZ_512M;
528 meminfo->nr_banks = 1;
529 #else
530 meminfo->bank[0].start = 0;
531 meminfo->bank[0].size = SZ_256M;
532 meminfo->nr_banks = 1;
533 #endif
534 }
Linux with added FPC-III support