| blob | 0650bb87c1e3a68feb64f465bf547c2e3de52771 |
1 /*
2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintenance instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020_proc_init()
74 */
75 ENTRY(cpu_arm1020_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020_proc_fin()
80 */
81 ENTRY(cpu_arm1020_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mov pc, lr
88 /*
89 * cpu_arm1020_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98 .pushsection .idmap.text, "ax"
99 ENTRY(cpu_arm1020_reset)
100 mov ip, #0
101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 #ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 #endif
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x1100 @ ...i...s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mov pc, r0
111 ENDPROC(cpu_arm1020_reset)
112 .popsection
114 /*
115 * cpu_arm1020_do_idle()
116 */
117 .align 5
118 ENTRY(cpu_arm1020_do_idle)
119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
120 mov pc, lr
122 /* ================================= CACHE ================================ */
124 .align 5
126 /*
127 * flush_icache_all()
128 *
129 * Unconditionally clean and invalidate the entire icache.
130 */
131 ENTRY(arm1020_flush_icache_all)
132 #ifndef CONFIG_CPU_ICACHE_DISABLE
133 mov r0, #0
134 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 #endif
136 mov pc, lr
137 ENDPROC(arm1020_flush_icache_all)
139 /*
140 * flush_user_cache_all()
141 *
142 * Invalidate all cache entries in a particular address
143 * space.
144 */
145 ENTRY(arm1020_flush_user_cache_all)
146 /* FALLTHROUGH */
147 /*
148 * flush_kern_cache_all()
149 *
150 * Clean and invalidate the entire cache.
151 */
152 ENTRY(arm1020_flush_kern_cache_all)
153 mov r2, #VM_EXEC
154 mov ip, #0
155 __flush_whole_cache:
156 #ifndef CONFIG_CPU_DCACHE_DISABLE
157 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
159 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
160 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 mcr p15, 0, ip, c7, c10, 4 @ drain WB
162 subs r3, r3, #1 << 26
163 bcs 2b @ entries 63 to 0
164 subs r1, r1, #1 << 5
165 bcs 1b @ segments 15 to 0
166 #endif
167 tst r2, #VM_EXEC
168 #ifndef CONFIG_CPU_ICACHE_DISABLE
169 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
170 #endif
171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
172 mov pc, lr
174 /*
175 * flush_user_cache_range(start, end, flags)
176 *
177 * Invalidate a range of cache entries in the specified
178 * address space.
179 *
180 * - start - start address (inclusive)
181 * - end - end address (exclusive)
182 * - flags - vm_flags for this space
183 */
184 ENTRY(arm1020_flush_user_cache_range)
185 mov ip, #0
186 sub r3, r1, r0 @ calculate total size
187 cmp r3, #CACHE_DLIMIT
188 bhs __flush_whole_cache
190 #ifndef CONFIG_CPU_DCACHE_DISABLE
191 mcr p15, 0, ip, c7, c10, 4
192 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
193 mcr p15, 0, ip, c7, c10, 4 @ drain WB
194 add r0, r0, #CACHE_DLINESIZE
195 cmp r0, r1
196 blo 1b
197 #endif
198 tst r2, #VM_EXEC
199 #ifndef CONFIG_CPU_ICACHE_DISABLE
200 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
201 #endif
202 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
203 mov pc, lr
205 /*
206 * coherent_kern_range(start, end)
207 *
208 * Ensure coherency between the Icache and the Dcache in the
209 * region described by start. If you have non-snooping
210 * Harvard caches, you need to implement this function.
211 *
212 * - start - virtual start address
213 * - end - virtual end address
214 */
215 ENTRY(arm1020_coherent_kern_range)
216 /* FALLTRHOUGH */
218 /*
219 * coherent_user_range(start, end)
220 *
221 * Ensure coherency between the Icache and the Dcache in the
222 * region described by start. If you have non-snooping
223 * Harvard caches, you need to implement this function.
224 *
225 * - start - virtual start address
226 * - end - virtual end address
227 */
228 ENTRY(arm1020_coherent_user_range)
229 mov ip, #0
230 bic r0, r0, #CACHE_DLINESIZE - 1
231 mcr p15, 0, ip, c7, c10, 4
232 1:
233 #ifndef CONFIG_CPU_DCACHE_DISABLE
234 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
235 mcr p15, 0, ip, c7, c10, 4 @ drain WB
236 #endif
237 #ifndef CONFIG_CPU_ICACHE_DISABLE
238 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
239 #endif
240 add r0, r0, #CACHE_DLINESIZE
241 cmp r0, r1
242 blo 1b
243 mcr p15, 0, ip, c7, c10, 4 @ drain WB
244 mov r0, #0
245 mov pc, lr
247 /*
248 * flush_kern_dcache_area(void *addr, size_t size)
249 *
250 * Ensure no D cache aliasing occurs, either with itself or
251 * the I cache
252 *
253 * - addr - kernel address
254 * - size - region size
255 */
256 ENTRY(arm1020_flush_kern_dcache_area)
257 mov ip, #0
258 #ifndef CONFIG_CPU_DCACHE_DISABLE
259 add r1, r0, r1
260 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
261 mcr p15, 0, ip, c7, c10, 4 @ drain WB
262 add r0, r0, #CACHE_DLINESIZE
263 cmp r0, r1
264 blo 1b
265 #endif
266 mcr p15, 0, ip, c7, c10, 4 @ drain WB
267 mov pc, lr
269 /*
270 * dma_inv_range(start, end)
271 *
272 * Invalidate (discard) the specified virtual address range.
273 * May not write back any entries. If 'start' or 'end'
274 * are not cache line aligned, those lines must be written
275 * back.
276 *
277 * - start - virtual start address
278 * - end - virtual end address
279 *
280 * (same as v4wb)
281 */
282 arm1020_dma_inv_range:
283 mov ip, #0
284 #ifndef CONFIG_CPU_DCACHE_DISABLE
285 tst r0, #CACHE_DLINESIZE - 1
286 bic r0, r0, #CACHE_DLINESIZE - 1
287 mcrne p15, 0, ip, c7, c10, 4
288 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
289 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
290 tst r1, #CACHE_DLINESIZE - 1
291 mcrne p15, 0, ip, c7, c10, 4
292 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
293 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
294 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
295 add r0, r0, #CACHE_DLINESIZE
296 cmp r0, r1
297 blo 1b
298 #endif
299 mcr p15, 0, ip, c7, c10, 4 @ drain WB
300 mov pc, lr
302 /*
303 * dma_clean_range(start, end)
304 *
305 * Clean the specified virtual address range.
306 *
307 * - start - virtual start address
308 * - end - virtual end address
309 *
310 * (same as v4wb)
311 */
312 arm1020_dma_clean_range:
313 mov ip, #0
314 #ifndef CONFIG_CPU_DCACHE_DISABLE
315 bic r0, r0, #CACHE_DLINESIZE - 1
316 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
317 mcr p15, 0, ip, c7, c10, 4 @ drain WB
318 add r0, r0, #CACHE_DLINESIZE
319 cmp r0, r1
320 blo 1b
321 #endif
322 mcr p15, 0, ip, c7, c10, 4 @ drain WB
323 mov pc, lr
325 /*
326 * dma_flush_range(start, end)
327 *
328 * Clean and invalidate the specified virtual address range.
329 *
330 * - start - virtual start address
331 * - end - virtual end address
332 */
333 ENTRY(arm1020_dma_flush_range)
334 mov ip, #0
335 #ifndef CONFIG_CPU_DCACHE_DISABLE
336 bic r0, r0, #CACHE_DLINESIZE - 1
337 mcr p15, 0, ip, c7, c10, 4
338 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
339 mcr p15, 0, ip, c7, c10, 4 @ drain WB
340 add r0, r0, #CACHE_DLINESIZE
341 cmp r0, r1
342 blo 1b
343 #endif
344 mcr p15, 0, ip, c7, c10, 4 @ drain WB
345 mov pc, lr
347 /*
348 * dma_map_area(start, size, dir)
349 * - start - kernel virtual start address
350 * - size - size of region
351 * - dir - DMA direction
352 */
353 ENTRY(arm1020_dma_map_area)
354 add r1, r1, r0
355 cmp r2, #DMA_TO_DEVICE
356 beq arm1020_dma_clean_range
357 bcs arm1020_dma_inv_range
358 b arm1020_dma_flush_range
359 ENDPROC(arm1020_dma_map_area)
361 /*
362 * dma_unmap_area(start, size, dir)
363 * - start - kernel virtual start address
364 * - size - size of region
365 * - dir - DMA direction
366 */
367 ENTRY(arm1020_dma_unmap_area)
368 mov pc, lr
369 ENDPROC(arm1020_dma_unmap_area)
371 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
372 define_cache_functions arm1020
374 .align 5
375 ENTRY(cpu_arm1020_dcache_clean_area)
376 #ifndef CONFIG_CPU_DCACHE_DISABLE
377 mov ip, #0
378 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 mcr p15, 0, ip, c7, c10, 4 @ drain WB
380 add r0, r0, #CACHE_DLINESIZE
381 subs r1, r1, #CACHE_DLINESIZE
382 bhi 1b
383 #endif
384 mov pc, lr
386 /* =============================== PageTable ============================== */
388 /*
389 * cpu_arm1020_switch_mm(pgd)
390 *
391 * Set the translation base pointer to be as described by pgd.
392 *
393 * pgd: new page tables
394 */
395 .align 5
396 ENTRY(cpu_arm1020_switch_mm)
397 #ifdef CONFIG_MMU
398 #ifndef CONFIG_CPU_DCACHE_DISABLE
399 mcr p15, 0, r3, c7, c10, 4
400 mov r1, #0xF @ 16 segments
401 1: mov r3, #0x3F @ 64 entries
402 2: mov ip, r3, LSL #26 @ shift up entry
403 orr ip, ip, r1, LSL #5 @ shift in/up index
404 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
405 mov ip, #0
406 mcr p15, 0, ip, c7, c10, 4
407 subs r3, r3, #1
408 cmp r3, #0
409 bge 2b @ entries 3F to 0
410 subs r1, r1, #1
411 cmp r1, #0
412 bge 1b @ segments 15 to 0
414 #endif
415 mov r1, #0
416 #ifndef CONFIG_CPU_ICACHE_DISABLE
417 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
418 #endif
419 mcr p15, 0, r1, c7, c10, 4 @ drain WB
420 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
421 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
422 #endif /* CONFIG_MMU */
423 mov pc, lr
425 /*
426 * cpu_arm1020_set_pte(ptep, pte)
427 *
428 * Set a PTE and flush it out
429 */
430 .align 5
431 ENTRY(cpu_arm1020_set_pte_ext)
432 #ifdef CONFIG_MMU
433 armv3_set_pte_ext
434 mov r0, r0
435 #ifndef CONFIG_CPU_DCACHE_DISABLE
436 mcr p15, 0, r0, c7, c10, 4
437 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
438 #endif
439 mcr p15, 0, r0, c7, c10, 4 @ drain WB
440 #endif /* CONFIG_MMU */
441 mov pc, lr
443 __CPUINIT
445 .type __arm1020_setup, #function
446 __arm1020_setup:
447 mov r0, #0
448 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
449 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
450 #ifdef CONFIG_MMU
451 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
452 #endif
454 adr r5, arm1020_crval
455 ldmia r5, {r5, r6}
456 mrc p15, 0, r0, c1, c0 @ get control register v4
457 bic r0, r0, r5
458 orr r0, r0, r6
459 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
460 orr r0, r0, #0x4000 @ .R.. .... .... ....
461 #endif
462 mov pc, lr
463 .size __arm1020_setup, . - __arm1020_setup
465 /*
466 * R
467 * .RVI ZFRS BLDP WCAM
468 * .011 1001 ..11 0101
469 */
470 .type arm1020_crval, #object
471 arm1020_crval:
472 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
474 __INITDATA
475 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
476 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
479 .section ".rodata"
481 string cpu_arch_name, "armv5t"
482 string cpu_elf_name, "v5"
484 .type cpu_arm1020_name, #object
485 cpu_arm1020_name:
486 .ascii "ARM1020"
487 #ifndef CONFIG_CPU_ICACHE_DISABLE
488 .ascii "i"
489 #endif
490 #ifndef CONFIG_CPU_DCACHE_DISABLE
491 .ascii "d"
492 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
493 .ascii "(wt)"
494 #else
495 .ascii "(wb)"
496 #endif
497 #endif
498 #ifndef CONFIG_CPU_BPREDICT_DISABLE
499 .ascii "B"
500 #endif
501 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
502 .ascii "RR"
503 #endif
504 .ascii "\0"
505 .size cpu_arm1020_name, . - cpu_arm1020_name
507 .align
509 .section ".proc.info.init", #alloc, #execinstr
511 .type __arm1020_proc_info,#object
512 __arm1020_proc_info:
513 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
514 .long 0xff0ffff0
515 .long PMD_TYPE_SECT | \
516 PMD_SECT_AP_WRITE | \
517 PMD_SECT_AP_READ
518 .long PMD_TYPE_SECT | \
519 PMD_SECT_AP_WRITE | \
520 PMD_SECT_AP_READ
521 b __arm1020_setup
522 .long cpu_arch_name
523 .long cpu_elf_name
524 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
525 .long cpu_arm1020_name
526 .long arm1020_processor_functions
527 .long v4wbi_tlb_fns
528 .long v4wb_user_fns
529 .long arm1020_cache_fns
530 .size __arm1020_proc_info, . - __arm1020_proc_info