arch/blackfin/mach-common/clocks-init.c

   1 /*
   2  * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/linkage.h>
  10 #include <linux/init.h>
  11 #include <asm/blackfin.h>
  12
  13 #include <asm/dma.h>
  14 #include <asm/clocks.h>
  15 #include <asm/mem_init.h>
  16 #include <asm/dpmc.h>
  17
  18 #ifdef CONFIG_BF60x
  19
  20 #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
  21 #define CGU_DIV_VAL \
  22         ((CONFIG_CCLK_DIV   << CSEL_OFFSET)   | \
  23         (CONFIG_SCLK_DIV << SYSSEL_OFFSET)   | \
  24         (CONFIG_SCLK0_DIV  << S0SEL_OFFSET)  | \
  25         (CONFIG_SCLK1_DIV  << S1SEL_OFFSET)  | \
  26         (CONFIG_DCLK_DIV   << DSEL_OFFSET))
  27
  28 #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
  29 #if ((CONFIG_BFIN_DCLK != 125) && \
  30         (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
  31         (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
  32         (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
  33 #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  34 #endif
  35
  36 #else
  37 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
  38 #define PLL_CTL_VAL \
  39         (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
  40                 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
  41 #endif
  42
  43 __attribute__((l1_text))
  44 static void do_sync(void)
  45 {
  46         __builtin_bfin_ssync();
  47 }
  48
  49 __attribute__((l1_text))
  50 void init_clocks(void)
  51 {
  52         /* Kill any active DMAs as they may trigger external memory accesses
  53          * in the middle of reprogramming things, and that'll screw us up.
  54          * For example, any automatic DMAs left by U-Boot for splash screens.
  55          */
  56 #ifdef CONFIG_BF60x
  57         init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
  58         init_dmc(CONFIG_BFIN_DCLK);
  59 #else
  60         size_t i;
  61         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
  62                 struct dma_register *dma = dma_io_base_addr[i];
  63                 dma->cfg = 0;
  64         }
  65
  66         do_sync();
  67
  68 #ifdef SIC_IWR0
  69         bfin_write_SIC_IWR0(IWR_ENABLE(0));
  70 # ifdef SIC_IWR1
  71         /* BF52x system reset does not properly reset SIC_IWR1 which
  72          * will screw up the bootrom as it relies on MDMA0/1 waking it
  73          * up from IDLE instructions.  See this report for more info:
  74          * http://blackfin.uclinux.org/gf/tracker/4323
  75          */
  76         if (ANOMALY_05000435)
  77                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  78         else
  79                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  80 # endif
  81 # ifdef SIC_IWR2
  82         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  83 # endif
  84 #else
  85         bfin_write_SIC_IWR(IWR_ENABLE(0));
  86 #endif
  87         do_sync();
  88 #ifdef EBIU_SDGCTL
  89         bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
  90         do_sync();
  91 #endif
  92
  93 #ifdef CLKBUFOE
  94         bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
  95         do_sync();
  96         __asm__ __volatile__("IDLE;");
  97 #endif
  98         bfin_write_PLL_LOCKCNT(0x300);
  99         do_sync();
 100         /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
 101         bfin_write16(PLL_CTL, PLL_CTL_VAL);
 102         __asm__ __volatile__("IDLE;");
 103         bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
 104 #ifdef EBIU_SDGCTL
 105         bfin_write_EBIU_SDRRC(mem_SDRRC);
 106         bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
 107 #else
 108         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 109         do_sync();
 110         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
 111         bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
 112         bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
 113         bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
 114 #ifdef CONFIG_MEM_EBIU_DDRQUE
 115         bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
 116 #endif
 117 #endif
 118 #endif
 119         do_sync();
 120         bfin_read16(0);
 121
 122 }