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[linux/fpc-iii.git] / arch / mn10300 / kernel / mn10300-serial.c
blob339cef4c82568a13ac20de767f066a6e1d95f035
1 /* MN10300 On-chip serial port UART driver
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11
12 static const char serial_name[] = "MN10300 Serial driver";
13 static const char serial_version[] = "mn10300_serial-1.0";
14 static const char serial_revdate[] = "2007-11-06";
15
16 #if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
17 #define SUPPORT_SYSRQ
18 #endif
19
20 #include <linux/module.h>
21 #include <linux/serial.h>
22 #include <linux/circ_buf.h>
23 #include <linux/errno.h>
24 #include <linux/signal.h>
25 #include <linux/sched.h>
26 #include <linux/timer.h>
27 #include <linux/interrupt.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/ioport.h>
33 #include <linux/mm.h>
34 #include <linux/slab.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/bitops.h>
42 #include <asm/serial-regs.h>
43 #include <unit/timex.h>
44 #include "mn10300-serial.h"
45
46 #ifdef CONFIG_SMP
47 #undef GxICR
48 #define GxICR(X) CROSS_GxICR(X, 0)
49 #endif /* CONFIG_SMP */
50
51 #define kenter(FMT, ...) \
52 printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
53 #define _enter(FMT, ...) \
54 no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
55 #define kdebug(FMT, ...) \
56 printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
57 #define _debug(FMT, ...) \
58 no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
59 #define kproto(FMT, ...) \
60 printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
61 #define _proto(FMT, ...) \
62 no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
63
64 #ifndef CODMSB
65 /* c_cflag bit meaning */
66 #define CODMSB 004000000000 /* change Transfer bit-order */
67 #endif
68
69 #define NR_UARTS 3
70
71 #ifdef CONFIG_MN10300_TTYSM_CONSOLE
72 static void mn10300_serial_console_write(struct console *co,
73 const char *s, unsigned count);
74 static int __init mn10300_serial_console_setup(struct console *co,
75 char *options);
76
77 static struct uart_driver mn10300_serial_driver;
78 static struct console mn10300_serial_console = {
79 .name = "ttySM",
80 .write = mn10300_serial_console_write,
81 .device = uart_console_device,
82 .setup = mn10300_serial_console_setup,
83 .flags = CON_PRINTBUFFER,
84 .index = -1,
85 .data = &mn10300_serial_driver,
86 };
87 #endif
88
89 static struct uart_driver mn10300_serial_driver = {
90 .owner = NULL,
91 .driver_name = "mn10300-serial",
92 .dev_name = "ttySM",
93 .major = TTY_MAJOR,
94 .minor = 128,
95 .nr = NR_UARTS,
96 #ifdef CONFIG_MN10300_TTYSM_CONSOLE
97 .cons = &mn10300_serial_console,
98 #endif
99 };
100
101 static unsigned int mn10300_serial_tx_empty(struct uart_port *);
102 static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl);
103 static unsigned int mn10300_serial_get_mctrl(struct uart_port *);
104 static void mn10300_serial_stop_tx(struct uart_port *);
105 static void mn10300_serial_start_tx(struct uart_port *);
106 static void mn10300_serial_send_xchar(struct uart_port *, char ch);
107 static void mn10300_serial_stop_rx(struct uart_port *);
108 static void mn10300_serial_enable_ms(struct uart_port *);
109 static void mn10300_serial_break_ctl(struct uart_port *, int ctl);
110 static int mn10300_serial_startup(struct uart_port *);
111 static void mn10300_serial_shutdown(struct uart_port *);
112 static void mn10300_serial_set_termios(struct uart_port *,
113 struct ktermios *new,
114 struct ktermios *old);
115 static const char *mn10300_serial_type(struct uart_port *);
116 static void mn10300_serial_release_port(struct uart_port *);
117 static int mn10300_serial_request_port(struct uart_port *);
118 static void mn10300_serial_config_port(struct uart_port *, int);
119 static int mn10300_serial_verify_port(struct uart_port *,
120 struct serial_struct *);
121 #ifdef CONFIG_CONSOLE_POLL
122 static void mn10300_serial_poll_put_char(struct uart_port *, unsigned char);
123 static int mn10300_serial_poll_get_char(struct uart_port *);
124 #endif
125
126 static const struct uart_ops mn10300_serial_ops = {
127 .tx_empty = mn10300_serial_tx_empty,
128 .set_mctrl = mn10300_serial_set_mctrl,
129 .get_mctrl = mn10300_serial_get_mctrl,
130 .stop_tx = mn10300_serial_stop_tx,
131 .start_tx = mn10300_serial_start_tx,
132 .send_xchar = mn10300_serial_send_xchar,
133 .stop_rx = mn10300_serial_stop_rx,
134 .enable_ms = mn10300_serial_enable_ms,
135 .break_ctl = mn10300_serial_break_ctl,
136 .startup = mn10300_serial_startup,
137 .shutdown = mn10300_serial_shutdown,
138 .set_termios = mn10300_serial_set_termios,
139 .type = mn10300_serial_type,
140 .release_port = mn10300_serial_release_port,
141 .request_port = mn10300_serial_request_port,
142 .config_port = mn10300_serial_config_port,
143 .verify_port = mn10300_serial_verify_port,
144 #ifdef CONFIG_CONSOLE_POLL
145 .poll_put_char = mn10300_serial_poll_put_char,
146 .poll_get_char = mn10300_serial_poll_get_char,
147 #endif
148 };
149
150 static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id);
151
152 /*
153 * the first on-chip serial port: ttySM0 (aka SIF0)
154 */
155 #ifdef CONFIG_MN10300_TTYSM0
156 struct mn10300_serial_port mn10300_serial_port_sif0 = {
157 .uart.ops = &mn10300_serial_ops,
158 .uart.membase = (void __iomem *) &SC0CTR,
159 .uart.mapbase = (unsigned long) &SC0CTR,
160 .uart.iotype = UPIO_MEM,
161 .uart.irq = 0,
162 .uart.uartclk = 0, /* MN10300_IOCLK, */
163 .uart.fifosize = 1,
164 .uart.flags = UPF_BOOT_AUTOCONF,
165 .uart.line = 0,
166 .uart.type = PORT_MN10300,
167 .uart.lock =
168 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock),
169 .name = "ttySM0",
170 ._iobase = &SC0CTR,
171 ._control = &SC0CTR,
172 ._status = (volatile u8 *)&SC0STR,
173 ._intr = &SC0ICR,
174 ._rxb = &SC0RXB,
175 ._txb = &SC0TXB,
176 .rx_name = "ttySM0:Rx",
177 .tx_name = "ttySM0:Tx",
178 #if defined(CONFIG_MN10300_TTYSM0_TIMER8)
179 .tm_name = "ttySM0:Timer8",
180 ._tmxmd = &TM8MD,
181 ._tmxbr = &TM8BR,
182 ._tmicr = &TM8ICR,
183 .tm_irq = TM8IRQ,
184 .div_timer = MNSCx_DIV_TIMER_16BIT,
185 #elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
186 .tm_name = "ttySM0:Timer0",
187 ._tmxmd = &TM0MD,
188 ._tmxbr = (volatile u16 *)&TM0BR,
189 ._tmicr = &TM0ICR,
190 .tm_irq = TM0IRQ,
191 .div_timer = MNSCx_DIV_TIMER_8BIT,
192 #elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
193 .tm_name = "ttySM0:Timer2",
194 ._tmxmd = &TM2MD,
195 ._tmxbr = (volatile u16 *)&TM2BR,
196 ._tmicr = &TM2ICR,
197 .tm_irq = TM2IRQ,
198 .div_timer = MNSCx_DIV_TIMER_8BIT,
199 #else
200 #error "Unknown config for ttySM0"
201 #endif
202 .rx_irq = SC0RXIRQ,
203 .tx_irq = SC0TXIRQ,
204 .rx_icr = &GxICR(SC0RXIRQ),
205 .tx_icr = &GxICR(SC0TXIRQ),
206 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
207 .options = 0,
208 #ifdef CONFIG_GDBSTUB_ON_TTYSM0
209 .gdbstub = 1,
210 #endif
211 };
212 #endif /* CONFIG_MN10300_TTYSM0 */
213
214 /*
215 * the second on-chip serial port: ttySM1 (aka SIF1)
216 */
217 #ifdef CONFIG_MN10300_TTYSM1
218 struct mn10300_serial_port mn10300_serial_port_sif1 = {
219 .uart.ops = &mn10300_serial_ops,
220 .uart.membase = (void __iomem *) &SC1CTR,
221 .uart.mapbase = (unsigned long) &SC1CTR,
222 .uart.iotype = UPIO_MEM,
223 .uart.irq = 0,
224 .uart.uartclk = 0, /* MN10300_IOCLK, */
225 .uart.fifosize = 1,
226 .uart.flags = UPF_BOOT_AUTOCONF,
227 .uart.line = 1,
228 .uart.type = PORT_MN10300,
229 .uart.lock =
230 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock),
231 .name = "ttySM1",
232 ._iobase = &SC1CTR,
233 ._control = &SC1CTR,
234 ._status = (volatile u8 *)&SC1STR,
235 ._intr = &SC1ICR,
236 ._rxb = &SC1RXB,
237 ._txb = &SC1TXB,
238 .rx_name = "ttySM1:Rx",
239 .tx_name = "ttySM1:Tx",
240 #if defined(CONFIG_MN10300_TTYSM1_TIMER9)
241 .tm_name = "ttySM1:Timer9",
242 ._tmxmd = &TM9MD,
243 ._tmxbr = &TM9BR,
244 ._tmicr = &TM9ICR,
245 .tm_irq = TM9IRQ,
246 .div_timer = MNSCx_DIV_TIMER_16BIT,
247 #elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
248 .tm_name = "ttySM1:Timer3",
249 ._tmxmd = &TM3MD,
250 ._tmxbr = (volatile u16 *)&TM3BR,
251 ._tmicr = &TM3ICR,
252 .tm_irq = TM3IRQ,
253 .div_timer = MNSCx_DIV_TIMER_8BIT,
254 #elif defined(CONFIG_MN10300_TTYSM1_TIMER12)
255 .tm_name = "ttySM1/Timer12",
256 ._tmxmd = &TM12MD,
257 ._tmxbr = &TM12BR,
258 ._tmicr = &TM12ICR,
259 .tm_irq = TM12IRQ,
260 .div_timer = MNSCx_DIV_TIMER_16BIT,
261 #else
262 #error "Unknown config for ttySM1"
263 #endif
264 .rx_irq = SC1RXIRQ,
265 .tx_irq = SC1TXIRQ,
266 .rx_icr = &GxICR(SC1RXIRQ),
267 .tx_icr = &GxICR(SC1TXIRQ),
268 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
269 .options = 0,
270 #ifdef CONFIG_GDBSTUB_ON_TTYSM1
271 .gdbstub = 1,
272 #endif
273 };
274 #endif /* CONFIG_MN10300_TTYSM1 */
275
276 /*
277 * the third on-chip serial port: ttySM2 (aka SIF2)
278 */
279 #ifdef CONFIG_MN10300_TTYSM2
280 struct mn10300_serial_port mn10300_serial_port_sif2 = {
281 .uart.ops = &mn10300_serial_ops,
282 .uart.membase = (void __iomem *) &SC2CTR,
283 .uart.mapbase = (unsigned long) &SC2CTR,
284 .uart.iotype = UPIO_MEM,
285 .uart.irq = 0,
286 .uart.uartclk = 0, /* MN10300_IOCLK, */
287 .uart.fifosize = 1,
288 .uart.flags = UPF_BOOT_AUTOCONF,
289 .uart.line = 2,
290 #ifdef CONFIG_MN10300_TTYSM2_CTS
291 .uart.type = PORT_MN10300_CTS,
292 #else
293 .uart.type = PORT_MN10300,
294 #endif
295 .uart.lock =
296 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
297 .name = "ttySM2",
298 ._iobase = &SC2CTR,
299 ._control = &SC2CTR,
300 ._status = (volatile u8 *)&SC2STR,
301 ._intr = &SC2ICR,
302 ._rxb = &SC2RXB,
303 ._txb = &SC2TXB,
304 .rx_name = "ttySM2:Rx",
305 .tx_name = "ttySM2:Tx",
306 #if defined(CONFIG_MN10300_TTYSM2_TIMER10)
307 .tm_name = "ttySM2/Timer10",
308 ._tmxmd = &TM10MD,
309 ._tmxbr = &TM10BR,
310 ._tmicr = &TM10ICR,
311 .tm_irq = TM10IRQ,
312 .div_timer = MNSCx_DIV_TIMER_16BIT,
313 #elif defined(CONFIG_MN10300_TTYSM2_TIMER9)
314 .tm_name = "ttySM2/Timer9",
315 ._tmxmd = &TM9MD,
316 ._tmxbr = &TM9BR,
317 ._tmicr = &TM9ICR,
318 .tm_irq = TM9IRQ,
319 .div_timer = MNSCx_DIV_TIMER_16BIT,
320 #elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
321 .tm_name = "ttySM2/Timer1",
322 ._tmxmd = &TM1MD,
323 ._tmxbr = (volatile u16 *)&TM1BR,
324 ._tmicr = &TM1ICR,
325 .tm_irq = TM1IRQ,
326 .div_timer = MNSCx_DIV_TIMER_8BIT,
327 #elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
328 .tm_name = "ttySM2/Timer3",
329 ._tmxmd = &TM3MD,
330 ._tmxbr = (volatile u16 *)&TM3BR,
331 ._tmicr = &TM3ICR,
332 .tm_irq = TM3IRQ,
333 .div_timer = MNSCx_DIV_TIMER_8BIT,
334 #else
335 #error "Unknown config for ttySM2"
336 #endif
337 .rx_irq = SC2RXIRQ,
338 .tx_irq = SC2TXIRQ,
339 .rx_icr = &GxICR(SC2RXIRQ),
340 .tx_icr = &GxICR(SC2TXIRQ),
341 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
342 #ifdef CONFIG_MN10300_TTYSM2_CTS
343 .options = MNSCx_OPT_CTS,
344 #else
345 .options = 0,
346 #endif
347 #ifdef CONFIG_GDBSTUB_ON_TTYSM2
348 .gdbstub = 1,
349 #endif
350 };
351 #endif /* CONFIG_MN10300_TTYSM2 */
352
353
354 /*
355 * list of available serial ports
356 */
357 struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = {
358 #ifdef CONFIG_MN10300_TTYSM0
359 [0] = &mn10300_serial_port_sif0,
360 #endif
361 #ifdef CONFIG_MN10300_TTYSM1
362 [1] = &mn10300_serial_port_sif1,
363 #endif
364 #ifdef CONFIG_MN10300_TTYSM2
365 [2] = &mn10300_serial_port_sif2,
366 #endif
367 [NR_UARTS] = NULL,
368 };
369
370
371 /*
372 * we abuse the serial ports' baud timers' interrupt lines to get the ability
373 * to deliver interrupts to userspace as we use the ports' interrupt lines to
374 * do virtual DMA on account of the ports having no hardware FIFOs
375 *
376 * we can generate an interrupt manually in the assembly stubs by writing to
377 * the enable and detect bits in the interrupt control register, so all we need
378 * to do here is disable the interrupt line
379 *
380 * note that we can't just leave the line enabled as the baud rate timer *also*
381 * generates interrupts
382 */
383 static void mn10300_serial_mask_ack(unsigned int irq)
384 {
385 unsigned long flags;
386 u16 tmp;
387
388 flags = arch_local_cli_save();
389 GxICR(irq) = GxICR_LEVEL_6;
390 tmp = GxICR(irq); /* flush write buffer */
391 arch_local_irq_restore(flags);
392 }
393
394 static void mn10300_serial_chip_mask_ack(struct irq_data *d)
395 {
396 mn10300_serial_mask_ack(d->irq);
397 }
398
399 static void mn10300_serial_nop(struct irq_data *d)
400 {
401 }
402
403 static struct irq_chip mn10300_serial_pic = {
404 .name = "mnserial",
405 .irq_ack = mn10300_serial_chip_mask_ack,
406 .irq_mask = mn10300_serial_chip_mask_ack,
407 .irq_mask_ack = mn10300_serial_chip_mask_ack,
408 .irq_unmask = mn10300_serial_nop,
409 };
410
411
412 /*
413 * serial virtual DMA interrupt jump table
414 */
415 struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS];
416
417 static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port)
418 {
419 unsigned long flags;
420 u16 x;
421
422 flags = arch_local_cli_save();
423 *port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
424 x = *port->tx_icr;
425 arch_local_irq_restore(flags);
426 }
427
428 static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port)
429 {
430 unsigned long flags;
431 u16 x;
432
433 flags = arch_local_cli_save();
434 *port->tx_icr =
435 NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) | GxICR_ENABLE;
436 x = *port->tx_icr;
437 arch_local_irq_restore(flags);
438 }
439
440 static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port)
441 {
442 unsigned long flags;
443 u16 x;
444
445 flags = arch_local_cli_save();
446 *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
447 x = *port->rx_icr;
448 arch_local_irq_restore(flags);
449 }
450
451 /*
452 * multi-bit equivalent of test_and_clear_bit()
453 */
454 static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
455 {
456 u32 epsw;
457 asm volatile(" bclr %1,(%2) \n"
458 " mov epsw,%0 \n"
459 : "=d"(epsw) : "d"(mask), "a"(ptr)
460 : "cc", "memory");
461 return !(epsw & EPSW_FLAG_Z);
462 }
463
464 /*
465 * receive chars from the ring buffer for this serial port
466 * - must do break detection here (not done in the UART)
467 */
468 static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port)
469 {
470 struct uart_icount *icount = &port->uart.icount;
471 struct tty_struct *tty = port->uart.state->port.tty;
472 unsigned ix;
473 int count;
474 u8 st, ch, push, status, overrun;
475
476 _enter("%s", port->name);
477
478 push = 0;
479
480 count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE);
481 count = tty_buffer_request_room(tty, count);
482 if (count == 0) {
483 if (!tty->low_latency)
484 tty_flip_buffer_push(tty);
485 return;
486 }
487
488 try_again:
489 /* pull chars out of the hat */
490 ix = port->rx_outp;
491 if (ix == port->rx_inp) {
492 if (push && !tty->low_latency)
493 tty_flip_buffer_push(tty);
494 return;
495 }
496
497 ch = port->rx_buffer[ix++];
498 st = port->rx_buffer[ix++];
499 smp_rmb();
500 port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
501 port->uart.icount.rx++;
502
503 st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF;
504 status = 0;
505 overrun = 0;
506
507 /* the UART doesn't detect BREAK, so we have to do that ourselves
508 * - it starts as a framing error on a NUL character
509 * - then we count another two NUL characters before issuing TTY_BREAK
510 * - then we end on a normal char or one that has all the bottom bits
511 * zero and the top bits set
512 */
513 switch (port->rx_brk) {
514 case 0:
515 /* not breaking at the moment */
516 break;
517
518 case 1:
519 if (st & SC01STR_FEF && ch == 0) {
520 port->rx_brk = 2;
521 goto try_again;
522 }
523 goto not_break;
524
525 case 2:
526 if (st & SC01STR_FEF && ch == 0) {
527 port->rx_brk = 3;
528 _proto("Rx Break Detected");
529 icount->brk++;
530 if (uart_handle_break(&port->uart))
531 goto ignore_char;
532 status |= 1 << TTY_BREAK;
533 goto insert;
534 }
535 goto not_break;
536
537 default:
538 if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
539 goto try_again; /* still breaking */
540
541 port->rx_brk = 0; /* end of the break */
542
543 switch (ch) {
544 case 0xFF:
545 case 0xFE:
546 case 0xFC:
547 case 0xF8:
548 case 0xF0:
549 case 0xE0:
550 case 0xC0:
551 case 0x80:
552 case 0x00:
553 /* discard char at probable break end */
554 goto try_again;
555 }
556 break;
557 }
558
559 process_errors:
560 /* handle framing error */
561 if (st & SC01STR_FEF) {
562 if (ch == 0) {
563 /* framing error with NUL char is probably a BREAK */
564 port->rx_brk = 1;
565 goto try_again;
566 }
567
568 _proto("Rx Framing Error");
569 icount->frame++;
570 status |= 1 << TTY_FRAME;
571 }
572
573 /* handle parity error */
574 if (st & SC01STR_PEF) {
575 _proto("Rx Parity Error");
576 icount->parity++;
577 status = TTY_PARITY;
578 }
579
580 /* handle normal char */
581 if (status == 0) {
582 if (uart_handle_sysrq_char(&port->uart, ch))
583 goto ignore_char;
584 status = (1 << TTY_NORMAL);
585 }
586
587 /* handle overrun error */
588 if (st & SC01STR_OEF) {
589 if (port->rx_brk)
590 goto try_again;
591
592 _proto("Rx Overrun Error");
593 icount->overrun++;
594 overrun = 1;
595 }
596
597 insert:
598 status &= port->uart.read_status_mask;
599
600 if (!overrun && !(status & port->uart.ignore_status_mask)) {
601 int flag;
602
603 if (status & (1 << TTY_BREAK))
604 flag = TTY_BREAK;
605 else if (status & (1 << TTY_PARITY))
606 flag = TTY_PARITY;
607 else if (status & (1 << TTY_FRAME))
608 flag = TTY_FRAME;
609 else
610 flag = TTY_NORMAL;
611
612 tty_insert_flip_char(tty, ch, flag);
613 }
614
615 /* overrun is special, since it's reported immediately, and doesn't
616 * affect the current character
617 */
618 if (overrun)
619 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
620
621 count--;
622 if (count <= 0) {
623 if (!tty->low_latency)
624 tty_flip_buffer_push(tty);
625 return;
626 }
627
628 ignore_char:
629 push = 1;
630 goto try_again;
631
632 not_break:
633 port->rx_brk = 0;
634 goto process_errors;
635 }
636
637 /*
638 * handle an interrupt from the serial transmission "virtual DMA" driver
639 * - note: the interrupt routine will disable its own interrupts when the Tx
640 * buffer is empty
641 */
642 static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
643 {
644 _enter("%s", port->name);
645
646 if (!port->uart.state || !port->uart.state->port.tty) {
647 mn10300_serial_dis_tx_intr(port);
648 return;
649 }
650
651 if (uart_tx_stopped(&port->uart) ||
652 uart_circ_empty(&port->uart.state->xmit))
653 mn10300_serial_dis_tx_intr(port);
654
655 if (uart_circ_chars_pending(&port->uart.state->xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(&port->uart);
657 }
658
659 /*
660 * deal with a change in the status of the CTS line
661 */
662 static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st)
663 {
664 u16 ctr;
665
666 port->tx_cts = st;
667 port->uart.icount.cts++;
668
669 /* flip the CTS state selector flag to interrupt when it changes
670 * back */
671 ctr = *port->_control;
672 ctr ^= SC2CTR_TWS;
673 *port->_control = ctr;
674
675 uart_handle_cts_change(&port->uart, st & SC2STR_CTS);
676 wake_up_interruptible(&port->uart.state->port.delta_msr_wait);
677 }
678
679 /*
680 * handle a virtual interrupt generated by the lower level "virtual DMA"
681 * routines (irq is the baud timer interrupt)
682 */
683 static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id)
684 {
685 struct mn10300_serial_port *port = dev_id;
686 u8 st;
687
688 spin_lock(&port->uart.lock);
689
690 if (port->intr_flags) {
691 _debug("INT %s: %x", port->name, port->intr_flags);
692
693 if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL))
694 mn10300_serial_receive_interrupt(port);
695
696 if (mask_test_and_clear(&port->intr_flags,
697 MNSCx_TX_SPACE | MNSCx_TX_EMPTY))
698 mn10300_serial_transmit_interrupt(port);
699 }
700
701 /* the only modem control line amongst the whole lot is CTS on
702 * serial port 2 */
703 if (port->type == PORT_MN10300_CTS) {
704 st = *port->_status;
705 if ((port->tx_cts ^ st) & SC2STR_CTS)
706 mn10300_serial_cts_changed(port, st);
707 }
708
709 spin_unlock(&port->uart.lock);
710
711 return IRQ_HANDLED;
712 }
713
714 /*
715 * return indication of whether the hardware transmit buffer is empty
716 */
717 static unsigned int mn10300_serial_tx_empty(struct uart_port *_port)
718 {
719 struct mn10300_serial_port *port =
720 container_of(_port, struct mn10300_serial_port, uart);
721
722 _enter("%s", port->name);
723
724 return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ?
725 0 : TIOCSER_TEMT;
726 }
727
728 /*
729 * set the modem control lines (we don't have any)
730 */
731 static void mn10300_serial_set_mctrl(struct uart_port *_port,
732 unsigned int mctrl)
733 {
734 struct mn10300_serial_port *port __attribute__ ((unused)) =
735 container_of(_port, struct mn10300_serial_port, uart);
736
737 _enter("%s,%x", port->name, mctrl);
738 }
739
740 /*
741 * get the modem control line statuses
742 */
743 static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port)
744 {
745 struct mn10300_serial_port *port =
746 container_of(_port, struct mn10300_serial_port, uart);
747
748 _enter("%s", port->name);
749
750 if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS))
751 return TIOCM_CAR | TIOCM_DSR;
752
753 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
754 }
755
756 /*
757 * stop transmitting characters
758 */
759 static void mn10300_serial_stop_tx(struct uart_port *_port)
760 {
761 struct mn10300_serial_port *port =
762 container_of(_port, struct mn10300_serial_port, uart);
763
764 _enter("%s", port->name);
765
766 /* disable the virtual DMA */
767 mn10300_serial_dis_tx_intr(port);
768 }
769
770 /*
771 * start transmitting characters
772 * - jump-start transmission if it has stalled
773 * - enable the serial Tx interrupt (used by the virtual DMA controller)
774 * - force an interrupt to happen if necessary
775 */
776 static void mn10300_serial_start_tx(struct uart_port *_port)
777 {
778 struct mn10300_serial_port *port =
779 container_of(_port, struct mn10300_serial_port, uart);
780
781 u16 x;
782
783 _enter("%s{%lu}",
784 port->name,
785 CIRC_CNT(&port->uart.state->xmit.head,
786 &port->uart.state->xmit.tail,
787 UART_XMIT_SIZE));
788
789 /* kick the virtual DMA controller */
790 arch_local_cli();
791 x = *port->tx_icr;
792 x |= GxICR_ENABLE;
793
794 if (*port->_status & SC01STR_TBF)
795 x &= ~(GxICR_REQUEST | GxICR_DETECT);
796 else
797 x |= GxICR_REQUEST | GxICR_DETECT;
798
799 _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx",
800 *port->_control, *port->_intr, *port->_status,
801 *port->_tmxmd,
802 (port->div_timer == MNSCx_DIV_TIMER_8BIT) ?
803 *(volatile u8 *)port->_tmxbr : *port->_tmxbr,
804 *port->tx_icr);
805
806 *port->tx_icr = x;
807 x = *port->tx_icr;
808 arch_local_sti();
809 }
810
811 /*
812 * transmit a high-priority XON/XOFF character
813 */
814 static void mn10300_serial_send_xchar(struct uart_port *_port, char ch)
815 {
816 struct mn10300_serial_port *port =
817 container_of(_port, struct mn10300_serial_port, uart);
818
819 _enter("%s,%02x", port->name, ch);
820
821 if (likely(port->gdbstub)) {
822 port->tx_xchar = ch;
823 if (ch)
824 mn10300_serial_en_tx_intr(port);
825 }
826 }
827
828 /*
829 * stop receiving characters
830 * - called whilst the port is being closed
831 */
832 static void mn10300_serial_stop_rx(struct uart_port *_port)
833 {
834 struct mn10300_serial_port *port =
835 container_of(_port, struct mn10300_serial_port, uart);
836
837 u16 ctr;
838
839 _enter("%s", port->name);
840
841 ctr = *port->_control;
842 ctr &= ~SC01CTR_RXE;
843 *port->_control = ctr;
844
845 mn10300_serial_dis_rx_intr(port);
846 }
847
848 /*
849 * enable modem status interrupts
850 */
851 static void mn10300_serial_enable_ms(struct uart_port *_port)
852 {
853 struct mn10300_serial_port *port =
854 container_of(_port, struct mn10300_serial_port, uart);
855
856 u16 ctr, cts;
857
858 _enter("%s", port->name);
859
860 if (port->type == PORT_MN10300_CTS) {
861 /* want to interrupt when CTS goes low if CTS is now high and
862 * vice versa
863 */
864 port->tx_cts = *port->_status;
865
866 cts = (port->tx_cts & SC2STR_CTS) ?
867 SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS;
868
869 ctr = *port->_control;
870 ctr &= ~SC2CTR_TWS;
871 ctr |= cts;
872 *port->_control = ctr;
873
874 mn10300_serial_en_tx_intr(port);
875 }
876 }
877
878 /*
879 * transmit or cease transmitting a break signal
880 */
881 static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl)
882 {
883 struct mn10300_serial_port *port =
884 container_of(_port, struct mn10300_serial_port, uart);
885
886 _enter("%s,%d", port->name, ctl);
887
888 if (ctl) {
889 /* tell the virtual DMA handler to assert BREAK */
890 port->tx_break = 1;
891 mn10300_serial_en_tx_intr(port);
892 } else {
893 port->tx_break = 0;
894 *port->_control &= ~SC01CTR_BKE;
895 mn10300_serial_en_tx_intr(port);
896 }
897 }
898
899 /*
900 * grab the interrupts and enable the port for reception
901 */
902 static int mn10300_serial_startup(struct uart_port *_port)
903 {
904 struct mn10300_serial_port *port =
905 container_of(_port, struct mn10300_serial_port, uart);
906 struct mn10300_serial_int *pint;
907
908 _enter("%s{%d}", port->name, port->gdbstub);
909
910 if (unlikely(port->gdbstub))
911 return -EBUSY;
912
913 /* allocate an Rx buffer for the virtual DMA handler */
914 port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL);
915 if (!port->rx_buffer)
916 return -ENOMEM;
917
918 port->rx_inp = port->rx_outp = 0;
919
920 /* finally, enable the device */
921 *port->_intr = SC01ICR_TI;
922 *port->_control |= SC01CTR_TXE | SC01CTR_RXE;
923
924 pint = &mn10300_serial_int_tbl[port->rx_irq];
925 pint->port = port;
926 pint->vdma = mn10300_serial_vdma_rx_handler;
927 pint = &mn10300_serial_int_tbl[port->tx_irq];
928 pint->port = port;
929 pint->vdma = mn10300_serial_vdma_tx_handler;
930
931 set_intr_level(port->rx_irq,
932 NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
933 set_intr_level(port->tx_irq,
934 NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
935 irq_set_chip(port->tm_irq, &mn10300_serial_pic);
936
937 if (request_irq(port->rx_irq, mn10300_serial_interrupt,
938 IRQF_DISABLED, port->rx_name, port) < 0)
939 goto error;
940
941 if (request_irq(port->tx_irq, mn10300_serial_interrupt,
942 IRQF_DISABLED, port->tx_name, port) < 0)
943 goto error2;
944
945 if (request_irq(port->tm_irq, mn10300_serial_interrupt,
946 IRQF_DISABLED, port->tm_name, port) < 0)
947 goto error3;
948 mn10300_serial_mask_ack(port->tm_irq);
949
950 return 0;
951
952 error3:
953 free_irq(port->tx_irq, port);
954 error2:
955 free_irq(port->rx_irq, port);
956 error:
957 kfree(port->rx_buffer);
958 port->rx_buffer = NULL;
959 return -EBUSY;
960 }
961
962 /*
963 * shutdown the port and release interrupts
964 */
965 static void mn10300_serial_shutdown(struct uart_port *_port)
966 {
967 u16 x;
968 struct mn10300_serial_port *port =
969 container_of(_port, struct mn10300_serial_port, uart);
970
971 _enter("%s", port->name);
972
973 /* disable the serial port and its baud rate timer */
974 port->tx_break = 0;
975 *port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
976 *port->_tmxmd = 0;
977
978 if (port->rx_buffer) {
979 void *buf = port->rx_buffer;
980 port->rx_buffer = NULL;
981 kfree(buf);
982 }
983
984 /* disable all intrs */
985 free_irq(port->tm_irq, port);
986 free_irq(port->rx_irq, port);
987 free_irq(port->tx_irq, port);
988
989 arch_local_cli();
990 *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
991 x = *port->rx_icr;
992 *port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
993 x = *port->tx_icr;
994 arch_local_sti();
995 }
996
997 /*
998 * this routine is called to set the UART divisor registers to match the
999 * specified baud rate for a serial port.
1000 */
1001 static void mn10300_serial_change_speed(struct mn10300_serial_port *port,
1002 struct ktermios *new,
1003 struct ktermios *old)
1004 {
1005 unsigned long flags;
1006 unsigned long ioclk = port->ioclk;
1007 unsigned cflag;
1008 int baud, bits, xdiv, tmp;
1009 u16 tmxbr, scxctr;
1010 u8 tmxmd, battempt;
1011 u8 div_timer = port->div_timer;
1012
1013 _enter("%s{%lu}", port->name, ioclk);
1014
1015 /* byte size and parity */
1016 cflag = new->c_cflag;
1017 switch (cflag & CSIZE) {
1018 case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break;
1019 case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
1020 default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
1021 }
1022
1023 if (cflag & CSTOPB) {
1024 scxctr |= SC01CTR_STB_2BIT;
1025 bits++;
1026 }
1027
1028 if (cflag & PARENB) {
1029 bits++;
1030 if (cflag & PARODD)
1031 scxctr |= SC01CTR_PB_ODD;
1032 #ifdef CMSPAR
1033 else if (cflag & CMSPAR)
1034 scxctr |= SC01CTR_PB_FIXED0;
1035 #endif
1036 else
1037 scxctr |= SC01CTR_PB_EVEN;
1038 }
1039
1040 /* Determine divisor based on baud rate */
1041 battempt = 0;
1042
1043 switch (port->uart.line) {
1044 #ifdef CONFIG_MN10300_TTYSM0
1045 case 0: /* ttySM0 */
1046 #if defined(CONFIG_MN10300_TTYSM0_TIMER8)
1047 scxctr |= SC0CTR_CK_TM8UFLOW_8;
1048 #elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
1049 scxctr |= SC0CTR_CK_TM0UFLOW_8;
1050 #elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
1051 scxctr |= SC0CTR_CK_TM2UFLOW_8;
1052 #else
1053 #error "Unknown config for ttySM0"
1054 #endif
1055 break;
1056 #endif /* CONFIG_MN10300_TTYSM0 */
1057
1058 #ifdef CONFIG_MN10300_TTYSM1
1059 case 1: /* ttySM1 */
1060 #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
1061 #if defined(CONFIG_MN10300_TTYSM1_TIMER9)
1062 scxctr |= SC1CTR_CK_TM9UFLOW_8;
1063 #elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
1064 scxctr |= SC1CTR_CK_TM3UFLOW_8;
1065 #else
1066 #error "Unknown config for ttySM1"
1067 #endif
1068 #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
1069 #if defined(CONFIG_MN10300_TTYSM1_TIMER12)
1070 scxctr |= SC1CTR_CK_TM12UFLOW_8;
1071 #else
1072 #error "Unknown config for ttySM1"
1073 #endif
1074 #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
1075 break;
1076 #endif /* CONFIG_MN10300_TTYSM1 */
1077
1078 #ifdef CONFIG_MN10300_TTYSM2
1079 case 2: /* ttySM2 */
1080 #if defined(CONFIG_AM33_2)
1081 #if defined(CONFIG_MN10300_TTYSM2_TIMER10)
1082 scxctr |= SC2CTR_CK_TM10UFLOW;
1083 #else
1084 #error "Unknown config for ttySM2"
1085 #endif
1086 #else /* CONFIG_AM33_2 */
1087 #if defined(CONFIG_MN10300_TTYSM2_TIMER9)
1088 scxctr |= SC2CTR_CK_TM9UFLOW_8;
1089 #elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
1090 scxctr |= SC2CTR_CK_TM1UFLOW_8;
1091 #elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
1092 scxctr |= SC2CTR_CK_TM3UFLOW_8;
1093 #else
1094 #error "Unknown config for ttySM2"
1095 #endif
1096 #endif /* CONFIG_AM33_2 */
1097 break;
1098 #endif /* CONFIG_MN10300_TTYSM2 */
1099
1100 default:
1101 break;
1102 }
1103
1104 try_alternative:
1105 baud = uart_get_baud_rate(&port->uart, new, old, 0,
1106 port->ioclk / 8);
1107
1108 _debug("ALT %d [baud %d]", battempt, baud);
1109
1110 if (!baud)
1111 baud = 9600; /* B0 transition handled in rs_set_termios */
1112 xdiv = 1;
1113 if (baud == 134) {
1114 baud = 269; /* 134 is really 134.5 */
1115 xdiv = 2;
1116 }
1117
1118 if (baud == 38400 &&
1119 (port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST
1120 ) {
1121 _debug("CUSTOM %u", port->uart.custom_divisor);
1122
1123 if (div_timer == MNSCx_DIV_TIMER_16BIT) {
1124 if (port->uart.custom_divisor <= 65535) {
1125 tmxmd = TM8MD_SRC_IOCLK;
1126 tmxbr = port->uart.custom_divisor;
1127 port->uart.uartclk = ioclk;
1128 goto timer_okay;
1129 }
1130 if (port->uart.custom_divisor / 8 <= 65535) {
1131 tmxmd = TM8MD_SRC_IOCLK_8;
1132 tmxbr = port->uart.custom_divisor / 8;
1133 port->uart.custom_divisor = tmxbr * 8;
1134 port->uart.uartclk = ioclk / 8;
1135 goto timer_okay;
1136 }
1137 if (port->uart.custom_divisor / 32 <= 65535) {
1138 tmxmd = TM8MD_SRC_IOCLK_32;
1139 tmxbr = port->uart.custom_divisor / 32;
1140 port->uart.custom_divisor = tmxbr * 32;
1141 port->uart.uartclk = ioclk / 32;
1142 goto timer_okay;
1143 }
1144
1145 } else if (div_timer == MNSCx_DIV_TIMER_8BIT) {
1146 if (port->uart.custom_divisor <= 255) {
1147 tmxmd = TM2MD_SRC_IOCLK;
1148 tmxbr = port->uart.custom_divisor;
1149 port->uart.uartclk = ioclk;
1150 goto timer_okay;
1151 }
1152 if (port->uart.custom_divisor / 8 <= 255) {
1153 tmxmd = TM2MD_SRC_IOCLK_8;
1154 tmxbr = port->uart.custom_divisor / 8;
1155 port->uart.custom_divisor = tmxbr * 8;
1156 port->uart.uartclk = ioclk / 8;
1157 goto timer_okay;
1158 }
1159 if (port->uart.custom_divisor / 32 <= 255) {
1160 tmxmd = TM2MD_SRC_IOCLK_32;
1161 tmxbr = port->uart.custom_divisor / 32;
1162 port->uart.custom_divisor = tmxbr * 32;
1163 port->uart.uartclk = ioclk / 32;
1164 goto timer_okay;
1165 }
1166 }
1167 }
1168
1169 switch (div_timer) {
1170 case MNSCx_DIV_TIMER_16BIT:
1171 port->uart.uartclk = ioclk;
1172 tmxmd = TM8MD_SRC_IOCLK;
1173 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
1174 if (tmp > 0 && tmp <= 65535)
1175 goto timer_okay;
1176
1177 port->uart.uartclk = ioclk / 8;
1178 tmxmd = TM8MD_SRC_IOCLK_8;
1179 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
1180 if (tmp > 0 && tmp <= 65535)
1181 goto timer_okay;
1182
1183 port->uart.uartclk = ioclk / 32;
1184 tmxmd = TM8MD_SRC_IOCLK_32;
1185 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
1186 if (tmp > 0 && tmp <= 65535)
1187 goto timer_okay;
1188 break;
1189
1190 case MNSCx_DIV_TIMER_8BIT:
1191 port->uart.uartclk = ioclk;
1192 tmxmd = TM2MD_SRC_IOCLK;
1193 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
1194 if (tmp > 0 && tmp <= 255)
1195 goto timer_okay;
1196
1197 port->uart.uartclk = ioclk / 8;
1198 tmxmd = TM2MD_SRC_IOCLK_8;
1199 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
1200 if (tmp > 0 && tmp <= 255)
1201 goto timer_okay;
1202
1203 port->uart.uartclk = ioclk / 32;
1204 tmxmd = TM2MD_SRC_IOCLK_32;
1205 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
1206 if (tmp > 0 && tmp <= 255)
1207 goto timer_okay;
1208 break;
1209
1210 default:
1211 BUG();
1212 return;
1213 }
1214
1215 /* refuse to change to a baud rate we can't support */
1216 _debug("CAN'T SUPPORT");
1217
1218 switch (battempt) {
1219 case 0:
1220 if (old) {
1221 new->c_cflag &= ~CBAUD;
1222 new->c_cflag |= (old->c_cflag & CBAUD);
1223 battempt = 1;
1224 goto try_alternative;
1225 }
1226
1227 case 1:
1228 /* as a last resort, if the quotient is zero, default to 9600
1229 * bps */
1230 new->c_cflag &= ~CBAUD;
1231 new->c_cflag |= B9600;
1232 battempt = 2;
1233 goto try_alternative;
1234
1235 default:
1236 /* hmmm... can't seem to support 9600 either
1237 * - we could try iterating through the speeds we know about to
1238 * find the lowest
1239 */
1240 new->c_cflag &= ~CBAUD;
1241 new->c_cflag |= B0;
1242
1243 if (div_timer == MNSCx_DIV_TIMER_16BIT)
1244 tmxmd = TM8MD_SRC_IOCLK_32;
1245 else if (div_timer == MNSCx_DIV_TIMER_8BIT)
1246 tmxmd = TM2MD_SRC_IOCLK_32;
1247 tmxbr = 1;
1248
1249 port->uart.uartclk = ioclk / 32;
1250 break;
1251 }
1252 timer_okay:
1253
1254 _debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr);
1255
1256 /* make the changes */
1257 spin_lock_irqsave(&port->uart.lock, flags);
1258
1259 uart_update_timeout(&port->uart, new->c_cflag, baud);
1260
1261 /* set the timer to produce the required baud rate */
1262 switch (div_timer) {
1263 case MNSCx_DIV_TIMER_16BIT:
1264 *port->_tmxmd = 0;
1265 *port->_tmxbr = tmxbr;
1266 *port->_tmxmd = TM8MD_INIT_COUNTER;
1267 *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
1268 break;
1269
1270 case MNSCx_DIV_TIMER_8BIT:
1271 *port->_tmxmd = 0;
1272 *(volatile u8 *) port->_tmxbr = (u8) tmxbr;
1273 *port->_tmxmd = TM2MD_INIT_COUNTER;
1274 *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
1275 break;
1276 }
1277
1278 /* CTS flow control flag and modem status interrupts */
1279 scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS);
1280
1281 if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) {
1282 /* want to interrupt when CTS goes low if CTS is now
1283 * high and vice versa
1284 */
1285 port->tx_cts = *port->_status;
1286
1287 if (port->tx_cts & SC2STR_CTS)
1288 scxctr |= SC2CTR_TWE;
1289 else
1290 scxctr |= SC2CTR_TWE | SC2CTR_TWS;
1291 }
1292
1293 /* set up parity check flag */
1294 port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN);
1295 if (new->c_iflag & INPCK)
1296 port->uart.read_status_mask |=
1297 (1 << TTY_PARITY) | (1 << TTY_FRAME);
1298 if (new->c_iflag & (BRKINT | PARMRK))
1299 port->uart.read_status_mask |= (1 << TTY_BREAK);
1300
1301 /* characters to ignore */
1302 port->uart.ignore_status_mask = 0;
1303 if (new->c_iflag & IGNPAR)
1304 port->uart.ignore_status_mask |=
1305 (1 << TTY_PARITY) | (1 << TTY_FRAME);
1306 if (new->c_iflag & IGNBRK) {
1307 port->uart.ignore_status_mask |= (1 << TTY_BREAK);
1308 /*
1309 * If we're ignoring parity and break indicators,
1310 * ignore overruns to (for real raw support).
1311 */
1312 if (new->c_iflag & IGNPAR)
1313 port->uart.ignore_status_mask |= (1 << TTY_OVERRUN);
1314 }
1315
1316 /* Ignore all characters if CREAD is not set */
1317 if ((new->c_cflag & CREAD) == 0)
1318 port->uart.ignore_status_mask |= (1 << TTY_NORMAL);
1319
1320 scxctr |= *port->_control & (SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
1321 *port->_control = scxctr;
1322
1323 spin_unlock_irqrestore(&port->uart.lock, flags);
1324 }
1325
1326 /*
1327 * set the terminal I/O parameters
1328 */
1329 static void mn10300_serial_set_termios(struct uart_port *_port,
1330 struct ktermios *new,
1331 struct ktermios *old)
1332 {
1333 struct mn10300_serial_port *port =
1334 container_of(_port, struct mn10300_serial_port, uart);
1335
1336 _enter("%s,%p,%p", port->name, new, old);
1337
1338 mn10300_serial_change_speed(port, new, old);
1339
1340 /* handle turning off CRTSCTS */
1341 if (!(new->c_cflag & CRTSCTS)) {
1342 u16 ctr = *port->_control;
1343 ctr &= ~SC2CTR_TWE;
1344 *port->_control = ctr;
1345 }
1346
1347 /* change Transfer bit-order (LSB/MSB) */
1348 if (new->c_cflag & CODMSB)
1349 *port->_control |= SC01CTR_OD_MSBFIRST; /* MSB MODE */
1350 else
1351 *port->_control &= ~SC01CTR_OD_MSBFIRST; /* LSB MODE */
1352 }
1353
1354 /*
1355 * return description of port type
1356 */
1357 static const char *mn10300_serial_type(struct uart_port *_port)
1358 {
1359 struct mn10300_serial_port *port =
1360 container_of(_port, struct mn10300_serial_port, uart);
1361
1362 if (port->uart.type == PORT_MN10300_CTS)
1363 return "MN10300 SIF_CTS";
1364
1365 return "MN10300 SIF";
1366 }
1367
1368 /*
1369 * release I/O and memory regions in use by port
1370 */
1371 static void mn10300_serial_release_port(struct uart_port *_port)
1372 {
1373 struct mn10300_serial_port *port =
1374 container_of(_port, struct mn10300_serial_port, uart);
1375
1376 _enter("%s", port->name);
1377
1378 release_mem_region((unsigned long) port->_iobase, 16);
1379 }
1380
1381 /*
1382 * request I/O and memory regions for port
1383 */
1384 static int mn10300_serial_request_port(struct uart_port *_port)
1385 {
1386 struct mn10300_serial_port *port =
1387 container_of(_port, struct mn10300_serial_port, uart);
1388
1389 _enter("%s", port->name);
1390
1391 request_mem_region((unsigned long) port->_iobase, 16, port->name);
1392 return 0;
1393 }
1394
1395 /*
1396 * configure the type and reserve the ports
1397 */
1398 static void mn10300_serial_config_port(struct uart_port *_port, int type)
1399 {
1400 struct mn10300_serial_port *port =
1401 container_of(_port, struct mn10300_serial_port, uart);
1402
1403 _enter("%s", port->name);
1404
1405 port->uart.type = PORT_MN10300;
1406
1407 if (port->options & MNSCx_OPT_CTS)
1408 port->uart.type = PORT_MN10300_CTS;
1409
1410 mn10300_serial_request_port(_port);
1411 }
1412
1413 /*
1414 * verify serial parameters are suitable for this port type
1415 */
1416 static int mn10300_serial_verify_port(struct uart_port *_port,
1417 struct serial_struct *ss)
1418 {
1419 struct mn10300_serial_port *port =
1420 container_of(_port, struct mn10300_serial_port, uart);
1421 void *mapbase = (void *) (unsigned long) port->uart.mapbase;
1422
1423 _enter("%s", port->name);
1424
1425 /* these things may not be changed */
1426 if (ss->irq != port->uart.irq ||
1427 ss->port != port->uart.iobase ||
1428 ss->io_type != port->uart.iotype ||
1429 ss->iomem_base != mapbase ||
1430 ss->iomem_reg_shift != port->uart.regshift ||
1431 ss->hub6 != port->uart.hub6 ||
1432 ss->xmit_fifo_size != port->uart.fifosize)
1433 return -EINVAL;
1434
1435 /* type may be changed on a port that supports CTS */
1436 if (ss->type != port->uart.type) {
1437 if (!(port->options & MNSCx_OPT_CTS))
1438 return -EINVAL;
1439
1440 if (ss->type != PORT_MN10300 &&
1441 ss->type != PORT_MN10300_CTS)
1442 return -EINVAL;
1443 }
1444
1445 return 0;
1446 }
1447
1448 /*
1449 * initialise the MN10300 on-chip UARTs
1450 */
1451 static int __init mn10300_serial_init(void)
1452 {
1453 struct mn10300_serial_port *port;
1454 int ret, i;
1455
1456 printk(KERN_INFO "%s version %s (%s)\n",
1457 serial_name, serial_version, serial_revdate);
1458
1459 #if defined(CONFIG_MN10300_TTYSM2) && defined(CONFIG_AM33_2)
1460 {
1461 int tmp;
1462 SC2TIM = 8; /* make the baud base of timer 2 IOCLK/8 */
1463 tmp = SC2TIM;
1464 }
1465 #endif
1466
1467 set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL),
1468 mn10300_serial_vdma_interrupt);
1469
1470 ret = uart_register_driver(&mn10300_serial_driver);
1471 if (!ret) {
1472 for (i = 0 ; i < NR_PORTS ; i++) {
1473 port = mn10300_serial_ports[i];
1474 if (!port || port->gdbstub)
1475 continue;
1476
1477 switch (port->clock_src) {
1478 case MNSCx_CLOCK_SRC_IOCLK:
1479 port->ioclk = MN10300_IOCLK;
1480 break;
1481
1482 #ifdef MN10300_IOBCLK
1483 case MNSCx_CLOCK_SRC_IOBCLK:
1484 port->ioclk = MN10300_IOBCLK;
1485 break;
1486 #endif
1487 default:
1488 BUG();
1489 }
1490
1491 ret = uart_add_one_port(&mn10300_serial_driver,
1492 &port->uart);
1493
1494 if (ret < 0) {
1495 _debug("ERROR %d", -ret);
1496 break;
1497 }
1498 }
1499
1500 if (ret)
1501 uart_unregister_driver(&mn10300_serial_driver);
1502 }
1503
1504 return ret;
1505 }
1506
1507 __initcall(mn10300_serial_init);
1508
1509
1510 #ifdef CONFIG_MN10300_TTYSM_CONSOLE
1511
1512 /*
1513 * print a string to the serial port without disturbing the real user of the
1514 * port too much
1515 * - the console must be locked by the caller
1516 */
1517 static void mn10300_serial_console_write(struct console *co,
1518 const char *s, unsigned count)
1519 {
1520 struct mn10300_serial_port *port;
1521 unsigned i;
1522 u16 scxctr, txicr, tmp;
1523 u8 tmxmd;
1524
1525 port = mn10300_serial_ports[co->index];
1526
1527 /* firstly hijack the serial port from the "virtual DMA" controller */
1528 arch_local_cli();
1529 txicr = *port->tx_icr;
1530 *port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
1531 tmp = *port->tx_icr;
1532 arch_local_sti();
1533
1534 /* the transmitter may be disabled */
1535 scxctr = *port->_control;
1536 if (!(scxctr & SC01CTR_TXE)) {
1537 /* restart the UART clock */
1538 tmxmd = *port->_tmxmd;
1539
1540 switch (port->div_timer) {
1541 case MNSCx_DIV_TIMER_16BIT:
1542 *port->_tmxmd = 0;
1543 *port->_tmxmd = TM8MD_INIT_COUNTER;
1544 *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
1545 break;
1546
1547 case MNSCx_DIV_TIMER_8BIT:
1548 *port->_tmxmd = 0;
1549 *port->_tmxmd = TM2MD_INIT_COUNTER;
1550 *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
1551 break;
1552 }
1553
1554 /* enable the transmitter */
1555 *port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE;
1556
1557 } else if (scxctr & SC01CTR_BKE) {
1558 /* stop transmitting BREAK */
1559 *port->_control = (scxctr & ~SC01CTR_BKE);
1560 }
1561
1562 /* send the chars into the serial port (with LF -> LFCR conversion) */
1563 for (i = 0; i < count; i++) {
1564 char ch = *s++;
1565
1566 while (*port->_status & SC01STR_TBF)
1567 continue;
1568 *(u8 *) port->_txb = ch;
1569
1570 if (ch == 0x0a) {
1571 while (*port->_status & SC01STR_TBF)
1572 continue;
1573 *(u8 *) port->_txb = 0xd;
1574 }
1575 }
1576
1577 /* can't let the transmitter be turned off if it's actually
1578 * transmitting */
1579 while (*port->_status & (SC01STR_TXF | SC01STR_TBF))
1580 continue;
1581
1582 /* disable the transmitter if we re-enabled it */
1583 if (!(scxctr & SC01CTR_TXE))
1584 *port->_control = scxctr;
1585
1586 arch_local_cli();
1587 *port->tx_icr = txicr;
1588 tmp = *port->tx_icr;
1589 arch_local_sti();
1590 }
1591
1592 /*
1593 * set up a serial port as a console
1594 * - construct a cflag setting for the first rs_open()
1595 * - initialize the serial port
1596 * - return non-zero if we didn't find a serial port.
1597 */
1598 static int __init mn10300_serial_console_setup(struct console *co,
1599 char *options)
1600 {
1601 struct mn10300_serial_port *port;
1602 int i, parity = 'n', baud = 9600, bits = 8, flow = 0;
1603
1604 for (i = 0 ; i < NR_PORTS ; i++) {
1605 port = mn10300_serial_ports[i];
1606 if (port && !port->gdbstub && port->uart.line == co->index)
1607 goto found_device;
1608 }
1609
1610 return -ENODEV;
1611
1612 found_device:
1613 switch (port->clock_src) {
1614 case MNSCx_CLOCK_SRC_IOCLK:
1615 port->ioclk = MN10300_IOCLK;
1616 break;
1617
1618 #ifdef MN10300_IOBCLK
1619 case MNSCx_CLOCK_SRC_IOBCLK:
1620 port->ioclk = MN10300_IOBCLK;
1621 break;
1622 #endif
1623 default:
1624 BUG();
1625 }
1626
1627 if (options)
1628 uart_parse_options(options, &baud, &parity, &bits, &flow);
1629
1630 return uart_set_options(&port->uart, co, baud, parity, bits, flow);
1631 }
1632
1633 /*
1634 * register console
1635 */
1636 static int __init mn10300_serial_console_init(void)
1637 {
1638 register_console(&mn10300_serial_console);
1639 return 0;
1640 }
1641
1642 console_initcall(mn10300_serial_console_init);
1643 #endif
1644
1645 #ifdef CONFIG_CONSOLE_POLL
1646 /*
1647 * Polled character reception for the kernel debugger
1648 */
1649 static int mn10300_serial_poll_get_char(struct uart_port *_port)
1650 {
1651 struct mn10300_serial_port *port =
1652 container_of(_port, struct mn10300_serial_port, uart);
1653 unsigned ix;
1654 u8 st, ch;
1655
1656 _enter("%s", port->name);
1657
1658 do {
1659 /* pull chars out of the hat */
1660 ix = port->rx_outp;
1661 if (ix == port->rx_inp)
1662 return NO_POLL_CHAR;
1663
1664 ch = port->rx_buffer[ix++];
1665 st = port->rx_buffer[ix++];
1666 smp_rmb();
1667 port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
1668
1669 } while (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF));
1670
1671 return ch;
1672 }
1673
1674
1675 /*
1676 * Polled character transmission for the kernel debugger
1677 */
1678 static void mn10300_serial_poll_put_char(struct uart_port *_port,
1679 unsigned char ch)
1680 {
1681 struct mn10300_serial_port *port =
1682 container_of(_port, struct mn10300_serial_port, uart);
1683 u8 intr, tmp;
1684
1685 /* wait for the transmitter to finish anything it might be doing (and
1686 * this includes the virtual DMA handler, so it might take a while) */
1687 while (*port->_status & (SC01STR_TBF | SC01STR_TXF))
1688 continue;
1689
1690 /* disable the Tx ready interrupt */
1691 intr = *port->_intr;
1692 *port->_intr = intr & ~SC01ICR_TI;
1693 tmp = *port->_intr;
1694
1695 if (ch == 0x0a) {
1696 *(u8 *) port->_txb = 0x0d;
1697 while (*port->_status & SC01STR_TBF)
1698 continue;
1699 }
1700
1701 *(u8 *) port->_txb = ch;
1702 while (*port->_status & SC01STR_TBF)
1703 continue;
1704
1705 /* restore the Tx interrupt flag */
1706 *port->_intr = intr;
1707 tmp = *port->_intr;
1708 }
1709
1710 #endif /* CONFIG_CONSOLE_POLL */
Linux with added FPC-III support