drivers/counter/stm32-lptimer-cnt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STM32 Low-Power Timer Encoder and Counter driver
   4  *
   5  * Copyright (C) STMicroelectronics 2017
   6  *
   7  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
   8  *
   9  * Inspired by 104-quad-8 and stm32-timer-trigger drivers.
  10  *
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/counter.h>
  15 #include <linux/iio/iio.h>
  16 #include <linux/mfd/stm32-lptimer.h>
  17 #include <linux/module.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20
  21 struct stm32_lptim_cnt {
  22         struct counter_device counter;
  23         struct device *dev;
  24         struct regmap *regmap;
  25         struct clk *clk;
  26         u32 ceiling;
  27         u32 polarity;
  28         u32 quadrature_mode;
  29         bool enabled;
  30 };
  31
  32 static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
  33 {
  34         u32 val;
  35         int ret;
  36
  37         ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
  38         if (ret)
  39                 return ret;
  40
  41         return FIELD_GET(STM32_LPTIM_ENABLE, val);
  42 }
  43
  44 static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
  45                                         int enable)
  46 {
  47         int ret;
  48         u32 val;
  49
  50         val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
  51         ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
  52         if (ret)
  53                 return ret;
  54
  55         if (!enable) {
  56                 clk_disable(priv->clk);
  57                 priv->enabled = false;
  58                 return 0;
  59         }
  60
  61         /* LP timer must be enabled before writing CMP & ARR */
  62         ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
  63         if (ret)
  64                 return ret;
  65
  66         ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
  67         if (ret)
  68                 return ret;
  69
  70         /* ensure CMP & ARR registers are properly written */
  71         ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
  72                                        (val & STM32_LPTIM_CMPOK_ARROK),
  73                                        100, 1000);
  74         if (ret)
  75                 return ret;
  76
  77         ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
  78                            STM32_LPTIM_CMPOKCF_ARROKCF);
  79         if (ret)
  80                 return ret;
  81
  82         ret = clk_enable(priv->clk);
  83         if (ret) {
  84                 regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
  85                 return ret;
  86         }
  87         priv->enabled = true;
  88
  89         /* Start LP timer in continuous mode */
  90         return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
  91                                   STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
  92 }
  93
  94 static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
  95 {
  96         u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
  97                    STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
  98         u32 val;
  99
 100         /* Setup LP timer encoder/counter and polarity, without prescaler */
 101         if (priv->quadrature_mode)
 102                 val = enable ? STM32_LPTIM_ENC : 0;
 103         else
 104                 val = enable ? STM32_LPTIM_COUNTMODE : 0;
 105         val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
 106
 107         return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
 108 }
 109
 110 static int stm32_lptim_write_raw(struct iio_dev *indio_dev,
 111                                  struct iio_chan_spec const *chan,
 112                                  int val, int val2, long mask)
 113 {
 114         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 115         int ret;
 116
 117         switch (mask) {
 118         case IIO_CHAN_INFO_ENABLE:
 119                 if (val < 0 || val > 1)
 120                         return -EINVAL;
 121
 122                 /* Check nobody uses the timer, or already disabled/enabled */
 123                 ret = stm32_lptim_is_enabled(priv);
 124                 if ((ret < 0) || (!ret && !val))
 125                         return ret;
 126                 if (val && ret)
 127                         return -EBUSY;
 128
 129                 ret = stm32_lptim_setup(priv, val);
 130                 if (ret)
 131                         return ret;
 132                 return stm32_lptim_set_enable_state(priv, val);
 133
 134         default:
 135                 return -EINVAL;
 136         }
 137 }
 138
 139 static int stm32_lptim_read_raw(struct iio_dev *indio_dev,
 140                                 struct iio_chan_spec const *chan,
 141                                 int *val, int *val2, long mask)
 142 {
 143         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 144         u32 dat;
 145         int ret;
 146
 147         switch (mask) {
 148         case IIO_CHAN_INFO_RAW:
 149                 ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat);
 150                 if (ret)
 151                         return ret;
 152                 *val = dat;
 153                 return IIO_VAL_INT;
 154
 155         case IIO_CHAN_INFO_ENABLE:
 156                 ret = stm32_lptim_is_enabled(priv);
 157                 if (ret < 0)
 158                         return ret;
 159                 *val = ret;
 160                 return IIO_VAL_INT;
 161
 162         case IIO_CHAN_INFO_SCALE:
 163                 /* Non-quadrature mode: scale = 1 */
 164                 *val = 1;
 165                 *val2 = 0;
 166                 if (priv->quadrature_mode) {
 167                         /*
 168                          * Quadrature encoder mode:
 169                          * - both edges, quarter cycle, scale is 0.25
 170                          * - either rising/falling edge scale is 0.5
 171                          */
 172                         if (priv->polarity > 1)
 173                                 *val2 = 2;
 174                         else
 175                                 *val2 = 1;
 176                 }
 177                 return IIO_VAL_FRACTIONAL_LOG2;
 178
 179         default:
 180                 return -EINVAL;
 181         }
 182 }
 183
 184 static const struct iio_info stm32_lptim_cnt_iio_info = {
 185         .read_raw = stm32_lptim_read_raw,
 186         .write_raw = stm32_lptim_write_raw,
 187 };
 188
 189 static const char *const stm32_lptim_quadrature_modes[] = {
 190         "non-quadrature",
 191         "quadrature",
 192 };
 193
 194 static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev,
 195                                            const struct iio_chan_spec *chan)
 196 {
 197         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 198
 199         return priv->quadrature_mode;
 200 }
 201
 202 static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev,
 203                                            const struct iio_chan_spec *chan,
 204                                            unsigned int type)
 205 {
 206         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 207
 208         if (stm32_lptim_is_enabled(priv))
 209                 return -EBUSY;
 210
 211         priv->quadrature_mode = type;
 212
 213         return 0;
 214 }
 215
 216 static const struct iio_enum stm32_lptim_quadrature_mode_en = {
 217         .items = stm32_lptim_quadrature_modes,
 218         .num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes),
 219         .get = stm32_lptim_get_quadrature_mode,
 220         .set = stm32_lptim_set_quadrature_mode,
 221 };
 222
 223 static const char * const stm32_lptim_cnt_polarity[] = {
 224         "rising-edge", "falling-edge", "both-edges",
 225 };
 226
 227 static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev,
 228                                         const struct iio_chan_spec *chan)
 229 {
 230         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 231
 232         return priv->polarity;
 233 }
 234
 235 static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev,
 236                                         const struct iio_chan_spec *chan,
 237                                         unsigned int type)
 238 {
 239         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 240
 241         if (stm32_lptim_is_enabled(priv))
 242                 return -EBUSY;
 243
 244         priv->polarity = type;
 245
 246         return 0;
 247 }
 248
 249 static const struct iio_enum stm32_lptim_cnt_polarity_en = {
 250         .items = stm32_lptim_cnt_polarity,
 251         .num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity),
 252         .get = stm32_lptim_cnt_get_polarity,
 253         .set = stm32_lptim_cnt_set_polarity,
 254 };
 255
 256 static ssize_t stm32_lptim_cnt_get_ceiling(struct stm32_lptim_cnt *priv,
 257                                            char *buf)
 258 {
 259         return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
 260 }
 261
 262 static ssize_t stm32_lptim_cnt_set_ceiling(struct stm32_lptim_cnt *priv,
 263                                            const char *buf, size_t len)
 264 {
 265         int ret;
 266
 267         if (stm32_lptim_is_enabled(priv))
 268                 return -EBUSY;
 269
 270         ret = kstrtouint(buf, 0, &priv->ceiling);
 271         if (ret)
 272                 return ret;
 273
 274         if (priv->ceiling > STM32_LPTIM_MAX_ARR)
 275                 return -EINVAL;
 276
 277         return len;
 278 }
 279
 280 static ssize_t stm32_lptim_cnt_get_preset_iio(struct iio_dev *indio_dev,
 281                                               uintptr_t private,
 282                                               const struct iio_chan_spec *chan,
 283                                               char *buf)
 284 {
 285         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 286
 287         return stm32_lptim_cnt_get_ceiling(priv, buf);
 288 }
 289
 290 static ssize_t stm32_lptim_cnt_set_preset_iio(struct iio_dev *indio_dev,
 291                                               uintptr_t private,
 292                                               const struct iio_chan_spec *chan,
 293                                               const char *buf, size_t len)
 294 {
 295         struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
 296
 297         return stm32_lptim_cnt_set_ceiling(priv, buf, len);
 298 }
 299
 300 /* LP timer with encoder */
 301 static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {
 302         {
 303                 .name = "preset",
 304                 .shared = IIO_SEPARATE,
 305                 .read = stm32_lptim_cnt_get_preset_iio,
 306                 .write = stm32_lptim_cnt_set_preset_iio,
 307         },
 308         IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
 309         IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
 310         IIO_ENUM("quadrature_mode", IIO_SEPARATE,
 311                  &stm32_lptim_quadrature_mode_en),
 312         IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_lptim_quadrature_mode_en),
 313         {}
 314 };
 315
 316 static const struct iio_chan_spec stm32_lptim_enc_channels = {
 317         .type = IIO_COUNT,
 318         .channel = 0,
 319         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 320                               BIT(IIO_CHAN_INFO_ENABLE) |
 321                               BIT(IIO_CHAN_INFO_SCALE),
 322         .ext_info = stm32_lptim_enc_ext_info,
 323         .indexed = 1,
 324 };
 325
 326 /* LP timer without encoder (counter only) */
 327 static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {
 328         {
 329                 .name = "preset",
 330                 .shared = IIO_SEPARATE,
 331                 .read = stm32_lptim_cnt_get_preset_iio,
 332                 .write = stm32_lptim_cnt_set_preset_iio,
 333         },
 334         IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
 335         IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
 336         {}
 337 };
 338
 339 static const struct iio_chan_spec stm32_lptim_cnt_channels = {
 340         .type = IIO_COUNT,
 341         .channel = 0,
 342         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 343                               BIT(IIO_CHAN_INFO_ENABLE) |
 344                               BIT(IIO_CHAN_INFO_SCALE),
 345         .ext_info = stm32_lptim_cnt_ext_info,
 346         .indexed = 1,
 347 };
 348
 349 /**
 350  * stm32_lptim_cnt_function - enumerates stm32 LPTimer counter & encoder modes
 351  * @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
 352  * @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
 353  */
 354 enum stm32_lptim_cnt_function {
 355         STM32_LPTIM_COUNTER_INCREASE,
 356         STM32_LPTIM_ENCODER_BOTH_EDGE,
 357 };
 358
 359 static enum counter_count_function stm32_lptim_cnt_functions[] = {
 360         [STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
 361         [STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
 362 };
 363
 364 enum stm32_lptim_synapse_action {
 365         STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
 366         STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
 367         STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
 368         STM32_LPTIM_SYNAPSE_ACTION_NONE,
 369 };
 370
 371 static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
 372         /* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
 373         [STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
 374         [STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
 375         [STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
 376         [STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
 377 };
 378
 379 static int stm32_lptim_cnt_read(struct counter_device *counter,
 380                                 struct counter_count *count,
 381                                 struct counter_count_read_value *val)
 382 {
 383         struct stm32_lptim_cnt *const priv = counter->priv;
 384         u32 cnt;
 385         int ret;
 386
 387         ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
 388         if (ret)
 389                 return ret;
 390
 391         counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt);
 392
 393         return 0;
 394 }
 395
 396 static int stm32_lptim_cnt_function_get(struct counter_device *counter,
 397                                         struct counter_count *count,
 398                                         size_t *function)
 399 {
 400         struct stm32_lptim_cnt *const priv = counter->priv;
 401
 402         if (!priv->quadrature_mode) {
 403                 *function = STM32_LPTIM_COUNTER_INCREASE;
 404                 return 0;
 405         }
 406
 407         if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
 408                 *function = STM32_LPTIM_ENCODER_BOTH_EDGE;
 409                 return 0;
 410         }
 411
 412         return -EINVAL;
 413 }
 414
 415 static int stm32_lptim_cnt_function_set(struct counter_device *counter,
 416                                         struct counter_count *count,
 417                                         size_t function)
 418 {
 419         struct stm32_lptim_cnt *const priv = counter->priv;
 420
 421         if (stm32_lptim_is_enabled(priv))
 422                 return -EBUSY;
 423
 424         switch (function) {
 425         case STM32_LPTIM_COUNTER_INCREASE:
 426                 priv->quadrature_mode = 0;
 427                 return 0;
 428         case STM32_LPTIM_ENCODER_BOTH_EDGE:
 429                 priv->quadrature_mode = 1;
 430                 priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
 431                 return 0;
 432         }
 433
 434         return -EINVAL;
 435 }
 436
 437 static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
 438                                            struct counter_count *count,
 439                                            void *private, char *buf)
 440 {
 441         struct stm32_lptim_cnt *const priv = counter->priv;
 442         int ret;
 443
 444         ret = stm32_lptim_is_enabled(priv);
 445         if (ret < 0)
 446                 return ret;
 447
 448         return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
 449 }
 450
 451 static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
 452                                             struct counter_count *count,
 453                                             void *private,
 454                                             const char *buf, size_t len)
 455 {
 456         struct stm32_lptim_cnt *const priv = counter->priv;
 457         bool enable;
 458         int ret;
 459
 460         ret = kstrtobool(buf, &enable);
 461         if (ret)
 462                 return ret;
 463
 464         /* Check nobody uses the timer, or already disabled/enabled */
 465         ret = stm32_lptim_is_enabled(priv);
 466         if ((ret < 0) || (!ret && !enable))
 467                 return ret;
 468         if (enable && ret)
 469                 return -EBUSY;
 470
 471         ret = stm32_lptim_setup(priv, enable);
 472         if (ret)
 473                 return ret;
 474
 475         ret = stm32_lptim_set_enable_state(priv, enable);
 476         if (ret)
 477                 return ret;
 478
 479         return len;
 480 }
 481
 482 static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
 483                                             struct counter_count *count,
 484                                             void *private, char *buf)
 485 {
 486         struct stm32_lptim_cnt *const priv = counter->priv;
 487
 488         return stm32_lptim_cnt_get_ceiling(priv, buf);
 489 }
 490
 491 static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
 492                                              struct counter_count *count,
 493                                              void *private,
 494                                              const char *buf, size_t len)
 495 {
 496         struct stm32_lptim_cnt *const priv = counter->priv;
 497
 498         return stm32_lptim_cnt_set_ceiling(priv, buf, len);
 499 }
 500
 501 static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
 502         {
 503                 .name = "enable",
 504                 .read = stm32_lptim_cnt_enable_read,
 505                 .write = stm32_lptim_cnt_enable_write
 506         },
 507         {
 508                 .name = "ceiling",
 509                 .read = stm32_lptim_cnt_ceiling_read,
 510                 .write = stm32_lptim_cnt_ceiling_write
 511         },
 512 };
 513
 514 static int stm32_lptim_cnt_action_get(struct counter_device *counter,
 515                                       struct counter_count *count,
 516                                       struct counter_synapse *synapse,
 517                                       size_t *action)
 518 {
 519         struct stm32_lptim_cnt *const priv = counter->priv;
 520         size_t function;
 521         int err;
 522
 523         err = stm32_lptim_cnt_function_get(counter, count, &function);
 524         if (err)
 525                 return err;
 526
 527         switch (function) {
 528         case STM32_LPTIM_COUNTER_INCREASE:
 529                 /* LP Timer acts as up-counter on input 1 */
 530                 if (synapse->signal->id == count->synapses[0].signal->id)
 531                         *action = priv->polarity;
 532                 else
 533                         *action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
 534                 return 0;
 535         case STM32_LPTIM_ENCODER_BOTH_EDGE:
 536                 *action = priv->polarity;
 537                 return 0;
 538         }
 539
 540         return -EINVAL;
 541 }
 542
 543 static int stm32_lptim_cnt_action_set(struct counter_device *counter,
 544                                       struct counter_count *count,
 545                                       struct counter_synapse *synapse,
 546                                       size_t action)
 547 {
 548         struct stm32_lptim_cnt *const priv = counter->priv;
 549         size_t function;
 550         int err;
 551
 552         if (stm32_lptim_is_enabled(priv))
 553                 return -EBUSY;
 554
 555         err = stm32_lptim_cnt_function_get(counter, count, &function);
 556         if (err)
 557                 return err;
 558
 559         /* only set polarity when in counter mode (on input 1) */
 560         if (function == STM32_LPTIM_COUNTER_INCREASE
 561             && synapse->signal->id == count->synapses[0].signal->id) {
 562                 switch (action) {
 563                 case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
 564                 case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
 565                 case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
 566                         priv->polarity = action;
 567                         return 0;
 568                 }
 569         }
 570
 571         return -EINVAL;
 572 }
 573
 574 static const struct counter_ops stm32_lptim_cnt_ops = {
 575         .count_read = stm32_lptim_cnt_read,
 576         .function_get = stm32_lptim_cnt_function_get,
 577         .function_set = stm32_lptim_cnt_function_set,
 578         .action_get = stm32_lptim_cnt_action_get,
 579         .action_set = stm32_lptim_cnt_action_set,
 580 };
 581
 582 static struct counter_signal stm32_lptim_cnt_signals[] = {
 583         {
 584                 .id = 0,
 585                 .name = "Channel 1 Quadrature A"
 586         },
 587         {
 588                 .id = 1,
 589                 .name = "Channel 1 Quadrature B"
 590         }
 591 };
 592
 593 static struct counter_synapse stm32_lptim_cnt_synapses[] = {
 594         {
 595                 .actions_list = stm32_lptim_cnt_synapse_actions,
 596                 .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
 597                 .signal = &stm32_lptim_cnt_signals[0]
 598         },
 599         {
 600                 .actions_list = stm32_lptim_cnt_synapse_actions,
 601                 .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
 602                 .signal = &stm32_lptim_cnt_signals[1]
 603         }
 604 };
 605
 606 /* LP timer with encoder */
 607 static struct counter_count stm32_lptim_enc_counts = {
 608         .id = 0,
 609         .name = "LPTimer Count",
 610         .functions_list = stm32_lptim_cnt_functions,
 611         .num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
 612         .synapses = stm32_lptim_cnt_synapses,
 613         .num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
 614         .ext = stm32_lptim_cnt_ext,
 615         .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
 616 };
 617
 618 /* LP timer without encoder (counter only) */
 619 static struct counter_count stm32_lptim_in1_counts = {
 620         .id = 0,
 621         .name = "LPTimer Count",
 622         .functions_list = stm32_lptim_cnt_functions,
 623         .num_functions = 1,
 624         .synapses = stm32_lptim_cnt_synapses,
 625         .num_synapses = 1,
 626         .ext = stm32_lptim_cnt_ext,
 627         .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
 628 };
 629
 630 static int stm32_lptim_cnt_probe(struct platform_device *pdev)
 631 {
 632         struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
 633         struct stm32_lptim_cnt *priv;
 634         struct iio_dev *indio_dev;
 635         int ret;
 636
 637         if (IS_ERR_OR_NULL(ddata))
 638                 return -EINVAL;
 639
 640         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
 641         if (!indio_dev)
 642                 return -ENOMEM;
 643
 644         priv = iio_priv(indio_dev);
 645         priv->dev = &pdev->dev;
 646         priv->regmap = ddata->regmap;
 647         priv->clk = ddata->clk;
 648         priv->ceiling = STM32_LPTIM_MAX_ARR;
 649
 650         /* Initialize IIO device */
 651         indio_dev->name = dev_name(&pdev->dev);
 652         indio_dev->dev.parent = &pdev->dev;
 653         indio_dev->dev.of_node = pdev->dev.of_node;
 654         indio_dev->info = &stm32_lptim_cnt_iio_info;
 655         if (ddata->has_encoder)
 656                 indio_dev->channels = &stm32_lptim_enc_channels;
 657         else
 658                 indio_dev->channels = &stm32_lptim_cnt_channels;
 659         indio_dev->num_channels = 1;
 660
 661         /* Initialize Counter device */
 662         priv->counter.name = dev_name(&pdev->dev);
 663         priv->counter.parent = &pdev->dev;
 664         priv->counter.ops = &stm32_lptim_cnt_ops;
 665         if (ddata->has_encoder) {
 666                 priv->counter.counts = &stm32_lptim_enc_counts;
 667                 priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
 668         } else {
 669                 priv->counter.counts = &stm32_lptim_in1_counts;
 670                 priv->counter.num_signals = 1;
 671         }
 672         priv->counter.num_counts = 1;
 673         priv->counter.signals = stm32_lptim_cnt_signals;
 674         priv->counter.priv = priv;
 675
 676         platform_set_drvdata(pdev, priv);
 677
 678         ret = devm_iio_device_register(&pdev->dev, indio_dev);
 679         if (ret)
 680                 return ret;
 681
 682         return devm_counter_register(&pdev->dev, &priv->counter);
 683 }
 684
 685 #ifdef CONFIG_PM_SLEEP
 686 static int stm32_lptim_cnt_suspend(struct device *dev)
 687 {
 688         struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
 689         int ret;
 690
 691         /* Only take care of enabled counter: don't disturb other MFD child */
 692         if (priv->enabled) {
 693                 ret = stm32_lptim_setup(priv, 0);
 694                 if (ret)
 695                         return ret;
 696
 697                 ret = stm32_lptim_set_enable_state(priv, 0);
 698                 if (ret)
 699                         return ret;
 700
 701                 /* Force enable state for later resume */
 702                 priv->enabled = true;
 703         }
 704
 705         return pinctrl_pm_select_sleep_state(dev);
 706 }
 707
 708 static int stm32_lptim_cnt_resume(struct device *dev)
 709 {
 710         struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
 711         int ret;
 712
 713         ret = pinctrl_pm_select_default_state(dev);
 714         if (ret)
 715                 return ret;
 716
 717         if (priv->enabled) {
 718                 priv->enabled = false;
 719                 ret = stm32_lptim_setup(priv, 1);
 720                 if (ret)
 721                         return ret;
 722
 723                 ret = stm32_lptim_set_enable_state(priv, 1);
 724                 if (ret)
 725                         return ret;
 726         }
 727
 728         return 0;
 729 }
 730 #endif
 731
 732 static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
 733                          stm32_lptim_cnt_resume);
 734
 735 static const struct of_device_id stm32_lptim_cnt_of_match[] = {
 736         { .compatible = "st,stm32-lptimer-counter", },
 737         {},
 738 };
 739 MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
 740
 741 static struct platform_driver stm32_lptim_cnt_driver = {
 742         .probe = stm32_lptim_cnt_probe,
 743         .driver = {
 744                 .name = "stm32-lptimer-counter",
 745                 .of_match_table = stm32_lptim_cnt_of_match,
 746                 .pm = &stm32_lptim_cnt_pm_ops,
 747         },
 748 };
 749 module_platform_driver(stm32_lptim_cnt_driver);
 750
 751 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
 752 MODULE_ALIAS("platform:stm32-lptimer-counter");
 753 MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
 754 MODULE_LICENSE("GPL v2");