drivers/ata/ahci_brcmstb.c

   1 /*
   2  * Broadcom SATA3 AHCI Controller Driver
   3  *
   4  * Copyright © 2009-2015 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2, or (at your option)
   9  * any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/ahci_platform.h>
  18 #include <linux/compiler.h>
  19 #include <linux/device.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/libata.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/string.h>
  29
  30 #include "ahci.h"
  31
  32 #define DRV_NAME                                        "brcm-ahci"
  33
  34 #define SATA_TOP_CTRL_VERSION                           0x0
  35 #define SATA_TOP_CTRL_BUS_CTRL                          0x4
  36  #define MMIO_ENDIAN_SHIFT                              0 /* CPU->AHCI */
  37  #define DMADESC_ENDIAN_SHIFT                           2 /* AHCI->DDR */
  38  #define DMADATA_ENDIAN_SHIFT                           4 /* AHCI->DDR */
  39  #define PIODATA_ENDIAN_SHIFT                           6
  40   #define ENDIAN_SWAP_NONE                              0
  41   #define ENDIAN_SWAP_FULL                              2
  42  #define OVERRIDE_HWINIT                                BIT(16)
  43 #define SATA_TOP_CTRL_TP_CTRL                           0x8
  44 #define SATA_TOP_CTRL_PHY_CTRL                          0xc
  45  #define SATA_TOP_CTRL_PHY_CTRL_1                       0x0
  46   #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE       BIT(14)
  47  #define SATA_TOP_CTRL_PHY_CTRL_2                       0x4
  48   #define SATA_TOP_CTRL_2_SW_RST_MDIOREG                BIT(0)
  49   #define SATA_TOP_CTRL_2_SW_RST_OOB                    BIT(1)
  50   #define SATA_TOP_CTRL_2_SW_RST_RX                     BIT(2)
  51   #define SATA_TOP_CTRL_2_SW_RST_TX                     BIT(3)
  52   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET              BIT(14)
  53  #define SATA_TOP_CTRL_PHY_OFFS                         0x8
  54  #define SATA_TOP_MAX_PHYS                              2
  55 #define SATA_TOP_CTRL_SATA_TP_OUT                       0x1c
  56 #define SATA_TOP_CTRL_CLIENT_INIT_CTRL                  0x20
  57
  58 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
  59 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
  60 #define DATA_ENDIAN                      2 /* AHCI->DDR inbound accesses */
  61 #define MMIO_ENDIAN                      2 /* CPU->AHCI outbound accesses */
  62 #else
  63 #define DATA_ENDIAN                      0
  64 #define MMIO_ENDIAN                      0
  65 #endif
  66
  67 #define BUS_CTRL_ENDIAN_CONF                            \
  68         ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |        \
  69         (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |         \
  70         (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
  71
  72 struct brcm_ahci_priv {
  73         struct device *dev;
  74         void __iomem *top_ctrl;
  75         u32 port_mask;
  76 };
  77
  78 static const struct ata_port_info ahci_brcm_port_info = {
  79         .flags          = AHCI_FLAG_COMMON,
  80         .pio_mask       = ATA_PIO4,
  81         .udma_mask      = ATA_UDMA6,
  82         .port_ops       = &ahci_platform_ops,
  83 };
  84
  85 static inline u32 brcm_sata_readreg(void __iomem *addr)
  86 {
  87         /*
  88          * MIPS endianness is configured by boot strap, which also reverses all
  89          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
  90          * endian I/O).
  91          *
  92          * Other architectures (e.g., ARM) either do not support big endian, or
  93          * else leave I/O in little endian mode.
  94          */
  95         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  96                 return __raw_readl(addr);
  97         else
  98                 return readl_relaxed(addr);
  99 }
 100
 101 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
 102 {
 103         /* See brcm_sata_readreg() comments */
 104         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 105                 __raw_writel(val, addr);
 106         else
 107                 writel_relaxed(val, addr);
 108 }
 109
 110 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 111 {
 112         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
 113                                 (port * SATA_TOP_CTRL_PHY_OFFS);
 114         void __iomem *p;
 115         u32 reg;
 116
 117         /* clear PHY_DEFAULT_POWER_STATE */
 118         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
 119         reg = brcm_sata_readreg(p);
 120         reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
 121         brcm_sata_writereg(reg, p);
 122
 123         /* reset the PHY digital logic */
 124         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
 125         reg = brcm_sata_readreg(p);
 126         reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
 127                  SATA_TOP_CTRL_2_SW_RST_RX);
 128         reg |= SATA_TOP_CTRL_2_SW_RST_TX;
 129         brcm_sata_writereg(reg, p);
 130         reg = brcm_sata_readreg(p);
 131         reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
 132         brcm_sata_writereg(reg, p);
 133         reg = brcm_sata_readreg(p);
 134         reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
 135         brcm_sata_writereg(reg, p);
 136         (void)brcm_sata_readreg(p);
 137 }
 138
 139 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
 140 {
 141         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
 142                                 (port * SATA_TOP_CTRL_PHY_OFFS);
 143         void __iomem *p;
 144         u32 reg;
 145
 146         /* power-off the PHY digital logic */
 147         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
 148         reg = brcm_sata_readreg(p);
 149         reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
 150                 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
 151                 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
 152         brcm_sata_writereg(reg, p);
 153
 154         /* set PHY_DEFAULT_POWER_STATE */
 155         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
 156         reg = brcm_sata_readreg(p);
 157         reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
 158         brcm_sata_writereg(reg, p);
 159 }
 160
 161 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
 162 {
 163         int i;
 164
 165         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
 166                 if (priv->port_mask & BIT(i))
 167                         brcm_sata_phy_enable(priv, i);
 168 }
 169
 170 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
 171 {
 172         int i;
 173
 174         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
 175                 if (priv->port_mask & BIT(i))
 176                         brcm_sata_phy_disable(priv, i);
 177 }
 178
 179 static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
 180                                   struct brcm_ahci_priv *priv)
 181 {
 182         void __iomem *ahci;
 183         struct resource *res;
 184         u32 impl;
 185
 186         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
 187         ahci = devm_ioremap_resource(&pdev->dev, res);
 188         if (IS_ERR(ahci))
 189                 return 0;
 190
 191         impl = readl(ahci + HOST_PORTS_IMPL);
 192
 193         if (fls(impl) > SATA_TOP_MAX_PHYS)
 194                 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
 195                          impl);
 196         else if (!impl)
 197                 dev_info(priv->dev, "no ports found\n");
 198
 199         devm_iounmap(&pdev->dev, ahci);
 200         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
 201
 202         return impl;
 203 }
 204
 205 static void brcm_sata_init(struct brcm_ahci_priv *priv)
 206 {
 207         /* Configure endianness */
 208         brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
 209                            priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
 210 }
 211
 212 #ifdef CONFIG_PM_SLEEP
 213 static int brcm_ahci_suspend(struct device *dev)
 214 {
 215         struct ata_host *host = dev_get_drvdata(dev);
 216         struct ahci_host_priv *hpriv = host->private_data;
 217         struct brcm_ahci_priv *priv = hpriv->plat_data;
 218         int ret;
 219
 220         ret = ahci_platform_suspend(dev);
 221         brcm_sata_phys_disable(priv);
 222         return ret;
 223 }
 224
 225 static int brcm_ahci_resume(struct device *dev)
 226 {
 227         struct ata_host *host = dev_get_drvdata(dev);
 228         struct ahci_host_priv *hpriv = host->private_data;
 229         struct brcm_ahci_priv *priv = hpriv->plat_data;
 230
 231         brcm_sata_init(priv);
 232         brcm_sata_phys_enable(priv);
 233         return ahci_platform_resume(dev);
 234 }
 235 #endif
 236
 237 static struct scsi_host_template ahci_platform_sht = {
 238         AHCI_SHT(DRV_NAME),
 239 };
 240
 241 static int brcm_ahci_probe(struct platform_device *pdev)
 242 {
 243         struct device *dev = &pdev->dev;
 244         struct brcm_ahci_priv *priv;
 245         struct ahci_host_priv *hpriv;
 246         struct resource *res;
 247         int ret;
 248
 249         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 250         if (!priv)
 251                 return -ENOMEM;
 252         priv->dev = dev;
 253
 254         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
 255         priv->top_ctrl = devm_ioremap_resource(dev, res);
 256         if (IS_ERR(priv->top_ctrl))
 257                 return PTR_ERR(priv->top_ctrl);
 258
 259         brcm_sata_init(priv);
 260
 261         priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
 262         if (!priv->port_mask)
 263                 return -ENODEV;
 264
 265         brcm_sata_phys_enable(priv);
 266
 267         hpriv = ahci_platform_get_resources(pdev);
 268         if (IS_ERR(hpriv))
 269                 return PTR_ERR(hpriv);
 270         hpriv->plat_data = priv;
 271
 272         ret = ahci_platform_enable_resources(hpriv);
 273         if (ret)
 274                 return ret;
 275
 276         ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
 277                                       &ahci_platform_sht);
 278         if (ret)
 279                 return ret;
 280
 281         dev_info(dev, "Broadcom AHCI SATA3 registered\n");
 282
 283         return 0;
 284 }
 285
 286 static int brcm_ahci_remove(struct platform_device *pdev)
 287 {
 288         struct ata_host *host = dev_get_drvdata(&pdev->dev);
 289         struct ahci_host_priv *hpriv = host->private_data;
 290         struct brcm_ahci_priv *priv = hpriv->plat_data;
 291         int ret;
 292
 293         ret = ata_platform_remove_one(pdev);
 294         if (ret)
 295                 return ret;
 296
 297         brcm_sata_phys_disable(priv);
 298
 299         return 0;
 300 }
 301
 302 static const struct of_device_id ahci_of_match[] = {
 303         {.compatible = "brcm,bcm7445-ahci"},
 304         {},
 305 };
 306 MODULE_DEVICE_TABLE(of, ahci_of_match);
 307
 308 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
 309
 310 static struct platform_driver brcm_ahci_driver = {
 311         .probe = brcm_ahci_probe,
 312         .remove = brcm_ahci_remove,
 313         .driver = {
 314                 .name = DRV_NAME,
 315                 .of_match_table = ahci_of_match,
 316                 .pm = &ahci_brcm_pm_ops,
 317         },
 318 };
 319 module_platform_driver(brcm_ahci_driver);
 320
 321 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
 322 MODULE_AUTHOR("Brian Norris");
 323 MODULE_LICENSE("GPL");
 324 MODULE_ALIAS("platform:sata-brcmstb");