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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / crypto / atmel-sha.c
blob7abe908427dfc3e669bde0e37190360437610a15
1 /*
2 * Cryptographic API.
3 *
4 * Support for ATMEL SHA1/SHA256 HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-sham.c drivers.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <linux/cryptohash.h>
37 #include <crypto/scatterwalk.h>
38 #include <crypto/algapi.h>
39 #include <crypto/sha.h>
40 #include <crypto/hash.h>
41 #include <crypto/internal/hash.h>
42 #include <linux/platform_data/crypto-atmel.h>
43 #include "atmel-sha-regs.h"
44
45 /* SHA flags */
46 #define SHA_FLAGS_BUSY BIT(0)
47 #define SHA_FLAGS_FINAL BIT(1)
48 #define SHA_FLAGS_DMA_ACTIVE BIT(2)
49 #define SHA_FLAGS_OUTPUT_READY BIT(3)
50 #define SHA_FLAGS_INIT BIT(4)
51 #define SHA_FLAGS_CPU BIT(5)
52 #define SHA_FLAGS_DMA_READY BIT(6)
53
54 #define SHA_FLAGS_FINUP BIT(16)
55 #define SHA_FLAGS_SG BIT(17)
56 #define SHA_FLAGS_SHA1 BIT(18)
57 #define SHA_FLAGS_SHA224 BIT(19)
58 #define SHA_FLAGS_SHA256 BIT(20)
59 #define SHA_FLAGS_SHA384 BIT(21)
60 #define SHA_FLAGS_SHA512 BIT(22)
61 #define SHA_FLAGS_ERROR BIT(23)
62 #define SHA_FLAGS_PAD BIT(24)
63
64 #define SHA_OP_UPDATE 1
65 #define SHA_OP_FINAL 2
66
67 #define SHA_BUFFER_LEN PAGE_SIZE
68
69 #define ATMEL_SHA_DMA_THRESHOLD 56
70
71 struct atmel_sha_caps {
72 bool has_dma;
73 bool has_dualbuff;
74 bool has_sha224;
75 bool has_sha_384_512;
76 };
77
78 struct atmel_sha_dev;
79
80 struct atmel_sha_reqctx {
81 struct atmel_sha_dev *dd;
82 unsigned long flags;
83 unsigned long op;
84
85 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
86 u64 digcnt[2];
87 size_t bufcnt;
88 size_t buflen;
89 dma_addr_t dma_addr;
90
91 /* walk state */
92 struct scatterlist *sg;
93 unsigned int offset; /* offset in current sg */
94 unsigned int total; /* total request */
95
96 size_t block_size;
97
98 u8 buffer[0] __aligned(sizeof(u32));
99 };
100
101 struct atmel_sha_ctx {
102 struct atmel_sha_dev *dd;
103
104 unsigned long flags;
105 };
106
107 #define ATMEL_SHA_QUEUE_LENGTH 50
108
109 struct atmel_sha_dma {
110 struct dma_chan *chan;
111 struct dma_slave_config dma_conf;
112 };
113
114 struct atmel_sha_dev {
115 struct list_head list;
116 unsigned long phys_base;
117 struct device *dev;
118 struct clk *iclk;
119 int irq;
120 void __iomem *io_base;
121
122 spinlock_t lock;
123 int err;
124 struct tasklet_struct done_task;
125
126 unsigned long flags;
127 struct crypto_queue queue;
128 struct ahash_request *req;
129
130 struct atmel_sha_dma dma_lch_in;
131
132 struct atmel_sha_caps caps;
133
134 u32 hw_version;
135 };
136
137 struct atmel_sha_drv {
138 struct list_head dev_list;
139 spinlock_t lock;
140 };
141
142 static struct atmel_sha_drv atmel_sha = {
143 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list),
144 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock),
145 };
146
147 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset)
148 {
149 return readl_relaxed(dd->io_base + offset);
150 }
151
152 static inline void atmel_sha_write(struct atmel_sha_dev *dd,
153 u32 offset, u32 value)
154 {
155 writel_relaxed(value, dd->io_base + offset);
156 }
157
158 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
159 {
160 size_t count;
161
162 while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
163 count = min(ctx->sg->length - ctx->offset, ctx->total);
164 count = min(count, ctx->buflen - ctx->bufcnt);
165
166 if (count <= 0) {
167 /*
168 * Check if count <= 0 because the buffer is full or
169 * because the sg length is 0. In the latest case,
170 * check if there is another sg in the list, a 0 length
171 * sg doesn't necessarily mean the end of the sg list.
172 */
173 if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) {
174 ctx->sg = sg_next(ctx->sg);
175 continue;
176 } else {
177 break;
178 }
179 }
180
181 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
182 ctx->offset, count, 0);
183
184 ctx->bufcnt += count;
185 ctx->offset += count;
186 ctx->total -= count;
187
188 if (ctx->offset == ctx->sg->length) {
189 ctx->sg = sg_next(ctx->sg);
190 if (ctx->sg)
191 ctx->offset = 0;
192 else
193 ctx->total = 0;
194 }
195 }
196
197 return 0;
198 }
199
200 /*
201 * The purpose of this padding is to ensure that the padded message is a
202 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
203 * The bit "1" is appended at the end of the message followed by
204 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
205 * 128 bits block (SHA384/SHA512) equals to the message length in bits
206 * is appended.
207 *
208 * For SHA1/SHA224/SHA256, padlen is calculated as followed:
209 * - if message length < 56 bytes then padlen = 56 - message length
210 * - else padlen = 64 + 56 - message length
211 *
212 * For SHA384/SHA512, padlen is calculated as followed:
213 * - if message length < 112 bytes then padlen = 112 - message length
214 * - else padlen = 128 + 112 - message length
215 */
216 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
217 {
218 unsigned int index, padlen;
219 u64 bits[2];
220 u64 size[2];
221
222 size[0] = ctx->digcnt[0];
223 size[1] = ctx->digcnt[1];
224
225 size[0] += ctx->bufcnt;
226 if (size[0] < ctx->bufcnt)
227 size[1]++;
228
229 size[0] += length;
230 if (size[0] < length)
231 size[1]++;
232
233 bits[1] = cpu_to_be64(size[0] << 3);
234 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
235
236 if (ctx->flags & (SHA_FLAGS_SHA384 | SHA_FLAGS_SHA512)) {
237 index = ctx->bufcnt & 0x7f;
238 padlen = (index < 112) ? (112 - index) : ((128+112) - index);
239 *(ctx->buffer + ctx->bufcnt) = 0x80;
240 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
241 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
242 ctx->bufcnt += padlen + 16;
243 ctx->flags |= SHA_FLAGS_PAD;
244 } else {
245 index = ctx->bufcnt & 0x3f;
246 padlen = (index < 56) ? (56 - index) : ((64+56) - index);
247 *(ctx->buffer + ctx->bufcnt) = 0x80;
248 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
249 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
250 ctx->bufcnt += padlen + 8;
251 ctx->flags |= SHA_FLAGS_PAD;
252 }
253 }
254
255 static int atmel_sha_init(struct ahash_request *req)
256 {
257 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
258 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
259 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
260 struct atmel_sha_dev *dd = NULL;
261 struct atmel_sha_dev *tmp;
262
263 spin_lock_bh(&atmel_sha.lock);
264 if (!tctx->dd) {
265 list_for_each_entry(tmp, &atmel_sha.dev_list, list) {
266 dd = tmp;
267 break;
268 }
269 tctx->dd = dd;
270 } else {
271 dd = tctx->dd;
272 }
273
274 spin_unlock_bh(&atmel_sha.lock);
275
276 ctx->dd = dd;
277
278 ctx->flags = 0;
279
280 dev_dbg(dd->dev, "init: digest size: %d\n",
281 crypto_ahash_digestsize(tfm));
282
283 switch (crypto_ahash_digestsize(tfm)) {
284 case SHA1_DIGEST_SIZE:
285 ctx->flags |= SHA_FLAGS_SHA1;
286 ctx->block_size = SHA1_BLOCK_SIZE;
287 break;
288 case SHA224_DIGEST_SIZE:
289 ctx->flags |= SHA_FLAGS_SHA224;
290 ctx->block_size = SHA224_BLOCK_SIZE;
291 break;
292 case SHA256_DIGEST_SIZE:
293 ctx->flags |= SHA_FLAGS_SHA256;
294 ctx->block_size = SHA256_BLOCK_SIZE;
295 break;
296 case SHA384_DIGEST_SIZE:
297 ctx->flags |= SHA_FLAGS_SHA384;
298 ctx->block_size = SHA384_BLOCK_SIZE;
299 break;
300 case SHA512_DIGEST_SIZE:
301 ctx->flags |= SHA_FLAGS_SHA512;
302 ctx->block_size = SHA512_BLOCK_SIZE;
303 break;
304 default:
305 return -EINVAL;
306 break;
307 }
308
309 ctx->bufcnt = 0;
310 ctx->digcnt[0] = 0;
311 ctx->digcnt[1] = 0;
312 ctx->buflen = SHA_BUFFER_LEN;
313
314 return 0;
315 }
316
317 static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
318 {
319 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
320 u32 valcr = 0, valmr = SHA_MR_MODE_AUTO;
321
322 if (likely(dma)) {
323 if (!dd->caps.has_dma)
324 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
325 valmr = SHA_MR_MODE_PDC;
326 if (dd->caps.has_dualbuff)
327 valmr |= SHA_MR_DUALBUFF;
328 } else {
329 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
330 }
331
332 if (ctx->flags & SHA_FLAGS_SHA1)
333 valmr |= SHA_MR_ALGO_SHA1;
334 else if (ctx->flags & SHA_FLAGS_SHA224)
335 valmr |= SHA_MR_ALGO_SHA224;
336 else if (ctx->flags & SHA_FLAGS_SHA256)
337 valmr |= SHA_MR_ALGO_SHA256;
338 else if (ctx->flags & SHA_FLAGS_SHA384)
339 valmr |= SHA_MR_ALGO_SHA384;
340 else if (ctx->flags & SHA_FLAGS_SHA512)
341 valmr |= SHA_MR_ALGO_SHA512;
342
343 /* Setting CR_FIRST only for the first iteration */
344 if (!(ctx->digcnt[0] || ctx->digcnt[1]))
345 valcr = SHA_CR_FIRST;
346
347 atmel_sha_write(dd, SHA_CR, valcr);
348 atmel_sha_write(dd, SHA_MR, valmr);
349 }
350
351 static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
352 size_t length, int final)
353 {
354 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
355 int count, len32;
356 const u32 *buffer = (const u32 *)buf;
357
358 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
359 ctx->digcnt[1], ctx->digcnt[0], length, final);
360
361 atmel_sha_write_ctrl(dd, 0);
362
363 /* should be non-zero before next lines to disable clocks later */
364 ctx->digcnt[0] += length;
365 if (ctx->digcnt[0] < length)
366 ctx->digcnt[1]++;
367
368 if (final)
369 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
370
371 len32 = DIV_ROUND_UP(length, sizeof(u32));
372
373 dd->flags |= SHA_FLAGS_CPU;
374
375 for (count = 0; count < len32; count++)
376 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]);
377
378 return -EINPROGRESS;
379 }
380
381 static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
382 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
383 {
384 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
385 int len32;
386
387 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
388 ctx->digcnt[1], ctx->digcnt[0], length1, final);
389
390 len32 = DIV_ROUND_UP(length1, sizeof(u32));
391 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
392 atmel_sha_write(dd, SHA_TPR, dma_addr1);
393 atmel_sha_write(dd, SHA_TCR, len32);
394
395 len32 = DIV_ROUND_UP(length2, sizeof(u32));
396 atmel_sha_write(dd, SHA_TNPR, dma_addr2);
397 atmel_sha_write(dd, SHA_TNCR, len32);
398
399 atmel_sha_write_ctrl(dd, 1);
400
401 /* should be non-zero before next lines to disable clocks later */
402 ctx->digcnt[0] += length1;
403 if (ctx->digcnt[0] < length1)
404 ctx->digcnt[1]++;
405
406 if (final)
407 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
408
409 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
410
411 /* Start DMA transfer */
412 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN);
413
414 return -EINPROGRESS;
415 }
416
417 static void atmel_sha_dma_callback(void *data)
418 {
419 struct atmel_sha_dev *dd = data;
420
421 /* dma_lch_in - completed - wait DATRDY */
422 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
423 }
424
425 static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
426 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
427 {
428 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
429 struct dma_async_tx_descriptor *in_desc;
430 struct scatterlist sg[2];
431
432 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
433 ctx->digcnt[1], ctx->digcnt[0], length1, final);
434
435 dd->dma_lch_in.dma_conf.src_maxburst = 16;
436 dd->dma_lch_in.dma_conf.dst_maxburst = 16;
437
438 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
439
440 if (length2) {
441 sg_init_table(sg, 2);
442 sg_dma_address(&sg[0]) = dma_addr1;
443 sg_dma_len(&sg[0]) = length1;
444 sg_dma_address(&sg[1]) = dma_addr2;
445 sg_dma_len(&sg[1]) = length2;
446 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
447 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
448 } else {
449 sg_init_table(sg, 1);
450 sg_dma_address(&sg[0]) = dma_addr1;
451 sg_dma_len(&sg[0]) = length1;
452 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
453 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
454 }
455 if (!in_desc)
456 return -EINVAL;
457
458 in_desc->callback = atmel_sha_dma_callback;
459 in_desc->callback_param = dd;
460
461 atmel_sha_write_ctrl(dd, 1);
462
463 /* should be non-zero before next lines to disable clocks later */
464 ctx->digcnt[0] += length1;
465 if (ctx->digcnt[0] < length1)
466 ctx->digcnt[1]++;
467
468 if (final)
469 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
470
471 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
472
473 /* Start DMA transfer */
474 dmaengine_submit(in_desc);
475 dma_async_issue_pending(dd->dma_lch_in.chan);
476
477 return -EINPROGRESS;
478 }
479
480 static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
481 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
482 {
483 if (dd->caps.has_dma)
484 return atmel_sha_xmit_dma(dd, dma_addr1, length1,
485 dma_addr2, length2, final);
486 else
487 return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
488 dma_addr2, length2, final);
489 }
490
491 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
492 {
493 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
494 int bufcnt;
495
496 atmel_sha_append_sg(ctx);
497 atmel_sha_fill_padding(ctx, 0);
498 bufcnt = ctx->bufcnt;
499 ctx->bufcnt = 0;
500
501 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
502 }
503
504 static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
505 struct atmel_sha_reqctx *ctx,
506 size_t length, int final)
507 {
508 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
509 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
510 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
511 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen +
512 ctx->block_size);
513 return -EINVAL;
514 }
515
516 ctx->flags &= ~SHA_FLAGS_SG;
517
518 /* next call does not fail... so no unmap in the case of error */
519 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
520 }
521
522 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
523 {
524 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
525 unsigned int final;
526 size_t count;
527
528 atmel_sha_append_sg(ctx);
529
530 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
531
532 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n",
533 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
534
535 if (final)
536 atmel_sha_fill_padding(ctx, 0);
537
538 if (final || (ctx->bufcnt == ctx->buflen)) {
539 count = ctx->bufcnt;
540 ctx->bufcnt = 0;
541 return atmel_sha_xmit_dma_map(dd, ctx, count, final);
542 }
543
544 return 0;
545 }
546
547 static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
548 {
549 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
550 unsigned int length, final, tail;
551 struct scatterlist *sg;
552 unsigned int count;
553
554 if (!ctx->total)
555 return 0;
556
557 if (ctx->bufcnt || ctx->offset)
558 return atmel_sha_update_dma_slow(dd);
559
560 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n",
561 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
562
563 sg = ctx->sg;
564
565 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
566 return atmel_sha_update_dma_slow(dd);
567
568 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
569 /* size is not ctx->block_size aligned */
570 return atmel_sha_update_dma_slow(dd);
571
572 length = min(ctx->total, sg->length);
573
574 if (sg_is_last(sg)) {
575 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
576 /* not last sg must be ctx->block_size aligned */
577 tail = length & (ctx->block_size - 1);
578 length -= tail;
579 }
580 }
581
582 ctx->total -= length;
583 ctx->offset = length; /* offset where to start slow */
584
585 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
586
587 /* Add padding */
588 if (final) {
589 tail = length & (ctx->block_size - 1);
590 length -= tail;
591 ctx->total += tail;
592 ctx->offset = length; /* offset where to start slow */
593
594 sg = ctx->sg;
595 atmel_sha_append_sg(ctx);
596
597 atmel_sha_fill_padding(ctx, length);
598
599 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
600 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
601 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
602 dev_err(dd->dev, "dma %u bytes error\n",
603 ctx->buflen + ctx->block_size);
604 return -EINVAL;
605 }
606
607 if (length == 0) {
608 ctx->flags &= ~SHA_FLAGS_SG;
609 count = ctx->bufcnt;
610 ctx->bufcnt = 0;
611 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
612 0, final);
613 } else {
614 ctx->sg = sg;
615 if (!dma_map_sg(dd->dev, ctx->sg, 1,
616 DMA_TO_DEVICE)) {
617 dev_err(dd->dev, "dma_map_sg error\n");
618 return -EINVAL;
619 }
620
621 ctx->flags |= SHA_FLAGS_SG;
622
623 count = ctx->bufcnt;
624 ctx->bufcnt = 0;
625 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
626 length, ctx->dma_addr, count, final);
627 }
628 }
629
630 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
631 dev_err(dd->dev, "dma_map_sg error\n");
632 return -EINVAL;
633 }
634
635 ctx->flags |= SHA_FLAGS_SG;
636
637 /* next call does not fail... so no unmap in the case of error */
638 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
639 0, final);
640 }
641
642 static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
643 {
644 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
645
646 if (ctx->flags & SHA_FLAGS_SG) {
647 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
648 if (ctx->sg->length == ctx->offset) {
649 ctx->sg = sg_next(ctx->sg);
650 if (ctx->sg)
651 ctx->offset = 0;
652 }
653 if (ctx->flags & SHA_FLAGS_PAD) {
654 dma_unmap_single(dd->dev, ctx->dma_addr,
655 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
656 }
657 } else {
658 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
659 ctx->block_size, DMA_TO_DEVICE);
660 }
661
662 return 0;
663 }
664
665 static int atmel_sha_update_req(struct atmel_sha_dev *dd)
666 {
667 struct ahash_request *req = dd->req;
668 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
669 int err;
670
671 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
672 ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
673
674 if (ctx->flags & SHA_FLAGS_CPU)
675 err = atmel_sha_update_cpu(dd);
676 else
677 err = atmel_sha_update_dma_start(dd);
678
679 /* wait for dma completion before can take more data */
680 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
681 err, ctx->digcnt[1], ctx->digcnt[0]);
682
683 return err;
684 }
685
686 static int atmel_sha_final_req(struct atmel_sha_dev *dd)
687 {
688 struct ahash_request *req = dd->req;
689 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
690 int err = 0;
691 int count;
692
693 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) {
694 atmel_sha_fill_padding(ctx, 0);
695 count = ctx->bufcnt;
696 ctx->bufcnt = 0;
697 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1);
698 }
699 /* faster to handle last block with cpu */
700 else {
701 atmel_sha_fill_padding(ctx, 0);
702 count = ctx->bufcnt;
703 ctx->bufcnt = 0;
704 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1);
705 }
706
707 dev_dbg(dd->dev, "final_req: err: %d\n", err);
708
709 return err;
710 }
711
712 static void atmel_sha_copy_hash(struct ahash_request *req)
713 {
714 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
715 u32 *hash = (u32 *)ctx->digest;
716 int i;
717
718 if (ctx->flags & SHA_FLAGS_SHA1)
719 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
720 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
721 else if (ctx->flags & SHA_FLAGS_SHA224)
722 for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++)
723 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
724 else if (ctx->flags & SHA_FLAGS_SHA256)
725 for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++)
726 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
727 else if (ctx->flags & SHA_FLAGS_SHA384)
728 for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++)
729 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
730 else
731 for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++)
732 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
733 }
734
735 static void atmel_sha_copy_ready_hash(struct ahash_request *req)
736 {
737 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
738
739 if (!req->result)
740 return;
741
742 if (ctx->flags & SHA_FLAGS_SHA1)
743 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
744 else if (ctx->flags & SHA_FLAGS_SHA224)
745 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
746 else if (ctx->flags & SHA_FLAGS_SHA256)
747 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
748 else if (ctx->flags & SHA_FLAGS_SHA384)
749 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
750 else
751 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
752 }
753
754 static int atmel_sha_finish(struct ahash_request *req)
755 {
756 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
757 struct atmel_sha_dev *dd = ctx->dd;
758 int err = 0;
759
760 if (ctx->digcnt[0] || ctx->digcnt[1])
761 atmel_sha_copy_ready_hash(req);
762
763 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1],
764 ctx->digcnt[0], ctx->bufcnt);
765
766 return err;
767 }
768
769 static void atmel_sha_finish_req(struct ahash_request *req, int err)
770 {
771 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
772 struct atmel_sha_dev *dd = ctx->dd;
773
774 if (!err) {
775 atmel_sha_copy_hash(req);
776 if (SHA_FLAGS_FINAL & dd->flags)
777 err = atmel_sha_finish(req);
778 } else {
779 ctx->flags |= SHA_FLAGS_ERROR;
780 }
781
782 /* atomic operation is not needed here */
783 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
784 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY);
785
786 clk_disable(dd->iclk);
787
788 if (req->base.complete)
789 req->base.complete(&req->base, err);
790
791 /* handle new request */
792 tasklet_schedule(&dd->done_task);
793 }
794
795 static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
796 {
797 int err;
798
799 err = clk_enable(dd->iclk);
800 if (err)
801 return err;
802
803 if (!(SHA_FLAGS_INIT & dd->flags)) {
804 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
805 dd->flags |= SHA_FLAGS_INIT;
806 dd->err = 0;
807 }
808
809 return 0;
810 }
811
812 static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
813 {
814 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
815 }
816
817 static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
818 {
819 atmel_sha_hw_init(dd);
820
821 dd->hw_version = atmel_sha_get_version(dd);
822
823 dev_info(dd->dev,
824 "version: 0x%x\n", dd->hw_version);
825
826 clk_disable(dd->iclk);
827 }
828
829 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
830 struct ahash_request *req)
831 {
832 struct crypto_async_request *async_req, *backlog;
833 struct atmel_sha_reqctx *ctx;
834 unsigned long flags;
835 int err = 0, ret = 0;
836
837 spin_lock_irqsave(&dd->lock, flags);
838 if (req)
839 ret = ahash_enqueue_request(&dd->queue, req);
840
841 if (SHA_FLAGS_BUSY & dd->flags) {
842 spin_unlock_irqrestore(&dd->lock, flags);
843 return ret;
844 }
845
846 backlog = crypto_get_backlog(&dd->queue);
847 async_req = crypto_dequeue_request(&dd->queue);
848 if (async_req)
849 dd->flags |= SHA_FLAGS_BUSY;
850
851 spin_unlock_irqrestore(&dd->lock, flags);
852
853 if (!async_req)
854 return ret;
855
856 if (backlog)
857 backlog->complete(backlog, -EINPROGRESS);
858
859 req = ahash_request_cast(async_req);
860 dd->req = req;
861 ctx = ahash_request_ctx(req);
862
863 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
864 ctx->op, req->nbytes);
865
866 err = atmel_sha_hw_init(dd);
867
868 if (err)
869 goto err1;
870
871 if (ctx->op == SHA_OP_UPDATE) {
872 err = atmel_sha_update_req(dd);
873 if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP))
874 /* no final() after finup() */
875 err = atmel_sha_final_req(dd);
876 } else if (ctx->op == SHA_OP_FINAL) {
877 err = atmel_sha_final_req(dd);
878 }
879
880 err1:
881 if (err != -EINPROGRESS)
882 /* done_task will not finish it, so do it here */
883 atmel_sha_finish_req(req, err);
884
885 dev_dbg(dd->dev, "exit, err: %d\n", err);
886
887 return ret;
888 }
889
890 static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
891 {
892 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
893 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
894 struct atmel_sha_dev *dd = tctx->dd;
895
896 ctx->op = op;
897
898 return atmel_sha_handle_queue(dd, req);
899 }
900
901 static int atmel_sha_update(struct ahash_request *req)
902 {
903 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
904
905 if (!req->nbytes)
906 return 0;
907
908 ctx->total = req->nbytes;
909 ctx->sg = req->src;
910 ctx->offset = 0;
911
912 if (ctx->flags & SHA_FLAGS_FINUP) {
913 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD)
914 /* faster to use CPU for short transfers */
915 ctx->flags |= SHA_FLAGS_CPU;
916 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
917 atmel_sha_append_sg(ctx);
918 return 0;
919 }
920 return atmel_sha_enqueue(req, SHA_OP_UPDATE);
921 }
922
923 static int atmel_sha_final(struct ahash_request *req)
924 {
925 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
926 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
927 struct atmel_sha_dev *dd = tctx->dd;
928
929 int err = 0;
930
931 ctx->flags |= SHA_FLAGS_FINUP;
932
933 if (ctx->flags & SHA_FLAGS_ERROR)
934 return 0; /* uncompleted hash is not needed */
935
936 if (ctx->bufcnt) {
937 return atmel_sha_enqueue(req, SHA_OP_FINAL);
938 } else if (!(ctx->flags & SHA_FLAGS_PAD)) { /* add padding */
939 err = atmel_sha_hw_init(dd);
940 if (err)
941 goto err1;
942
943 dd->flags |= SHA_FLAGS_BUSY;
944 err = atmel_sha_final_req(dd);
945 } else {
946 /* copy ready hash (+ finalize hmac) */
947 return atmel_sha_finish(req);
948 }
949
950 err1:
951 if (err != -EINPROGRESS)
952 /* done_task will not finish it, so do it here */
953 atmel_sha_finish_req(req, err);
954
955 return err;
956 }
957
958 static int atmel_sha_finup(struct ahash_request *req)
959 {
960 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
961 int err1, err2;
962
963 ctx->flags |= SHA_FLAGS_FINUP;
964
965 err1 = atmel_sha_update(req);
966 if (err1 == -EINPROGRESS ||
967 (err1 == -EBUSY && (ahash_request_flags(req) &
968 CRYPTO_TFM_REQ_MAY_BACKLOG)))
969 return err1;
970
971 /*
972 * final() has to be always called to cleanup resources
973 * even if udpate() failed, except EINPROGRESS
974 */
975 err2 = atmel_sha_final(req);
976
977 return err1 ?: err2;
978 }
979
980 static int atmel_sha_digest(struct ahash_request *req)
981 {
982 return atmel_sha_init(req) ?: atmel_sha_finup(req);
983 }
984
985 static int atmel_sha_cra_init(struct crypto_tfm *tfm)
986 {
987 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
988 sizeof(struct atmel_sha_reqctx) +
989 SHA_BUFFER_LEN + SHA512_BLOCK_SIZE);
990
991 return 0;
992 }
993
994 static struct ahash_alg sha_1_256_algs[] = {
995 {
996 .init = atmel_sha_init,
997 .update = atmel_sha_update,
998 .final = atmel_sha_final,
999 .finup = atmel_sha_finup,
1000 .digest = atmel_sha_digest,
1001 .halg = {
1002 .digestsize = SHA1_DIGEST_SIZE,
1003 .base = {
1004 .cra_name = "sha1",
1005 .cra_driver_name = "atmel-sha1",
1006 .cra_priority = 100,
1007 .cra_flags = CRYPTO_ALG_ASYNC,
1008 .cra_blocksize = SHA1_BLOCK_SIZE,
1009 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1010 .cra_alignmask = 0,
1011 .cra_module = THIS_MODULE,
1012 .cra_init = atmel_sha_cra_init,
1013 }
1014 }
1015 },
1016 {
1017 .init = atmel_sha_init,
1018 .update = atmel_sha_update,
1019 .final = atmel_sha_final,
1020 .finup = atmel_sha_finup,
1021 .digest = atmel_sha_digest,
1022 .halg = {
1023 .digestsize = SHA256_DIGEST_SIZE,
1024 .base = {
1025 .cra_name = "sha256",
1026 .cra_driver_name = "atmel-sha256",
1027 .cra_priority = 100,
1028 .cra_flags = CRYPTO_ALG_ASYNC,
1029 .cra_blocksize = SHA256_BLOCK_SIZE,
1030 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1031 .cra_alignmask = 0,
1032 .cra_module = THIS_MODULE,
1033 .cra_init = atmel_sha_cra_init,
1034 }
1035 }
1036 },
1037 };
1038
1039 static struct ahash_alg sha_224_alg = {
1040 .init = atmel_sha_init,
1041 .update = atmel_sha_update,
1042 .final = atmel_sha_final,
1043 .finup = atmel_sha_finup,
1044 .digest = atmel_sha_digest,
1045 .halg = {
1046 .digestsize = SHA224_DIGEST_SIZE,
1047 .base = {
1048 .cra_name = "sha224",
1049 .cra_driver_name = "atmel-sha224",
1050 .cra_priority = 100,
1051 .cra_flags = CRYPTO_ALG_ASYNC,
1052 .cra_blocksize = SHA224_BLOCK_SIZE,
1053 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1054 .cra_alignmask = 0,
1055 .cra_module = THIS_MODULE,
1056 .cra_init = atmel_sha_cra_init,
1057 }
1058 }
1059 };
1060
1061 static struct ahash_alg sha_384_512_algs[] = {
1062 {
1063 .init = atmel_sha_init,
1064 .update = atmel_sha_update,
1065 .final = atmel_sha_final,
1066 .finup = atmel_sha_finup,
1067 .digest = atmel_sha_digest,
1068 .halg = {
1069 .digestsize = SHA384_DIGEST_SIZE,
1070 .base = {
1071 .cra_name = "sha384",
1072 .cra_driver_name = "atmel-sha384",
1073 .cra_priority = 100,
1074 .cra_flags = CRYPTO_ALG_ASYNC,
1075 .cra_blocksize = SHA384_BLOCK_SIZE,
1076 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1077 .cra_alignmask = 0x3,
1078 .cra_module = THIS_MODULE,
1079 .cra_init = atmel_sha_cra_init,
1080 }
1081 }
1082 },
1083 {
1084 .init = atmel_sha_init,
1085 .update = atmel_sha_update,
1086 .final = atmel_sha_final,
1087 .finup = atmel_sha_finup,
1088 .digest = atmel_sha_digest,
1089 .halg = {
1090 .digestsize = SHA512_DIGEST_SIZE,
1091 .base = {
1092 .cra_name = "sha512",
1093 .cra_driver_name = "atmel-sha512",
1094 .cra_priority = 100,
1095 .cra_flags = CRYPTO_ALG_ASYNC,
1096 .cra_blocksize = SHA512_BLOCK_SIZE,
1097 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1098 .cra_alignmask = 0x3,
1099 .cra_module = THIS_MODULE,
1100 .cra_init = atmel_sha_cra_init,
1101 }
1102 }
1103 },
1104 };
1105
1106 static void atmel_sha_done_task(unsigned long data)
1107 {
1108 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1109 int err = 0;
1110
1111 if (!(SHA_FLAGS_BUSY & dd->flags)) {
1112 atmel_sha_handle_queue(dd, NULL);
1113 return;
1114 }
1115
1116 if (SHA_FLAGS_CPU & dd->flags) {
1117 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1118 dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
1119 goto finish;
1120 }
1121 } else if (SHA_FLAGS_DMA_READY & dd->flags) {
1122 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
1123 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
1124 atmel_sha_update_dma_stop(dd);
1125 if (dd->err) {
1126 err = dd->err;
1127 goto finish;
1128 }
1129 }
1130 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1131 /* hash or semi-hash ready */
1132 dd->flags &= ~(SHA_FLAGS_DMA_READY |
1133 SHA_FLAGS_OUTPUT_READY);
1134 err = atmel_sha_update_dma_start(dd);
1135 if (err != -EINPROGRESS)
1136 goto finish;
1137 }
1138 }
1139 return;
1140
1141 finish:
1142 /* finish curent request */
1143 atmel_sha_finish_req(dd->req, err);
1144 }
1145
1146 static irqreturn_t atmel_sha_irq(int irq, void *dev_id)
1147 {
1148 struct atmel_sha_dev *sha_dd = dev_id;
1149 u32 reg;
1150
1151 reg = atmel_sha_read(sha_dd, SHA_ISR);
1152 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) {
1153 atmel_sha_write(sha_dd, SHA_IDR, reg);
1154 if (SHA_FLAGS_BUSY & sha_dd->flags) {
1155 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY;
1156 if (!(SHA_FLAGS_CPU & sha_dd->flags))
1157 sha_dd->flags |= SHA_FLAGS_DMA_READY;
1158 tasklet_schedule(&sha_dd->done_task);
1159 } else {
1160 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n");
1161 }
1162 return IRQ_HANDLED;
1163 }
1164
1165 return IRQ_NONE;
1166 }
1167
1168 static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
1169 {
1170 int i;
1171
1172 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++)
1173 crypto_unregister_ahash(&sha_1_256_algs[i]);
1174
1175 if (dd->caps.has_sha224)
1176 crypto_unregister_ahash(&sha_224_alg);
1177
1178 if (dd->caps.has_sha_384_512) {
1179 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++)
1180 crypto_unregister_ahash(&sha_384_512_algs[i]);
1181 }
1182 }
1183
1184 static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
1185 {
1186 int err, i, j;
1187
1188 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
1189 err = crypto_register_ahash(&sha_1_256_algs[i]);
1190 if (err)
1191 goto err_sha_1_256_algs;
1192 }
1193
1194 if (dd->caps.has_sha224) {
1195 err = crypto_register_ahash(&sha_224_alg);
1196 if (err)
1197 goto err_sha_224_algs;
1198 }
1199
1200 if (dd->caps.has_sha_384_512) {
1201 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
1202 err = crypto_register_ahash(&sha_384_512_algs[i]);
1203 if (err)
1204 goto err_sha_384_512_algs;
1205 }
1206 }
1207
1208 return 0;
1209
1210 err_sha_384_512_algs:
1211 for (j = 0; j < i; j++)
1212 crypto_unregister_ahash(&sha_384_512_algs[j]);
1213 crypto_unregister_ahash(&sha_224_alg);
1214 err_sha_224_algs:
1215 i = ARRAY_SIZE(sha_1_256_algs);
1216 err_sha_1_256_algs:
1217 for (j = 0; j < i; j++)
1218 crypto_unregister_ahash(&sha_1_256_algs[j]);
1219
1220 return err;
1221 }
1222
1223 static bool atmel_sha_filter(struct dma_chan *chan, void *slave)
1224 {
1225 struct at_dma_slave *sl = slave;
1226
1227 if (sl && sl->dma_dev == chan->device->dev) {
1228 chan->private = sl;
1229 return true;
1230 } else {
1231 return false;
1232 }
1233 }
1234
1235 static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
1236 struct crypto_platform_data *pdata)
1237 {
1238 int err = -ENOMEM;
1239 dma_cap_mask_t mask_in;
1240
1241 /* Try to grab DMA channel */
1242 dma_cap_zero(mask_in);
1243 dma_cap_set(DMA_SLAVE, mask_in);
1244
1245 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in,
1246 atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
1247 if (!dd->dma_lch_in.chan) {
1248 dev_warn(dd->dev, "no DMA channel available\n");
1249 return err;
1250 }
1251
1252 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
1253 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
1254 SHA_REG_DIN(0);
1255 dd->dma_lch_in.dma_conf.src_maxburst = 1;
1256 dd->dma_lch_in.dma_conf.src_addr_width =
1257 DMA_SLAVE_BUSWIDTH_4_BYTES;
1258 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
1259 dd->dma_lch_in.dma_conf.dst_addr_width =
1260 DMA_SLAVE_BUSWIDTH_4_BYTES;
1261 dd->dma_lch_in.dma_conf.device_fc = false;
1262
1263 return 0;
1264 }
1265
1266 static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
1267 {
1268 dma_release_channel(dd->dma_lch_in.chan);
1269 }
1270
1271 static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
1272 {
1273
1274 dd->caps.has_dma = 0;
1275 dd->caps.has_dualbuff = 0;
1276 dd->caps.has_sha224 = 0;
1277 dd->caps.has_sha_384_512 = 0;
1278
1279 /* keep only major version number */
1280 switch (dd->hw_version & 0xff0) {
1281 case 0x420:
1282 dd->caps.has_dma = 1;
1283 dd->caps.has_dualbuff = 1;
1284 dd->caps.has_sha224 = 1;
1285 dd->caps.has_sha_384_512 = 1;
1286 break;
1287 case 0x410:
1288 dd->caps.has_dma = 1;
1289 dd->caps.has_dualbuff = 1;
1290 dd->caps.has_sha224 = 1;
1291 dd->caps.has_sha_384_512 = 1;
1292 break;
1293 case 0x400:
1294 dd->caps.has_dma = 1;
1295 dd->caps.has_dualbuff = 1;
1296 dd->caps.has_sha224 = 1;
1297 break;
1298 case 0x320:
1299 break;
1300 default:
1301 dev_warn(dd->dev,
1302 "Unmanaged sha version, set minimum capabilities\n");
1303 break;
1304 }
1305 }
1306
1307 #if defined(CONFIG_OF)
1308 static const struct of_device_id atmel_sha_dt_ids[] = {
1309 { .compatible = "atmel,at91sam9g46-sha" },
1310 { /* sentinel */ }
1311 };
1312
1313 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
1314
1315 static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev)
1316 {
1317 struct device_node *np = pdev->dev.of_node;
1318 struct crypto_platform_data *pdata;
1319
1320 if (!np) {
1321 dev_err(&pdev->dev, "device node not found\n");
1322 return ERR_PTR(-EINVAL);
1323 }
1324
1325 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1326 if (!pdata) {
1327 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1328 return ERR_PTR(-ENOMEM);
1329 }
1330
1331 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1332 sizeof(*(pdata->dma_slave)),
1333 GFP_KERNEL);
1334 if (!pdata->dma_slave) {
1335 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1336 return ERR_PTR(-ENOMEM);
1337 }
1338
1339 return pdata;
1340 }
1341 #else /* CONFIG_OF */
1342 static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev)
1343 {
1344 return ERR_PTR(-EINVAL);
1345 }
1346 #endif
1347
1348 static int atmel_sha_probe(struct platform_device *pdev)
1349 {
1350 struct atmel_sha_dev *sha_dd;
1351 struct crypto_platform_data *pdata;
1352 struct device *dev = &pdev->dev;
1353 struct resource *sha_res;
1354 int err;
1355
1356 sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL);
1357 if (sha_dd == NULL) {
1358 dev_err(dev, "unable to alloc data struct.\n");
1359 err = -ENOMEM;
1360 goto sha_dd_err;
1361 }
1362
1363 sha_dd->dev = dev;
1364
1365 platform_set_drvdata(pdev, sha_dd);
1366
1367 INIT_LIST_HEAD(&sha_dd->list);
1368 spin_lock_init(&sha_dd->lock);
1369
1370 tasklet_init(&sha_dd->done_task, atmel_sha_done_task,
1371 (unsigned long)sha_dd);
1372
1373 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH);
1374
1375 sha_dd->irq = -1;
1376
1377 /* Get the base address */
1378 sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1379 if (!sha_res) {
1380 dev_err(dev, "no MEM resource info\n");
1381 err = -ENODEV;
1382 goto res_err;
1383 }
1384 sha_dd->phys_base = sha_res->start;
1385
1386 /* Get the IRQ */
1387 sha_dd->irq = platform_get_irq(pdev, 0);
1388 if (sha_dd->irq < 0) {
1389 dev_err(dev, "no IRQ resource info\n");
1390 err = sha_dd->irq;
1391 goto res_err;
1392 }
1393
1394 err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq,
1395 IRQF_SHARED, "atmel-sha", sha_dd);
1396 if (err) {
1397 dev_err(dev, "unable to request sha irq.\n");
1398 goto res_err;
1399 }
1400
1401 /* Initializing the clock */
1402 sha_dd->iclk = devm_clk_get(&pdev->dev, "sha_clk");
1403 if (IS_ERR(sha_dd->iclk)) {
1404 dev_err(dev, "clock initialization failed.\n");
1405 err = PTR_ERR(sha_dd->iclk);
1406 goto res_err;
1407 }
1408
1409 sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res);
1410 if (IS_ERR(sha_dd->io_base)) {
1411 dev_err(dev, "can't ioremap\n");
1412 err = PTR_ERR(sha_dd->io_base);
1413 goto res_err;
1414 }
1415
1416 err = clk_prepare(sha_dd->iclk);
1417 if (err)
1418 goto res_err;
1419
1420 atmel_sha_hw_version_init(sha_dd);
1421
1422 atmel_sha_get_cap(sha_dd);
1423
1424 if (sha_dd->caps.has_dma) {
1425 pdata = pdev->dev.platform_data;
1426 if (!pdata) {
1427 pdata = atmel_sha_of_init(pdev);
1428 if (IS_ERR(pdata)) {
1429 dev_err(&pdev->dev, "platform data not available\n");
1430 err = PTR_ERR(pdata);
1431 goto iclk_unprepare;
1432 }
1433 }
1434 if (!pdata->dma_slave) {
1435 err = -ENXIO;
1436 goto iclk_unprepare;
1437 }
1438 err = atmel_sha_dma_init(sha_dd, pdata);
1439 if (err)
1440 goto err_sha_dma;
1441
1442 dev_info(dev, "using %s for DMA transfers\n",
1443 dma_chan_name(sha_dd->dma_lch_in.chan));
1444 }
1445
1446 spin_lock(&atmel_sha.lock);
1447 list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
1448 spin_unlock(&atmel_sha.lock);
1449
1450 err = atmel_sha_register_algs(sha_dd);
1451 if (err)
1452 goto err_algs;
1453
1454 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
1455 sha_dd->caps.has_sha224 ? "/SHA224" : "",
1456 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
1457
1458 return 0;
1459
1460 err_algs:
1461 spin_lock(&atmel_sha.lock);
1462 list_del(&sha_dd->list);
1463 spin_unlock(&atmel_sha.lock);
1464 if (sha_dd->caps.has_dma)
1465 atmel_sha_dma_cleanup(sha_dd);
1466 err_sha_dma:
1467 iclk_unprepare:
1468 clk_unprepare(sha_dd->iclk);
1469 res_err:
1470 tasklet_kill(&sha_dd->done_task);
1471 sha_dd_err:
1472 dev_err(dev, "initialization failed.\n");
1473
1474 return err;
1475 }
1476
1477 static int atmel_sha_remove(struct platform_device *pdev)
1478 {
1479 static struct atmel_sha_dev *sha_dd;
1480
1481 sha_dd = platform_get_drvdata(pdev);
1482 if (!sha_dd)
1483 return -ENODEV;
1484 spin_lock(&atmel_sha.lock);
1485 list_del(&sha_dd->list);
1486 spin_unlock(&atmel_sha.lock);
1487
1488 atmel_sha_unregister_algs(sha_dd);
1489
1490 tasklet_kill(&sha_dd->done_task);
1491
1492 if (sha_dd->caps.has_dma)
1493 atmel_sha_dma_cleanup(sha_dd);
1494
1495 clk_unprepare(sha_dd->iclk);
1496
1497 return 0;
1498 }
1499
1500 static struct platform_driver atmel_sha_driver = {
1501 .probe = atmel_sha_probe,
1502 .remove = atmel_sha_remove,
1503 .driver = {
1504 .name = "atmel_sha",
1505 .of_match_table = of_match_ptr(atmel_sha_dt_ids),
1506 },
1507 };
1508
1509 module_platform_driver(atmel_sha_driver);
1510
1511 MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
1512 MODULE_LICENSE("GPL v2");
1513 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
Linux with added FPC-III support