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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / crypto / mxs-dcp.c
blobfe8cfe24c518f09b4c912766689ef95d9aa5c5ce
1 /*
2 * Freescale i.MX23/i.MX28 Data Co-Processor driver
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 #include <linux/crypto.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/stmp_device.h>
24
25 #include <crypto/aes.h>
26 #include <crypto/sha.h>
27 #include <crypto/internal/hash.h>
28
29 #define DCP_MAX_CHANS 4
30 #define DCP_BUF_SZ PAGE_SIZE
31
32 #define DCP_ALIGNMENT 64
33
34 /* DCP DMA descriptor. */
35 struct dcp_dma_desc {
36 uint32_t next_cmd_addr;
37 uint32_t control0;
38 uint32_t control1;
39 uint32_t source;
40 uint32_t destination;
41 uint32_t size;
42 uint32_t payload;
43 uint32_t status;
44 };
45
46 /* Coherent aligned block for bounce buffering. */
47 struct dcp_coherent_block {
48 uint8_t aes_in_buf[DCP_BUF_SZ];
49 uint8_t aes_out_buf[DCP_BUF_SZ];
50 uint8_t sha_in_buf[DCP_BUF_SZ];
51
52 uint8_t aes_key[2 * AES_KEYSIZE_128];
53
54 struct dcp_dma_desc desc[DCP_MAX_CHANS];
55 };
56
57 struct dcp {
58 struct device *dev;
59 void __iomem *base;
60
61 uint32_t caps;
62
63 struct dcp_coherent_block *coh;
64
65 struct completion completion[DCP_MAX_CHANS];
66 spinlock_t lock[DCP_MAX_CHANS];
67 struct task_struct *thread[DCP_MAX_CHANS];
68 struct crypto_queue queue[DCP_MAX_CHANS];
69 };
70
71 enum dcp_chan {
72 DCP_CHAN_HASH_SHA = 0,
73 DCP_CHAN_CRYPTO = 2,
74 };
75
76 struct dcp_async_ctx {
77 /* Common context */
78 enum dcp_chan chan;
79 uint32_t fill;
80
81 /* SHA Hash-specific context */
82 struct mutex mutex;
83 uint32_t alg;
84 unsigned int hot:1;
85
86 /* Crypto-specific context */
87 struct crypto_ablkcipher *fallback;
88 unsigned int key_len;
89 uint8_t key[AES_KEYSIZE_128];
90 };
91
92 struct dcp_aes_req_ctx {
93 unsigned int enc:1;
94 unsigned int ecb:1;
95 };
96
97 struct dcp_sha_req_ctx {
98 unsigned int init:1;
99 unsigned int fini:1;
100 };
101
102 /*
103 * There can even be only one instance of the MXS DCP due to the
104 * design of Linux Crypto API.
105 */
106 static struct dcp *global_sdcp;
107
108 /* DCP register layout. */
109 #define MXS_DCP_CTRL 0x00
110 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
111 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
112
113 #define MXS_DCP_STAT 0x10
114 #define MXS_DCP_STAT_CLR 0x18
115 #define MXS_DCP_STAT_IRQ_MASK 0xf
116
117 #define MXS_DCP_CHANNELCTRL 0x20
118 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
119
120 #define MXS_DCP_CAPABILITY1 0x40
121 #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
122 #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
123 #define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
124
125 #define MXS_DCP_CONTEXT 0x50
126
127 #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
128
129 #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
130
131 #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
132 #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
133
134 /* DMA descriptor bits. */
135 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
136 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
137 #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
138 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
139 #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
140 #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
141 #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
142 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
143 #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
144
145 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
146 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
147 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
148 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
149 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
150
151 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
152 {
153 struct dcp *sdcp = global_sdcp;
154 const int chan = actx->chan;
155 uint32_t stat;
156 unsigned long ret;
157 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
158
159 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
160 DMA_TO_DEVICE);
161
162 reinit_completion(&sdcp->completion[chan]);
163
164 /* Clear status register. */
165 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
166
167 /* Load the DMA descriptor. */
168 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
169
170 /* Increment the semaphore to start the DMA transfer. */
171 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
172
173 ret = wait_for_completion_timeout(&sdcp->completion[chan],
174 msecs_to_jiffies(1000));
175 if (!ret) {
176 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
177 chan, readl(sdcp->base + MXS_DCP_STAT));
178 return -ETIMEDOUT;
179 }
180
181 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
182 if (stat & 0xff) {
183 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
184 chan, stat);
185 return -EINVAL;
186 }
187
188 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
189
190 return 0;
191 }
192
193 /*
194 * Encryption (AES128)
195 */
196 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
197 struct ablkcipher_request *req, int init)
198 {
199 struct dcp *sdcp = global_sdcp;
200 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
201 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
202 int ret;
203
204 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
205 2 * AES_KEYSIZE_128,
206 DMA_TO_DEVICE);
207 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
208 DCP_BUF_SZ, DMA_TO_DEVICE);
209 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
210 DCP_BUF_SZ, DMA_FROM_DEVICE);
211
212 /* Fill in the DMA descriptor. */
213 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
214 MXS_DCP_CONTROL0_INTERRUPT |
215 MXS_DCP_CONTROL0_ENABLE_CIPHER;
216
217 /* Payload contains the key. */
218 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
219
220 if (rctx->enc)
221 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
222 if (init)
223 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
224
225 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
226
227 if (rctx->ecb)
228 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
229 else
230 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
231
232 desc->next_cmd_addr = 0;
233 desc->source = src_phys;
234 desc->destination = dst_phys;
235 desc->size = actx->fill;
236 desc->payload = key_phys;
237 desc->status = 0;
238
239 ret = mxs_dcp_start_dma(actx);
240
241 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
242 DMA_TO_DEVICE);
243 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
244 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
245
246 return ret;
247 }
248
249 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
250 {
251 struct dcp *sdcp = global_sdcp;
252
253 struct ablkcipher_request *req = ablkcipher_request_cast(arq);
254 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
255 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
256
257 struct scatterlist *dst = req->dst;
258 struct scatterlist *src = req->src;
259 const int nents = sg_nents(req->src);
260
261 const int out_off = DCP_BUF_SZ;
262 uint8_t *in_buf = sdcp->coh->aes_in_buf;
263 uint8_t *out_buf = sdcp->coh->aes_out_buf;
264
265 uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
266 uint32_t dst_off = 0;
267
268 uint8_t *key = sdcp->coh->aes_key;
269
270 int ret = 0;
271 int split = 0;
272 unsigned int i, len, clen, rem = 0;
273 int init = 0;
274
275 actx->fill = 0;
276
277 /* Copy the key from the temporary location. */
278 memcpy(key, actx->key, actx->key_len);
279
280 if (!rctx->ecb) {
281 /* Copy the CBC IV just past the key. */
282 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
283 /* CBC needs the INIT set. */
284 init = 1;
285 } else {
286 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
287 }
288
289 for_each_sg(req->src, src, nents, i) {
290 src_buf = sg_virt(src);
291 len = sg_dma_len(src);
292
293 do {
294 if (actx->fill + len > out_off)
295 clen = out_off - actx->fill;
296 else
297 clen = len;
298
299 memcpy(in_buf + actx->fill, src_buf, clen);
300 len -= clen;
301 src_buf += clen;
302 actx->fill += clen;
303
304 /*
305 * If we filled the buffer or this is the last SG,
306 * submit the buffer.
307 */
308 if (actx->fill == out_off || sg_is_last(src)) {
309 ret = mxs_dcp_run_aes(actx, req, init);
310 if (ret)
311 return ret;
312 init = 0;
313
314 out_tmp = out_buf;
315 while (dst && actx->fill) {
316 if (!split) {
317 dst_buf = sg_virt(dst);
318 dst_off = 0;
319 }
320 rem = min(sg_dma_len(dst) - dst_off,
321 actx->fill);
322
323 memcpy(dst_buf + dst_off, out_tmp, rem);
324 out_tmp += rem;
325 dst_off += rem;
326 actx->fill -= rem;
327
328 if (dst_off == sg_dma_len(dst)) {
329 dst = sg_next(dst);
330 split = 0;
331 } else {
332 split = 1;
333 }
334 }
335 }
336 } while (len);
337 }
338
339 return ret;
340 }
341
342 static int dcp_chan_thread_aes(void *data)
343 {
344 struct dcp *sdcp = global_sdcp;
345 const int chan = DCP_CHAN_CRYPTO;
346
347 struct crypto_async_request *backlog;
348 struct crypto_async_request *arq;
349
350 int ret;
351
352 while (!kthread_should_stop()) {
353 set_current_state(TASK_INTERRUPTIBLE);
354
355 spin_lock(&sdcp->lock[chan]);
356 backlog = crypto_get_backlog(&sdcp->queue[chan]);
357 arq = crypto_dequeue_request(&sdcp->queue[chan]);
358 spin_unlock(&sdcp->lock[chan]);
359
360 if (!backlog && !arq) {
361 schedule();
362 continue;
363 }
364
365 set_current_state(TASK_RUNNING);
366
367 if (backlog)
368 backlog->complete(backlog, -EINPROGRESS);
369
370 if (arq) {
371 ret = mxs_dcp_aes_block_crypt(arq);
372 arq->complete(arq, ret);
373 }
374 }
375
376 return 0;
377 }
378
379 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
380 {
381 struct crypto_tfm *tfm =
382 crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
383 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(
384 crypto_ablkcipher_reqtfm(req));
385 int ret;
386
387 ablkcipher_request_set_tfm(req, ctx->fallback);
388
389 if (enc)
390 ret = crypto_ablkcipher_encrypt(req);
391 else
392 ret = crypto_ablkcipher_decrypt(req);
393
394 ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm));
395
396 return ret;
397 }
398
399 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
400 {
401 struct dcp *sdcp = global_sdcp;
402 struct crypto_async_request *arq = &req->base;
403 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
404 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
405 int ret;
406
407 if (unlikely(actx->key_len != AES_KEYSIZE_128))
408 return mxs_dcp_block_fallback(req, enc);
409
410 rctx->enc = enc;
411 rctx->ecb = ecb;
412 actx->chan = DCP_CHAN_CRYPTO;
413
414 spin_lock(&sdcp->lock[actx->chan]);
415 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
416 spin_unlock(&sdcp->lock[actx->chan]);
417
418 wake_up_process(sdcp->thread[actx->chan]);
419
420 return -EINPROGRESS;
421 }
422
423 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
424 {
425 return mxs_dcp_aes_enqueue(req, 0, 1);
426 }
427
428 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
429 {
430 return mxs_dcp_aes_enqueue(req, 1, 1);
431 }
432
433 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
434 {
435 return mxs_dcp_aes_enqueue(req, 0, 0);
436 }
437
438 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
439 {
440 return mxs_dcp_aes_enqueue(req, 1, 0);
441 }
442
443 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
444 unsigned int len)
445 {
446 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
447 unsigned int ret;
448
449 /*
450 * AES 128 is supposed by the hardware, store key into temporary
451 * buffer and exit. We must use the temporary buffer here, since
452 * there can still be an operation in progress.
453 */
454 actx->key_len = len;
455 if (len == AES_KEYSIZE_128) {
456 memcpy(actx->key, key, len);
457 return 0;
458 }
459
460 /* Check if the key size is supported by kernel at all. */
461 if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
462 tfm->base.crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
463 return -EINVAL;
464 }
465
466 /*
467 * If the requested AES key size is not supported by the hardware,
468 * but is supported by in-kernel software implementation, we use
469 * software fallback.
470 */
471 actx->fallback->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
472 actx->fallback->base.crt_flags |=
473 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK;
474
475 ret = crypto_ablkcipher_setkey(actx->fallback, key, len);
476 if (!ret)
477 return 0;
478
479 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
480 tfm->base.crt_flags |=
481 actx->fallback->base.crt_flags & CRYPTO_TFM_RES_MASK;
482
483 return ret;
484 }
485
486 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
487 {
488 const char *name = crypto_tfm_alg_name(tfm);
489 const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
490 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
491 struct crypto_ablkcipher *blk;
492
493 blk = crypto_alloc_ablkcipher(name, 0, flags);
494 if (IS_ERR(blk))
495 return PTR_ERR(blk);
496
497 actx->fallback = blk;
498 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
499 return 0;
500 }
501
502 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
503 {
504 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
505
506 crypto_free_ablkcipher(actx->fallback);
507 actx->fallback = NULL;
508 }
509
510 /*
511 * Hashing (SHA1/SHA256)
512 */
513 static int mxs_dcp_run_sha(struct ahash_request *req)
514 {
515 struct dcp *sdcp = global_sdcp;
516 int ret;
517
518 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
519 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
520 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
521 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
522
523 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
524
525 dma_addr_t digest_phys = 0;
526 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
527 DCP_BUF_SZ, DMA_TO_DEVICE);
528
529 /* Fill in the DMA descriptor. */
530 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
531 MXS_DCP_CONTROL0_INTERRUPT |
532 MXS_DCP_CONTROL0_ENABLE_HASH;
533 if (rctx->init)
534 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
535
536 desc->control1 = actx->alg;
537 desc->next_cmd_addr = 0;
538 desc->source = buf_phys;
539 desc->destination = 0;
540 desc->size = actx->fill;
541 desc->payload = 0;
542 desc->status = 0;
543
544 /* Set HASH_TERM bit for last transfer block. */
545 if (rctx->fini) {
546 digest_phys = dma_map_single(sdcp->dev, req->result,
547 halg->digestsize, DMA_FROM_DEVICE);
548 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
549 desc->payload = digest_phys;
550 }
551
552 ret = mxs_dcp_start_dma(actx);
553
554 if (rctx->fini)
555 dma_unmap_single(sdcp->dev, digest_phys, halg->digestsize,
556 DMA_FROM_DEVICE);
557
558 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
559
560 return ret;
561 }
562
563 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
564 {
565 struct dcp *sdcp = global_sdcp;
566
567 struct ahash_request *req = ahash_request_cast(arq);
568 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
569 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
570 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
571 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
572 const int nents = sg_nents(req->src);
573
574 uint8_t *in_buf = sdcp->coh->sha_in_buf;
575
576 uint8_t *src_buf;
577
578 struct scatterlist *src;
579
580 unsigned int i, len, clen;
581 int ret;
582
583 int fin = rctx->fini;
584 if (fin)
585 rctx->fini = 0;
586
587 for_each_sg(req->src, src, nents, i) {
588 src_buf = sg_virt(src);
589 len = sg_dma_len(src);
590
591 do {
592 if (actx->fill + len > DCP_BUF_SZ)
593 clen = DCP_BUF_SZ - actx->fill;
594 else
595 clen = len;
596
597 memcpy(in_buf + actx->fill, src_buf, clen);
598 len -= clen;
599 src_buf += clen;
600 actx->fill += clen;
601
602 /*
603 * If we filled the buffer and still have some
604 * more data, submit the buffer.
605 */
606 if (len && actx->fill == DCP_BUF_SZ) {
607 ret = mxs_dcp_run_sha(req);
608 if (ret)
609 return ret;
610 actx->fill = 0;
611 rctx->init = 0;
612 }
613 } while (len);
614 }
615
616 if (fin) {
617 rctx->fini = 1;
618
619 /* Submit whatever is left. */
620 if (!req->result)
621 return -EINVAL;
622
623 ret = mxs_dcp_run_sha(req);
624 if (ret)
625 return ret;
626
627 actx->fill = 0;
628
629 /* For some reason, the result is flipped. */
630 for (i = 0; i < halg->digestsize / 2; i++) {
631 swap(req->result[i],
632 req->result[halg->digestsize - i - 1]);
633 }
634 }
635
636 return 0;
637 }
638
639 static int dcp_chan_thread_sha(void *data)
640 {
641 struct dcp *sdcp = global_sdcp;
642 const int chan = DCP_CHAN_HASH_SHA;
643
644 struct crypto_async_request *backlog;
645 struct crypto_async_request *arq;
646
647 struct dcp_sha_req_ctx *rctx;
648
649 struct ahash_request *req;
650 int ret, fini;
651
652 while (!kthread_should_stop()) {
653 set_current_state(TASK_INTERRUPTIBLE);
654
655 spin_lock(&sdcp->lock[chan]);
656 backlog = crypto_get_backlog(&sdcp->queue[chan]);
657 arq = crypto_dequeue_request(&sdcp->queue[chan]);
658 spin_unlock(&sdcp->lock[chan]);
659
660 if (!backlog && !arq) {
661 schedule();
662 continue;
663 }
664
665 set_current_state(TASK_RUNNING);
666
667 if (backlog)
668 backlog->complete(backlog, -EINPROGRESS);
669
670 if (arq) {
671 req = ahash_request_cast(arq);
672 rctx = ahash_request_ctx(req);
673
674 ret = dcp_sha_req_to_buf(arq);
675 fini = rctx->fini;
676 arq->complete(arq, ret);
677 }
678 }
679
680 return 0;
681 }
682
683 static int dcp_sha_init(struct ahash_request *req)
684 {
685 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
686 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
687
688 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
689
690 /*
691 * Start hashing session. The code below only inits the
692 * hashing session context, nothing more.
693 */
694 memset(actx, 0, sizeof(*actx));
695
696 if (strcmp(halg->base.cra_name, "sha1") == 0)
697 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
698 else
699 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
700
701 actx->fill = 0;
702 actx->hot = 0;
703 actx->chan = DCP_CHAN_HASH_SHA;
704
705 mutex_init(&actx->mutex);
706
707 return 0;
708 }
709
710 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
711 {
712 struct dcp *sdcp = global_sdcp;
713
714 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
715 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
716 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
717
718 int ret;
719
720 /*
721 * Ignore requests that have no data in them and are not
722 * the trailing requests in the stream of requests.
723 */
724 if (!req->nbytes && !fini)
725 return 0;
726
727 mutex_lock(&actx->mutex);
728
729 rctx->fini = fini;
730
731 if (!actx->hot) {
732 actx->hot = 1;
733 rctx->init = 1;
734 }
735
736 spin_lock(&sdcp->lock[actx->chan]);
737 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
738 spin_unlock(&sdcp->lock[actx->chan]);
739
740 wake_up_process(sdcp->thread[actx->chan]);
741 mutex_unlock(&actx->mutex);
742
743 return -EINPROGRESS;
744 }
745
746 static int dcp_sha_update(struct ahash_request *req)
747 {
748 return dcp_sha_update_fx(req, 0);
749 }
750
751 static int dcp_sha_final(struct ahash_request *req)
752 {
753 ahash_request_set_crypt(req, NULL, req->result, 0);
754 req->nbytes = 0;
755 return dcp_sha_update_fx(req, 1);
756 }
757
758 static int dcp_sha_finup(struct ahash_request *req)
759 {
760 return dcp_sha_update_fx(req, 1);
761 }
762
763 static int dcp_sha_digest(struct ahash_request *req)
764 {
765 int ret;
766
767 ret = dcp_sha_init(req);
768 if (ret)
769 return ret;
770
771 return dcp_sha_finup(req);
772 }
773
774 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
775 {
776 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
777 sizeof(struct dcp_sha_req_ctx));
778 return 0;
779 }
780
781 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
782 {
783 }
784
785 /* AES 128 ECB and AES 128 CBC */
786 static struct crypto_alg dcp_aes_algs[] = {
787 {
788 .cra_name = "ecb(aes)",
789 .cra_driver_name = "ecb-aes-dcp",
790 .cra_priority = 400,
791 .cra_alignmask = 15,
792 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
793 CRYPTO_ALG_ASYNC |
794 CRYPTO_ALG_NEED_FALLBACK,
795 .cra_init = mxs_dcp_aes_fallback_init,
796 .cra_exit = mxs_dcp_aes_fallback_exit,
797 .cra_blocksize = AES_BLOCK_SIZE,
798 .cra_ctxsize = sizeof(struct dcp_async_ctx),
799 .cra_type = &crypto_ablkcipher_type,
800 .cra_module = THIS_MODULE,
801 .cra_u = {
802 .ablkcipher = {
803 .min_keysize = AES_MIN_KEY_SIZE,
804 .max_keysize = AES_MAX_KEY_SIZE,
805 .setkey = mxs_dcp_aes_setkey,
806 .encrypt = mxs_dcp_aes_ecb_encrypt,
807 .decrypt = mxs_dcp_aes_ecb_decrypt
808 },
809 },
810 }, {
811 .cra_name = "cbc(aes)",
812 .cra_driver_name = "cbc-aes-dcp",
813 .cra_priority = 400,
814 .cra_alignmask = 15,
815 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
816 CRYPTO_ALG_ASYNC |
817 CRYPTO_ALG_NEED_FALLBACK,
818 .cra_init = mxs_dcp_aes_fallback_init,
819 .cra_exit = mxs_dcp_aes_fallback_exit,
820 .cra_blocksize = AES_BLOCK_SIZE,
821 .cra_ctxsize = sizeof(struct dcp_async_ctx),
822 .cra_type = &crypto_ablkcipher_type,
823 .cra_module = THIS_MODULE,
824 .cra_u = {
825 .ablkcipher = {
826 .min_keysize = AES_MIN_KEY_SIZE,
827 .max_keysize = AES_MAX_KEY_SIZE,
828 .setkey = mxs_dcp_aes_setkey,
829 .encrypt = mxs_dcp_aes_cbc_encrypt,
830 .decrypt = mxs_dcp_aes_cbc_decrypt,
831 .ivsize = AES_BLOCK_SIZE,
832 },
833 },
834 },
835 };
836
837 /* SHA1 */
838 static struct ahash_alg dcp_sha1_alg = {
839 .init = dcp_sha_init,
840 .update = dcp_sha_update,
841 .final = dcp_sha_final,
842 .finup = dcp_sha_finup,
843 .digest = dcp_sha_digest,
844 .halg = {
845 .digestsize = SHA1_DIGEST_SIZE,
846 .base = {
847 .cra_name = "sha1",
848 .cra_driver_name = "sha1-dcp",
849 .cra_priority = 400,
850 .cra_alignmask = 63,
851 .cra_flags = CRYPTO_ALG_ASYNC,
852 .cra_blocksize = SHA1_BLOCK_SIZE,
853 .cra_ctxsize = sizeof(struct dcp_async_ctx),
854 .cra_module = THIS_MODULE,
855 .cra_init = dcp_sha_cra_init,
856 .cra_exit = dcp_sha_cra_exit,
857 },
858 },
859 };
860
861 /* SHA256 */
862 static struct ahash_alg dcp_sha256_alg = {
863 .init = dcp_sha_init,
864 .update = dcp_sha_update,
865 .final = dcp_sha_final,
866 .finup = dcp_sha_finup,
867 .digest = dcp_sha_digest,
868 .halg = {
869 .digestsize = SHA256_DIGEST_SIZE,
870 .base = {
871 .cra_name = "sha256",
872 .cra_driver_name = "sha256-dcp",
873 .cra_priority = 400,
874 .cra_alignmask = 63,
875 .cra_flags = CRYPTO_ALG_ASYNC,
876 .cra_blocksize = SHA256_BLOCK_SIZE,
877 .cra_ctxsize = sizeof(struct dcp_async_ctx),
878 .cra_module = THIS_MODULE,
879 .cra_init = dcp_sha_cra_init,
880 .cra_exit = dcp_sha_cra_exit,
881 },
882 },
883 };
884
885 static irqreturn_t mxs_dcp_irq(int irq, void *context)
886 {
887 struct dcp *sdcp = context;
888 uint32_t stat;
889 int i;
890
891 stat = readl(sdcp->base + MXS_DCP_STAT);
892 stat &= MXS_DCP_STAT_IRQ_MASK;
893 if (!stat)
894 return IRQ_NONE;
895
896 /* Clear the interrupts. */
897 writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
898
899 /* Complete the DMA requests that finished. */
900 for (i = 0; i < DCP_MAX_CHANS; i++)
901 if (stat & (1 << i))
902 complete(&sdcp->completion[i]);
903
904 return IRQ_HANDLED;
905 }
906
907 static int mxs_dcp_probe(struct platform_device *pdev)
908 {
909 struct device *dev = &pdev->dev;
910 struct dcp *sdcp = NULL;
911 int i, ret;
912
913 struct resource *iores;
914 int dcp_vmi_irq, dcp_irq;
915
916 if (global_sdcp) {
917 dev_err(dev, "Only one DCP instance allowed!\n");
918 return -ENODEV;
919 }
920
921 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 dcp_vmi_irq = platform_get_irq(pdev, 0);
923 if (dcp_vmi_irq < 0)
924 return dcp_vmi_irq;
925
926 dcp_irq = platform_get_irq(pdev, 1);
927 if (dcp_irq < 0)
928 return dcp_irq;
929
930 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
931 if (!sdcp)
932 return -ENOMEM;
933
934 sdcp->dev = dev;
935 sdcp->base = devm_ioremap_resource(dev, iores);
936 if (IS_ERR(sdcp->base))
937 return PTR_ERR(sdcp->base);
938
939
940 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
941 "dcp-vmi-irq", sdcp);
942 if (ret) {
943 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
944 return ret;
945 }
946
947 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
948 "dcp-irq", sdcp);
949 if (ret) {
950 dev_err(dev, "Failed to claim DCP IRQ!\n");
951 return ret;
952 }
953
954 /* Allocate coherent helper block. */
955 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
956 GFP_KERNEL);
957 if (!sdcp->coh)
958 return -ENOMEM;
959
960 /* Re-align the structure so it fits the DCP constraints. */
961 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
962
963 /* Restart the DCP block. */
964 ret = stmp_reset_block(sdcp->base);
965 if (ret)
966 return ret;
967
968 /* Initialize control register. */
969 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
970 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
971 sdcp->base + MXS_DCP_CTRL);
972
973 /* Enable all DCP DMA channels. */
974 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
975 sdcp->base + MXS_DCP_CHANNELCTRL);
976
977 /*
978 * We do not enable context switching. Give the context buffer a
979 * pointer to an illegal address so if context switching is
980 * inadvertantly enabled, the DCP will return an error instead of
981 * trashing good memory. The DCP DMA cannot access ROM, so any ROM
982 * address will do.
983 */
984 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
985 for (i = 0; i < DCP_MAX_CHANS; i++)
986 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
987 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
988
989 global_sdcp = sdcp;
990
991 platform_set_drvdata(pdev, sdcp);
992
993 for (i = 0; i < DCP_MAX_CHANS; i++) {
994 spin_lock_init(&sdcp->lock[i]);
995 init_completion(&sdcp->completion[i]);
996 crypto_init_queue(&sdcp->queue[i], 50);
997 }
998
999 /* Create the SHA and AES handler threads. */
1000 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1001 NULL, "mxs_dcp_chan/sha");
1002 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1003 dev_err(dev, "Error starting SHA thread!\n");
1004 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1005 }
1006
1007 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1008 NULL, "mxs_dcp_chan/aes");
1009 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1010 dev_err(dev, "Error starting SHA thread!\n");
1011 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1012 goto err_destroy_sha_thread;
1013 }
1014
1015 /* Register the various crypto algorithms. */
1016 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1017
1018 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1019 ret = crypto_register_algs(dcp_aes_algs,
1020 ARRAY_SIZE(dcp_aes_algs));
1021 if (ret) {
1022 /* Failed to register algorithm. */
1023 dev_err(dev, "Failed to register AES crypto!\n");
1024 goto err_destroy_aes_thread;
1025 }
1026 }
1027
1028 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1029 ret = crypto_register_ahash(&dcp_sha1_alg);
1030 if (ret) {
1031 dev_err(dev, "Failed to register %s hash!\n",
1032 dcp_sha1_alg.halg.base.cra_name);
1033 goto err_unregister_aes;
1034 }
1035 }
1036
1037 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1038 ret = crypto_register_ahash(&dcp_sha256_alg);
1039 if (ret) {
1040 dev_err(dev, "Failed to register %s hash!\n",
1041 dcp_sha256_alg.halg.base.cra_name);
1042 goto err_unregister_sha1;
1043 }
1044 }
1045
1046 return 0;
1047
1048 err_unregister_sha1:
1049 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1050 crypto_unregister_ahash(&dcp_sha1_alg);
1051
1052 err_unregister_aes:
1053 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1054 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1055
1056 err_destroy_aes_thread:
1057 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1058
1059 err_destroy_sha_thread:
1060 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1061 return ret;
1062 }
1063
1064 static int mxs_dcp_remove(struct platform_device *pdev)
1065 {
1066 struct dcp *sdcp = platform_get_drvdata(pdev);
1067
1068 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1069 crypto_unregister_ahash(&dcp_sha256_alg);
1070
1071 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1072 crypto_unregister_ahash(&dcp_sha1_alg);
1073
1074 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1075 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1076
1077 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1078 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1079
1080 platform_set_drvdata(pdev, NULL);
1081
1082 global_sdcp = NULL;
1083
1084 return 0;
1085 }
1086
1087 static const struct of_device_id mxs_dcp_dt_ids[] = {
1088 { .compatible = "fsl,imx23-dcp", .data = NULL, },
1089 { .compatible = "fsl,imx28-dcp", .data = NULL, },
1090 { /* sentinel */ }
1091 };
1092
1093 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1094
1095 static struct platform_driver mxs_dcp_driver = {
1096 .probe = mxs_dcp_probe,
1097 .remove = mxs_dcp_remove,
1098 .driver = {
1099 .name = "mxs-dcp",
1100 .of_match_table = mxs_dcp_dt_ids,
1101 },
1102 };
1103
1104 module_platform_driver(mxs_dcp_driver);
1105
1106 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1107 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1108 MODULE_LICENSE("GPL");
1109 MODULE_ALIAS("platform:mxs-dcp");
Linux with added FPC-III support