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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / firewire / ohci.c
blob5545a7f3a98f35456a144dd022dc34015cc37136
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
61 #define DESCRIPTOR_OUTPUT_MORE 0
62 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63 #define DESCRIPTOR_INPUT_MORE (2 << 12)
64 #define DESCRIPTOR_INPUT_LAST (3 << 12)
65 #define DESCRIPTOR_STATUS (1 << 11)
66 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67 #define DESCRIPTOR_PING (1 << 7)
68 #define DESCRIPTOR_YY (1 << 6)
69 #define DESCRIPTOR_NO_IRQ (0 << 4)
70 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
71 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73 #define DESCRIPTOR_WAIT (3 << 0)
74
75 #define DESCRIPTOR_CMD (0xf << 12)
76
77 struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84 } __attribute__((aligned(16)));
85
86 #define CONTROL_SET(regs) (regs)
87 #define CONTROL_CLEAR(regs) ((regs) + 4)
88 #define COMMAND_PTR(regs) ((regs) + 12)
89 #define CONTEXT_MATCH(regs) ((regs) + 16)
90
91 #define AR_BUFFER_SIZE (32*1024)
92 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93 /* we need at least two pages for proper list management */
94 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96 #define MAX_ASYNC_PAYLOAD 4096
97 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
99
100 struct ar_context {
101 struct fw_ohci *ohci;
102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
106 void *pointer;
107 unsigned int last_buffer_index;
108 u32 regs;
109 struct tasklet_struct tasklet;
110 };
111
112 struct context;
113
114 typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
117
118 /*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122 struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128 };
129
130 struct context {
131 struct fw_ohci *ohci;
132 u32 regs;
133 int total_allocation;
134 u32 current_bus;
135 bool running;
136 bool flushing;
137
138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
158 * The last descriptor block in the DMA program. It contains the branch
159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
162 int prev_z;
163
164 descriptor_callback_t callback;
165
166 struct tasklet_struct tasklet;
167 };
168
169 #define IT_HEADER_SY(v) ((v) << 0)
170 #define IT_HEADER_TCODE(v) ((v) << 4)
171 #define IT_HEADER_CHANNEL(v) ((v) << 8)
172 #define IT_HEADER_TAG(v) ((v) << 14)
173 #define IT_HEADER_SPEED(v) ((v) << 16)
174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
175
176 struct iso_context {
177 struct fw_iso_context base;
178 struct context context;
179 void *header;
180 size_t header_length;
181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
184 u16 last_timestamp;
185 u8 sync;
186 u8 tags;
187 };
188
189 #define CONFIG_ROM_SIZE 1024
190
191 struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
195 int node_id;
196 int generation;
197 int request_generation; /* for timestamping incoming requests */
198 unsigned quirks;
199 unsigned int pri_req_max;
200 u32 bus_time;
201 bool bus_time_running;
202 bool is_root;
203 bool csr_state_setclear_abdicate;
204 int n_ir;
205 int n_it;
206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
210 spinlock_t lock;
211
212 struct mutex phy_reg_mutex;
213
214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
219 struct context at_request_ctx;
220 struct context at_response_ctx;
221
222 u32 it_context_support;
223 u32 it_context_mask; /* unoccupied IT contexts */
224 struct iso_context *it_context_list;
225 u64 ir_context_channels; /* unoccupied channels */
226 u32 ir_context_support;
227 u32 ir_context_mask; /* unoccupied IR contexts */
228 struct iso_context *ir_context_list;
229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
238 __le32 *self_id;
239 dma_addr_t self_id_bus;
240 struct work_struct bus_reset_work;
241
242 u32 self_id_buffer[512];
243 };
244
245 static struct workqueue_struct *selfid_workqueue;
246
247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
248 {
249 return container_of(card, struct fw_ohci, card);
250 }
251
252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253 #define IR_CONTEXT_BUFFER_FILL 0x80000000
254 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
258
259 #define CONTEXT_RUN 0x8000
260 #define CONTEXT_WAKE 0x1000
261 #define CONTEXT_DEAD 0x0800
262 #define CONTEXT_ACTIVE 0x0400
263
264 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
265 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
268 #define OHCI1394_REGISTER_SIZE 0x800
269 #define OHCI1394_PCI_HCI_Control 0x40
270 #define SELF_ID_BUF_SIZE 0x800
271 #define OHCI_TCODE_PHY_PACKET 0x0e
272 #define OHCI_VERSION_1_1 0x010010
273
274 static char ohci_driver_name[] = KBUILD_MODNAME;
275
276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
277 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
278 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
280 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
281 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
283 #define PCI_DEVICE_ID_VIA_VT630X 0x3044
284 #define PCI_REV_ID_VIA_VT6306 0x46
285 #define PCI_DEVICE_ID_VIA_VT6315 0x3403
286
287 #define QUIRK_CYCLE_TIMER 0x1
288 #define QUIRK_RESET_PACKET 0x2
289 #define QUIRK_BE_HEADERS 0x4
290 #define QUIRK_NO_1394A 0x8
291 #define QUIRK_NO_MSI 0x10
292 #define QUIRK_TI_SLLZ059 0x20
293 #define QUIRK_IR_WAKE 0x40
294
295 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
296 static const struct {
297 unsigned short vendor, device, revision, flags;
298 } ohci_quirks[] = {
299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
306 QUIRK_NO_MSI},
307
308 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
309 QUIRK_RESET_PACKET},
310
311 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
312 QUIRK_NO_MSI},
313
314 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_CYCLE_TIMER},
316
317 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_NO_MSI},
319
320 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
321 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
324 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
332 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
333 QUIRK_RESET_PACKET},
334
335 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
336 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
337
338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
339 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
340
341 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
342 QUIRK_NO_MSI},
343
344 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
345 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
346 };
347
348 /* This overrides anything that was found in ohci_quirks[]. */
349 static int param_quirks;
350 module_param_named(quirks, param_quirks, int, 0644);
351 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
352 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
353 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
354 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
355 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
356 ", disable MSI = " __stringify(QUIRK_NO_MSI)
357 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
358 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
359 ")");
360
361 #define OHCI_PARAM_DEBUG_AT_AR 1
362 #define OHCI_PARAM_DEBUG_SELFIDS 2
363 #define OHCI_PARAM_DEBUG_IRQS 4
364 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
365
366 static int param_debug;
367 module_param_named(debug, param_debug, int, 0644);
368 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
369 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
370 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
371 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
372 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
373 ", or a combination, or all = -1)");
374
375 static bool param_remote_dma;
376 module_param_named(remote_dma, param_remote_dma, bool, 0444);
377 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
378
379 static void log_irqs(struct fw_ohci *ohci, u32 evt)
380 {
381 if (likely(!(param_debug &
382 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
383 return;
384
385 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
386 !(evt & OHCI1394_busReset))
387 return;
388
389 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
390 evt & OHCI1394_selfIDComplete ? " selfID" : "",
391 evt & OHCI1394_RQPkt ? " AR_req" : "",
392 evt & OHCI1394_RSPkt ? " AR_resp" : "",
393 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
394 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
395 evt & OHCI1394_isochRx ? " IR" : "",
396 evt & OHCI1394_isochTx ? " IT" : "",
397 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
398 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
399 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
400 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
401 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
402 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
403 evt & OHCI1394_busReset ? " busReset" : "",
404 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
405 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
406 OHCI1394_respTxComplete | OHCI1394_isochRx |
407 OHCI1394_isochTx | OHCI1394_postedWriteErr |
408 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
409 OHCI1394_cycleInconsistent |
410 OHCI1394_regAccessFail | OHCI1394_busReset)
411 ? " ?" : "");
412 }
413
414 static const char *speed[] = {
415 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
416 };
417 static const char *power[] = {
418 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
419 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
420 };
421 static const char port[] = { '.', '-', 'p', 'c', };
422
423 static char _p(u32 *s, int shift)
424 {
425 return port[*s >> shift & 3];
426 }
427
428 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
429 {
430 u32 *s;
431
432 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
433 return;
434
435 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
436 self_id_count, generation, ohci->node_id);
437
438 for (s = ohci->self_id_buffer; self_id_count--; ++s)
439 if ((*s & 1 << 23) == 0)
440 ohci_notice(ohci,
441 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
442 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
443 speed[*s >> 14 & 3], *s >> 16 & 63,
444 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
445 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
446 else
447 ohci_notice(ohci,
448 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
449 *s, *s >> 24 & 63,
450 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
451 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
452 }
453
454 static const char *evts[] = {
455 [0x00] = "evt_no_status", [0x01] = "-reserved-",
456 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
457 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
458 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
459 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
460 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
461 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
462 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
463 [0x10] = "-reserved-", [0x11] = "ack_complete",
464 [0x12] = "ack_pending ", [0x13] = "-reserved-",
465 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
466 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
467 [0x18] = "-reserved-", [0x19] = "-reserved-",
468 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
469 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
470 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
471 [0x20] = "pending/cancelled",
472 };
473 static const char *tcodes[] = {
474 [0x0] = "QW req", [0x1] = "BW req",
475 [0x2] = "W resp", [0x3] = "-reserved-",
476 [0x4] = "QR req", [0x5] = "BR req",
477 [0x6] = "QR resp", [0x7] = "BR resp",
478 [0x8] = "cycle start", [0x9] = "Lk req",
479 [0xa] = "async stream packet", [0xb] = "Lk resp",
480 [0xc] = "-reserved-", [0xd] = "-reserved-",
481 [0xe] = "link internal", [0xf] = "-reserved-",
482 };
483
484 static void log_ar_at_event(struct fw_ohci *ohci,
485 char dir, int speed, u32 *header, int evt)
486 {
487 int tcode = header[0] >> 4 & 0xf;
488 char specific[12];
489
490 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
491 return;
492
493 if (unlikely(evt >= ARRAY_SIZE(evts)))
494 evt = 0x1f;
495
496 if (evt == OHCI1394_evt_bus_reset) {
497 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
498 dir, (header[2] >> 16) & 0xff);
499 return;
500 }
501
502 switch (tcode) {
503 case 0x0: case 0x6: case 0x8:
504 snprintf(specific, sizeof(specific), " = %08x",
505 be32_to_cpu((__force __be32)header[3]));
506 break;
507 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
508 snprintf(specific, sizeof(specific), " %x,%x",
509 header[3] >> 16, header[3] & 0xffff);
510 break;
511 default:
512 specific[0] = '\0';
513 }
514
515 switch (tcode) {
516 case 0xa:
517 ohci_notice(ohci, "A%c %s, %s\n",
518 dir, evts[evt], tcodes[tcode]);
519 break;
520 case 0xe:
521 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
522 dir, evts[evt], header[1], header[2]);
523 break;
524 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
525 ohci_notice(ohci,
526 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
527 dir, speed, header[0] >> 10 & 0x3f,
528 header[1] >> 16, header[0] >> 16, evts[evt],
529 tcodes[tcode], header[1] & 0xffff, header[2], specific);
530 break;
531 default:
532 ohci_notice(ohci,
533 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
534 dir, speed, header[0] >> 10 & 0x3f,
535 header[1] >> 16, header[0] >> 16, evts[evt],
536 tcodes[tcode], specific);
537 }
538 }
539
540 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
541 {
542 writel(data, ohci->registers + offset);
543 }
544
545 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
546 {
547 return readl(ohci->registers + offset);
548 }
549
550 static inline void flush_writes(const struct fw_ohci *ohci)
551 {
552 /* Do a dummy read to flush writes. */
553 reg_read(ohci, OHCI1394_Version);
554 }
555
556 /*
557 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
558 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
559 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
560 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
561 */
562 static int read_phy_reg(struct fw_ohci *ohci, int addr)
563 {
564 u32 val;
565 int i;
566
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
568 for (i = 0; i < 3 + 100; i++) {
569 val = reg_read(ohci, OHCI1394_PhyControl);
570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
573 if (val & OHCI1394_PhyControl_ReadDone)
574 return OHCI1394_PhyControl_ReadData(val);
575
576 /*
577 * Try a few times without waiting. Sleeping is necessary
578 * only when the link/PHY interface is busy.
579 */
580 if (i >= 3)
581 msleep(1);
582 }
583 ohci_err(ohci, "failed to read phy reg %d\n", addr);
584 dump_stack();
585
586 return -EBUSY;
587 }
588
589 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
590 {
591 int i;
592
593 reg_write(ohci, OHCI1394_PhyControl,
594 OHCI1394_PhyControl_Write(addr, val));
595 for (i = 0; i < 3 + 100; i++) {
596 val = reg_read(ohci, OHCI1394_PhyControl);
597 if (!~val)
598 return -ENODEV; /* Card was ejected. */
599
600 if (!(val & OHCI1394_PhyControl_WritePending))
601 return 0;
602
603 if (i >= 3)
604 msleep(1);
605 }
606 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
607 dump_stack();
608
609 return -EBUSY;
610 }
611
612 static int update_phy_reg(struct fw_ohci *ohci, int addr,
613 int clear_bits, int set_bits)
614 {
615 int ret = read_phy_reg(ohci, addr);
616 if (ret < 0)
617 return ret;
618
619 /*
620 * The interrupt status bits are cleared by writing a one bit.
621 * Avoid clearing them unless explicitly requested in set_bits.
622 */
623 if (addr == 5)
624 clear_bits |= PHY_INT_STATUS_BITS;
625
626 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
627 }
628
629 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
630 {
631 int ret;
632
633 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
634 if (ret < 0)
635 return ret;
636
637 return read_phy_reg(ohci, addr);
638 }
639
640 static int ohci_read_phy_reg(struct fw_card *card, int addr)
641 {
642 struct fw_ohci *ohci = fw_ohci(card);
643 int ret;
644
645 mutex_lock(&ohci->phy_reg_mutex);
646 ret = read_phy_reg(ohci, addr);
647 mutex_unlock(&ohci->phy_reg_mutex);
648
649 return ret;
650 }
651
652 static int ohci_update_phy_reg(struct fw_card *card, int addr,
653 int clear_bits, int set_bits)
654 {
655 struct fw_ohci *ohci = fw_ohci(card);
656 int ret;
657
658 mutex_lock(&ohci->phy_reg_mutex);
659 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
660 mutex_unlock(&ohci->phy_reg_mutex);
661
662 return ret;
663 }
664
665 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
666 {
667 return page_private(ctx->pages[i]);
668 }
669
670 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
671 {
672 struct descriptor *d;
673
674 d = &ctx->descriptors[index];
675 d->branch_address &= cpu_to_le32(~0xf);
676 d->res_count = cpu_to_le16(PAGE_SIZE);
677 d->transfer_status = 0;
678
679 wmb(); /* finish init of new descriptors before branch_address update */
680 d = &ctx->descriptors[ctx->last_buffer_index];
681 d->branch_address |= cpu_to_le32(1);
682
683 ctx->last_buffer_index = index;
684
685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
686 }
687
688 static void ar_context_release(struct ar_context *ctx)
689 {
690 unsigned int i;
691
692 vunmap(ctx->buffer);
693
694 for (i = 0; i < AR_BUFFERS; i++)
695 if (ctx->pages[i]) {
696 dma_unmap_page(ctx->ohci->card.device,
697 ar_buffer_bus(ctx, i),
698 PAGE_SIZE, DMA_FROM_DEVICE);
699 __free_page(ctx->pages[i]);
700 }
701 }
702
703 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
704 {
705 struct fw_ohci *ohci = ctx->ohci;
706
707 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
708 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
709 flush_writes(ohci);
710
711 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
712 }
713 /* FIXME: restart? */
714 }
715
716 static inline unsigned int ar_next_buffer_index(unsigned int index)
717 {
718 return (index + 1) % AR_BUFFERS;
719 }
720
721 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
722 {
723 return ar_next_buffer_index(ctx->last_buffer_index);
724 }
725
726 /*
727 * We search for the buffer that contains the last AR packet DMA data written
728 * by the controller.
729 */
730 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
731 unsigned int *buffer_offset)
732 {
733 unsigned int i, next_i, last = ctx->last_buffer_index;
734 __le16 res_count, next_res_count;
735
736 i = ar_first_buffer_index(ctx);
737 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
738
739 /* A buffer that is not yet completely filled must be the last one. */
740 while (i != last && res_count == 0) {
741
742 /* Peek at the next descriptor. */
743 next_i = ar_next_buffer_index(i);
744 rmb(); /* read descriptors in order */
745 next_res_count = ACCESS_ONCE(
746 ctx->descriptors[next_i].res_count);
747 /*
748 * If the next descriptor is still empty, we must stop at this
749 * descriptor.
750 */
751 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
752 /*
753 * The exception is when the DMA data for one packet is
754 * split over three buffers; in this case, the middle
755 * buffer's descriptor might be never updated by the
756 * controller and look still empty, and we have to peek
757 * at the third one.
758 */
759 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
760 next_i = ar_next_buffer_index(next_i);
761 rmb();
762 next_res_count = ACCESS_ONCE(
763 ctx->descriptors[next_i].res_count);
764 if (next_res_count != cpu_to_le16(PAGE_SIZE))
765 goto next_buffer_is_active;
766 }
767
768 break;
769 }
770
771 next_buffer_is_active:
772 i = next_i;
773 res_count = next_res_count;
774 }
775
776 rmb(); /* read res_count before the DMA data */
777
778 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
779 if (*buffer_offset > PAGE_SIZE) {
780 *buffer_offset = 0;
781 ar_context_abort(ctx, "corrupted descriptor");
782 }
783
784 return i;
785 }
786
787 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
788 unsigned int end_buffer_index,
789 unsigned int end_buffer_offset)
790 {
791 unsigned int i;
792
793 i = ar_first_buffer_index(ctx);
794 while (i != end_buffer_index) {
795 dma_sync_single_for_cpu(ctx->ohci->card.device,
796 ar_buffer_bus(ctx, i),
797 PAGE_SIZE, DMA_FROM_DEVICE);
798 i = ar_next_buffer_index(i);
799 }
800 if (end_buffer_offset > 0)
801 dma_sync_single_for_cpu(ctx->ohci->card.device,
802 ar_buffer_bus(ctx, i),
803 end_buffer_offset, DMA_FROM_DEVICE);
804 }
805
806 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
807 #define cond_le32_to_cpu(v) \
808 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
809 #else
810 #define cond_le32_to_cpu(v) le32_to_cpu(v)
811 #endif
812
813 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
814 {
815 struct fw_ohci *ohci = ctx->ohci;
816 struct fw_packet p;
817 u32 status, length, tcode;
818 int evt;
819
820 p.header[0] = cond_le32_to_cpu(buffer[0]);
821 p.header[1] = cond_le32_to_cpu(buffer[1]);
822 p.header[2] = cond_le32_to_cpu(buffer[2]);
823
824 tcode = (p.header[0] >> 4) & 0x0f;
825 switch (tcode) {
826 case TCODE_WRITE_QUADLET_REQUEST:
827 case TCODE_READ_QUADLET_RESPONSE:
828 p.header[3] = (__force __u32) buffer[3];
829 p.header_length = 16;
830 p.payload_length = 0;
831 break;
832
833 case TCODE_READ_BLOCK_REQUEST :
834 p.header[3] = cond_le32_to_cpu(buffer[3]);
835 p.header_length = 16;
836 p.payload_length = 0;
837 break;
838
839 case TCODE_WRITE_BLOCK_REQUEST:
840 case TCODE_READ_BLOCK_RESPONSE:
841 case TCODE_LOCK_REQUEST:
842 case TCODE_LOCK_RESPONSE:
843 p.header[3] = cond_le32_to_cpu(buffer[3]);
844 p.header_length = 16;
845 p.payload_length = p.header[3] >> 16;
846 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
847 ar_context_abort(ctx, "invalid packet length");
848 return NULL;
849 }
850 break;
851
852 case TCODE_WRITE_RESPONSE:
853 case TCODE_READ_QUADLET_REQUEST:
854 case OHCI_TCODE_PHY_PACKET:
855 p.header_length = 12;
856 p.payload_length = 0;
857 break;
858
859 default:
860 ar_context_abort(ctx, "invalid tcode");
861 return NULL;
862 }
863
864 p.payload = (void *) buffer + p.header_length;
865
866 /* FIXME: What to do about evt_* errors? */
867 length = (p.header_length + p.payload_length + 3) / 4;
868 status = cond_le32_to_cpu(buffer[length]);
869 evt = (status >> 16) & 0x1f;
870
871 p.ack = evt - 16;
872 p.speed = (status >> 21) & 0x7;
873 p.timestamp = status & 0xffff;
874 p.generation = ohci->request_generation;
875
876 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
877
878 /*
879 * Several controllers, notably from NEC and VIA, forget to
880 * write ack_complete status at PHY packet reception.
881 */
882 if (evt == OHCI1394_evt_no_status &&
883 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
884 p.ack = ACK_COMPLETE;
885
886 /*
887 * The OHCI bus reset handler synthesizes a PHY packet with
888 * the new generation number when a bus reset happens (see
889 * section 8.4.2.3). This helps us determine when a request
890 * was received and make sure we send the response in the same
891 * generation. We only need this for requests; for responses
892 * we use the unique tlabel for finding the matching
893 * request.
894 *
895 * Alas some chips sometimes emit bus reset packets with a
896 * wrong generation. We set the correct generation for these
897 * at a slightly incorrect time (in bus_reset_work).
898 */
899 if (evt == OHCI1394_evt_bus_reset) {
900 if (!(ohci->quirks & QUIRK_RESET_PACKET))
901 ohci->request_generation = (p.header[2] >> 16) & 0xff;
902 } else if (ctx == &ohci->ar_request_ctx) {
903 fw_core_handle_request(&ohci->card, &p);
904 } else {
905 fw_core_handle_response(&ohci->card, &p);
906 }
907
908 return buffer + length + 1;
909 }
910
911 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
912 {
913 void *next;
914
915 while (p < end) {
916 next = handle_ar_packet(ctx, p);
917 if (!next)
918 return p;
919 p = next;
920 }
921
922 return p;
923 }
924
925 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
926 {
927 unsigned int i;
928
929 i = ar_first_buffer_index(ctx);
930 while (i != end_buffer) {
931 dma_sync_single_for_device(ctx->ohci->card.device,
932 ar_buffer_bus(ctx, i),
933 PAGE_SIZE, DMA_FROM_DEVICE);
934 ar_context_link_page(ctx, i);
935 i = ar_next_buffer_index(i);
936 }
937 }
938
939 static void ar_context_tasklet(unsigned long data)
940 {
941 struct ar_context *ctx = (struct ar_context *)data;
942 unsigned int end_buffer_index, end_buffer_offset;
943 void *p, *end;
944
945 p = ctx->pointer;
946 if (!p)
947 return;
948
949 end_buffer_index = ar_search_last_active_buffer(ctx,
950 &end_buffer_offset);
951 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
952 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
953
954 if (end_buffer_index < ar_first_buffer_index(ctx)) {
955 /*
956 * The filled part of the overall buffer wraps around; handle
957 * all packets up to the buffer end here. If the last packet
958 * wraps around, its tail will be visible after the buffer end
959 * because the buffer start pages are mapped there again.
960 */
961 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
962 p = handle_ar_packets(ctx, p, buffer_end);
963 if (p < buffer_end)
964 goto error;
965 /* adjust p to point back into the actual buffer */
966 p -= AR_BUFFERS * PAGE_SIZE;
967 }
968
969 p = handle_ar_packets(ctx, p, end);
970 if (p != end) {
971 if (p > end)
972 ar_context_abort(ctx, "inconsistent descriptor");
973 goto error;
974 }
975
976 ctx->pointer = p;
977 ar_recycle_buffers(ctx, end_buffer_index);
978
979 return;
980
981 error:
982 ctx->pointer = NULL;
983 }
984
985 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
986 unsigned int descriptors_offset, u32 regs)
987 {
988 unsigned int i;
989 dma_addr_t dma_addr;
990 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
991 struct descriptor *d;
992
993 ctx->regs = regs;
994 ctx->ohci = ohci;
995 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
996
997 for (i = 0; i < AR_BUFFERS; i++) {
998 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
999 if (!ctx->pages[i])
1000 goto out_of_memory;
1001 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1002 0, PAGE_SIZE, DMA_FROM_DEVICE);
1003 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1004 __free_page(ctx->pages[i]);
1005 ctx->pages[i] = NULL;
1006 goto out_of_memory;
1007 }
1008 set_page_private(ctx->pages[i], dma_addr);
1009 }
1010
1011 for (i = 0; i < AR_BUFFERS; i++)
1012 pages[i] = ctx->pages[i];
1013 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1014 pages[AR_BUFFERS + i] = ctx->pages[i];
1015 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1016 if (!ctx->buffer)
1017 goto out_of_memory;
1018
1019 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1020 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1021
1022 for (i = 0; i < AR_BUFFERS; i++) {
1023 d = &ctx->descriptors[i];
1024 d->req_count = cpu_to_le16(PAGE_SIZE);
1025 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1026 DESCRIPTOR_STATUS |
1027 DESCRIPTOR_BRANCH_ALWAYS);
1028 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1029 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1030 ar_next_buffer_index(i) * sizeof(struct descriptor));
1031 }
1032
1033 return 0;
1034
1035 out_of_memory:
1036 ar_context_release(ctx);
1037
1038 return -ENOMEM;
1039 }
1040
1041 static void ar_context_run(struct ar_context *ctx)
1042 {
1043 unsigned int i;
1044
1045 for (i = 0; i < AR_BUFFERS; i++)
1046 ar_context_link_page(ctx, i);
1047
1048 ctx->pointer = ctx->buffer;
1049
1050 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1051 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1052 }
1053
1054 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1055 {
1056 __le16 branch;
1057
1058 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1059
1060 /* figure out which descriptor the branch address goes in */
1061 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1062 return d;
1063 else
1064 return d + z - 1;
1065 }
1066
1067 static void context_tasklet(unsigned long data)
1068 {
1069 struct context *ctx = (struct context *) data;
1070 struct descriptor *d, *last;
1071 u32 address;
1072 int z;
1073 struct descriptor_buffer *desc;
1074
1075 desc = list_entry(ctx->buffer_list.next,
1076 struct descriptor_buffer, list);
1077 last = ctx->last;
1078 while (last->branch_address != 0) {
1079 struct descriptor_buffer *old_desc = desc;
1080 address = le32_to_cpu(last->branch_address);
1081 z = address & 0xf;
1082 address &= ~0xf;
1083 ctx->current_bus = address;
1084
1085 /* If the branch address points to a buffer outside of the
1086 * current buffer, advance to the next buffer. */
1087 if (address < desc->buffer_bus ||
1088 address >= desc->buffer_bus + desc->used)
1089 desc = list_entry(desc->list.next,
1090 struct descriptor_buffer, list);
1091 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1092 last = find_branch_descriptor(d, z);
1093
1094 if (!ctx->callback(ctx, d, last))
1095 break;
1096
1097 if (old_desc != desc) {
1098 /* If we've advanced to the next buffer, move the
1099 * previous buffer to the free list. */
1100 unsigned long flags;
1101 old_desc->used = 0;
1102 spin_lock_irqsave(&ctx->ohci->lock, flags);
1103 list_move_tail(&old_desc->list, &ctx->buffer_list);
1104 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1105 }
1106 ctx->last = last;
1107 }
1108 }
1109
1110 /*
1111 * Allocate a new buffer and add it to the list of free buffers for this
1112 * context. Must be called with ohci->lock held.
1113 */
1114 static int context_add_buffer(struct context *ctx)
1115 {
1116 struct descriptor_buffer *desc;
1117 dma_addr_t uninitialized_var(bus_addr);
1118 int offset;
1119
1120 /*
1121 * 16MB of descriptors should be far more than enough for any DMA
1122 * program. This will catch run-away userspace or DoS attacks.
1123 */
1124 if (ctx->total_allocation >= 16*1024*1024)
1125 return -ENOMEM;
1126
1127 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1128 &bus_addr, GFP_ATOMIC);
1129 if (!desc)
1130 return -ENOMEM;
1131
1132 offset = (void *)&desc->buffer - (void *)desc;
1133 /*
1134 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
1135 * for descriptors, even 0x10-byte ones. This can cause page faults when
1136 * an IOMMU is in use and the oversized read crosses a page boundary.
1137 * Work around this by always leaving at least 0x10 bytes of padding.
1138 */
1139 desc->buffer_size = PAGE_SIZE - offset - 0x10;
1140 desc->buffer_bus = bus_addr + offset;
1141 desc->used = 0;
1142
1143 list_add_tail(&desc->list, &ctx->buffer_list);
1144 ctx->total_allocation += PAGE_SIZE;
1145
1146 return 0;
1147 }
1148
1149 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1150 u32 regs, descriptor_callback_t callback)
1151 {
1152 ctx->ohci = ohci;
1153 ctx->regs = regs;
1154 ctx->total_allocation = 0;
1155
1156 INIT_LIST_HEAD(&ctx->buffer_list);
1157 if (context_add_buffer(ctx) < 0)
1158 return -ENOMEM;
1159
1160 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1161 struct descriptor_buffer, list);
1162
1163 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1164 ctx->callback = callback;
1165
1166 /*
1167 * We put a dummy descriptor in the buffer that has a NULL
1168 * branch address and looks like it's been sent. That way we
1169 * have a descriptor to append DMA programs to.
1170 */
1171 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1172 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1173 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1174 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1175 ctx->last = ctx->buffer_tail->buffer;
1176 ctx->prev = ctx->buffer_tail->buffer;
1177 ctx->prev_z = 1;
1178
1179 return 0;
1180 }
1181
1182 static void context_release(struct context *ctx)
1183 {
1184 struct fw_card *card = &ctx->ohci->card;
1185 struct descriptor_buffer *desc, *tmp;
1186
1187 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1188 dma_free_coherent(card->device, PAGE_SIZE, desc,
1189 desc->buffer_bus -
1190 ((void *)&desc->buffer - (void *)desc));
1191 }
1192
1193 /* Must be called with ohci->lock held */
1194 static struct descriptor *context_get_descriptors(struct context *ctx,
1195 int z, dma_addr_t *d_bus)
1196 {
1197 struct descriptor *d = NULL;
1198 struct descriptor_buffer *desc = ctx->buffer_tail;
1199
1200 if (z * sizeof(*d) > desc->buffer_size)
1201 return NULL;
1202
1203 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1204 /* No room for the descriptor in this buffer, so advance to the
1205 * next one. */
1206
1207 if (desc->list.next == &ctx->buffer_list) {
1208 /* If there is no free buffer next in the list,
1209 * allocate one. */
1210 if (context_add_buffer(ctx) < 0)
1211 return NULL;
1212 }
1213 desc = list_entry(desc->list.next,
1214 struct descriptor_buffer, list);
1215 ctx->buffer_tail = desc;
1216 }
1217
1218 d = desc->buffer + desc->used / sizeof(*d);
1219 memset(d, 0, z * sizeof(*d));
1220 *d_bus = desc->buffer_bus + desc->used;
1221
1222 return d;
1223 }
1224
1225 static void context_run(struct context *ctx, u32 extra)
1226 {
1227 struct fw_ohci *ohci = ctx->ohci;
1228
1229 reg_write(ohci, COMMAND_PTR(ctx->regs),
1230 le32_to_cpu(ctx->last->branch_address));
1231 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1232 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1233 ctx->running = true;
1234 flush_writes(ohci);
1235 }
1236
1237 static void context_append(struct context *ctx,
1238 struct descriptor *d, int z, int extra)
1239 {
1240 dma_addr_t d_bus;
1241 struct descriptor_buffer *desc = ctx->buffer_tail;
1242 struct descriptor *d_branch;
1243
1244 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1245
1246 desc->used += (z + extra) * sizeof(*d);
1247
1248 wmb(); /* finish init of new descriptors before branch_address update */
1249
1250 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1251 d_branch->branch_address = cpu_to_le32(d_bus | z);
1252
1253 /*
1254 * VT6306 incorrectly checks only the single descriptor at the
1255 * CommandPtr when the wake bit is written, so if it's a
1256 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1257 * the branch address in the first descriptor.
1258 *
1259 * Not doing this for transmit contexts since not sure how it interacts
1260 * with skip addresses.
1261 */
1262 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1263 d_branch != ctx->prev &&
1264 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1265 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1266 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1267 }
1268
1269 ctx->prev = d;
1270 ctx->prev_z = z;
1271 }
1272
1273 static void context_stop(struct context *ctx)
1274 {
1275 struct fw_ohci *ohci = ctx->ohci;
1276 u32 reg;
1277 int i;
1278
1279 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1280 ctx->running = false;
1281
1282 for (i = 0; i < 1000; i++) {
1283 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1284 if ((reg & CONTEXT_ACTIVE) == 0)
1285 return;
1286
1287 if (i)
1288 udelay(10);
1289 }
1290 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1291 }
1292
1293 struct driver_data {
1294 u8 inline_data[8];
1295 struct fw_packet *packet;
1296 };
1297
1298 /*
1299 * This function apppends a packet to the DMA queue for transmission.
1300 * Must always be called with the ochi->lock held to ensure proper
1301 * generation handling and locking around packet queue manipulation.
1302 */
1303 static int at_context_queue_packet(struct context *ctx,
1304 struct fw_packet *packet)
1305 {
1306 struct fw_ohci *ohci = ctx->ohci;
1307 dma_addr_t d_bus, uninitialized_var(payload_bus);
1308 struct driver_data *driver_data;
1309 struct descriptor *d, *last;
1310 __le32 *header;
1311 int z, tcode;
1312
1313 d = context_get_descriptors(ctx, 4, &d_bus);
1314 if (d == NULL) {
1315 packet->ack = RCODE_SEND_ERROR;
1316 return -1;
1317 }
1318
1319 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1320 d[0].res_count = cpu_to_le16(packet->timestamp);
1321
1322 /*
1323 * The DMA format for asynchronous link packets is different
1324 * from the IEEE1394 layout, so shift the fields around
1325 * accordingly.
1326 */
1327
1328 tcode = (packet->header[0] >> 4) & 0x0f;
1329 header = (__le32 *) &d[1];
1330 switch (tcode) {
1331 case TCODE_WRITE_QUADLET_REQUEST:
1332 case TCODE_WRITE_BLOCK_REQUEST:
1333 case TCODE_WRITE_RESPONSE:
1334 case TCODE_READ_QUADLET_REQUEST:
1335 case TCODE_READ_BLOCK_REQUEST:
1336 case TCODE_READ_QUADLET_RESPONSE:
1337 case TCODE_READ_BLOCK_RESPONSE:
1338 case TCODE_LOCK_REQUEST:
1339 case TCODE_LOCK_RESPONSE:
1340 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1341 (packet->speed << 16));
1342 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1343 (packet->header[0] & 0xffff0000));
1344 header[2] = cpu_to_le32(packet->header[2]);
1345
1346 if (TCODE_IS_BLOCK_PACKET(tcode))
1347 header[3] = cpu_to_le32(packet->header[3]);
1348 else
1349 header[3] = (__force __le32) packet->header[3];
1350
1351 d[0].req_count = cpu_to_le16(packet->header_length);
1352 break;
1353
1354 case TCODE_LINK_INTERNAL:
1355 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1356 (packet->speed << 16));
1357 header[1] = cpu_to_le32(packet->header[1]);
1358 header[2] = cpu_to_le32(packet->header[2]);
1359 d[0].req_count = cpu_to_le16(12);
1360
1361 if (is_ping_packet(&packet->header[1]))
1362 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1363 break;
1364
1365 case TCODE_STREAM_DATA:
1366 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1367 (packet->speed << 16));
1368 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1369 d[0].req_count = cpu_to_le16(8);
1370 break;
1371
1372 default:
1373 /* BUG(); */
1374 packet->ack = RCODE_SEND_ERROR;
1375 return -1;
1376 }
1377
1378 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1379 driver_data = (struct driver_data *) &d[3];
1380 driver_data->packet = packet;
1381 packet->driver_data = driver_data;
1382
1383 if (packet->payload_length > 0) {
1384 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1385 payload_bus = dma_map_single(ohci->card.device,
1386 packet->payload,
1387 packet->payload_length,
1388 DMA_TO_DEVICE);
1389 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1390 packet->ack = RCODE_SEND_ERROR;
1391 return -1;
1392 }
1393 packet->payload_bus = payload_bus;
1394 packet->payload_mapped = true;
1395 } else {
1396 memcpy(driver_data->inline_data, packet->payload,
1397 packet->payload_length);
1398 payload_bus = d_bus + 3 * sizeof(*d);
1399 }
1400
1401 d[2].req_count = cpu_to_le16(packet->payload_length);
1402 d[2].data_address = cpu_to_le32(payload_bus);
1403 last = &d[2];
1404 z = 3;
1405 } else {
1406 last = &d[0];
1407 z = 2;
1408 }
1409
1410 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1411 DESCRIPTOR_IRQ_ALWAYS |
1412 DESCRIPTOR_BRANCH_ALWAYS);
1413
1414 /* FIXME: Document how the locking works. */
1415 if (ohci->generation != packet->generation) {
1416 if (packet->payload_mapped)
1417 dma_unmap_single(ohci->card.device, payload_bus,
1418 packet->payload_length, DMA_TO_DEVICE);
1419 packet->ack = RCODE_GENERATION;
1420 return -1;
1421 }
1422
1423 context_append(ctx, d, z, 4 - z);
1424
1425 if (ctx->running)
1426 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1427 else
1428 context_run(ctx, 0);
1429
1430 return 0;
1431 }
1432
1433 static void at_context_flush(struct context *ctx)
1434 {
1435 tasklet_disable(&ctx->tasklet);
1436
1437 ctx->flushing = true;
1438 context_tasklet((unsigned long)ctx);
1439 ctx->flushing = false;
1440
1441 tasklet_enable(&ctx->tasklet);
1442 }
1443
1444 static int handle_at_packet(struct context *context,
1445 struct descriptor *d,
1446 struct descriptor *last)
1447 {
1448 struct driver_data *driver_data;
1449 struct fw_packet *packet;
1450 struct fw_ohci *ohci = context->ohci;
1451 int evt;
1452
1453 if (last->transfer_status == 0 && !context->flushing)
1454 /* This descriptor isn't done yet, stop iteration. */
1455 return 0;
1456
1457 driver_data = (struct driver_data *) &d[3];
1458 packet = driver_data->packet;
1459 if (packet == NULL)
1460 /* This packet was cancelled, just continue. */
1461 return 1;
1462
1463 if (packet->payload_mapped)
1464 dma_unmap_single(ohci->card.device, packet->payload_bus,
1465 packet->payload_length, DMA_TO_DEVICE);
1466
1467 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1468 packet->timestamp = le16_to_cpu(last->res_count);
1469
1470 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1471
1472 switch (evt) {
1473 case OHCI1394_evt_timeout:
1474 /* Async response transmit timed out. */
1475 packet->ack = RCODE_CANCELLED;
1476 break;
1477
1478 case OHCI1394_evt_flushed:
1479 /*
1480 * The packet was flushed should give same error as
1481 * when we try to use a stale generation count.
1482 */
1483 packet->ack = RCODE_GENERATION;
1484 break;
1485
1486 case OHCI1394_evt_missing_ack:
1487 if (context->flushing)
1488 packet->ack = RCODE_GENERATION;
1489 else {
1490 /*
1491 * Using a valid (current) generation count, but the
1492 * node is not on the bus or not sending acks.
1493 */
1494 packet->ack = RCODE_NO_ACK;
1495 }
1496 break;
1497
1498 case ACK_COMPLETE + 0x10:
1499 case ACK_PENDING + 0x10:
1500 case ACK_BUSY_X + 0x10:
1501 case ACK_BUSY_A + 0x10:
1502 case ACK_BUSY_B + 0x10:
1503 case ACK_DATA_ERROR + 0x10:
1504 case ACK_TYPE_ERROR + 0x10:
1505 packet->ack = evt - 0x10;
1506 break;
1507
1508 case OHCI1394_evt_no_status:
1509 if (context->flushing) {
1510 packet->ack = RCODE_GENERATION;
1511 break;
1512 }
1513 /* fall through */
1514
1515 default:
1516 packet->ack = RCODE_SEND_ERROR;
1517 break;
1518 }
1519
1520 packet->callback(packet, &ohci->card, packet->ack);
1521
1522 return 1;
1523 }
1524
1525 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1526 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1527 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1528 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1529 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1530
1531 static void handle_local_rom(struct fw_ohci *ohci,
1532 struct fw_packet *packet, u32 csr)
1533 {
1534 struct fw_packet response;
1535 int tcode, length, i;
1536
1537 tcode = HEADER_GET_TCODE(packet->header[0]);
1538 if (TCODE_IS_BLOCK_PACKET(tcode))
1539 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1540 else
1541 length = 4;
1542
1543 i = csr - CSR_CONFIG_ROM;
1544 if (i + length > CONFIG_ROM_SIZE) {
1545 fw_fill_response(&response, packet->header,
1546 RCODE_ADDRESS_ERROR, NULL, 0);
1547 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1548 fw_fill_response(&response, packet->header,
1549 RCODE_TYPE_ERROR, NULL, 0);
1550 } else {
1551 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1552 (void *) ohci->config_rom + i, length);
1553 }
1554
1555 fw_core_handle_response(&ohci->card, &response);
1556 }
1557
1558 static void handle_local_lock(struct fw_ohci *ohci,
1559 struct fw_packet *packet, u32 csr)
1560 {
1561 struct fw_packet response;
1562 int tcode, length, ext_tcode, sel, try;
1563 __be32 *payload, lock_old;
1564 u32 lock_arg, lock_data;
1565
1566 tcode = HEADER_GET_TCODE(packet->header[0]);
1567 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1568 payload = packet->payload;
1569 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1570
1571 if (tcode == TCODE_LOCK_REQUEST &&
1572 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1573 lock_arg = be32_to_cpu(payload[0]);
1574 lock_data = be32_to_cpu(payload[1]);
1575 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1576 lock_arg = 0;
1577 lock_data = 0;
1578 } else {
1579 fw_fill_response(&response, packet->header,
1580 RCODE_TYPE_ERROR, NULL, 0);
1581 goto out;
1582 }
1583
1584 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1585 reg_write(ohci, OHCI1394_CSRData, lock_data);
1586 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1587 reg_write(ohci, OHCI1394_CSRControl, sel);
1588
1589 for (try = 0; try < 20; try++)
1590 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1591 lock_old = cpu_to_be32(reg_read(ohci,
1592 OHCI1394_CSRData));
1593 fw_fill_response(&response, packet->header,
1594 RCODE_COMPLETE,
1595 &lock_old, sizeof(lock_old));
1596 goto out;
1597 }
1598
1599 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1600 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1601
1602 out:
1603 fw_core_handle_response(&ohci->card, &response);
1604 }
1605
1606 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1607 {
1608 u64 offset, csr;
1609
1610 if (ctx == &ctx->ohci->at_request_ctx) {
1611 packet->ack = ACK_PENDING;
1612 packet->callback(packet, &ctx->ohci->card, packet->ack);
1613 }
1614
1615 offset =
1616 ((unsigned long long)
1617 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1618 packet->header[2];
1619 csr = offset - CSR_REGISTER_BASE;
1620
1621 /* Handle config rom reads. */
1622 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1623 handle_local_rom(ctx->ohci, packet, csr);
1624 else switch (csr) {
1625 case CSR_BUS_MANAGER_ID:
1626 case CSR_BANDWIDTH_AVAILABLE:
1627 case CSR_CHANNELS_AVAILABLE_HI:
1628 case CSR_CHANNELS_AVAILABLE_LO:
1629 handle_local_lock(ctx->ohci, packet, csr);
1630 break;
1631 default:
1632 if (ctx == &ctx->ohci->at_request_ctx)
1633 fw_core_handle_request(&ctx->ohci->card, packet);
1634 else
1635 fw_core_handle_response(&ctx->ohci->card, packet);
1636 break;
1637 }
1638
1639 if (ctx == &ctx->ohci->at_response_ctx) {
1640 packet->ack = ACK_COMPLETE;
1641 packet->callback(packet, &ctx->ohci->card, packet->ack);
1642 }
1643 }
1644
1645 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1646 {
1647 unsigned long flags;
1648 int ret;
1649
1650 spin_lock_irqsave(&ctx->ohci->lock, flags);
1651
1652 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1653 ctx->ohci->generation == packet->generation) {
1654 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1655 handle_local_request(ctx, packet);
1656 return;
1657 }
1658
1659 ret = at_context_queue_packet(ctx, packet);
1660 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1661
1662 if (ret < 0)
1663 packet->callback(packet, &ctx->ohci->card, packet->ack);
1664
1665 }
1666
1667 static void detect_dead_context(struct fw_ohci *ohci,
1668 const char *name, unsigned int regs)
1669 {
1670 u32 ctl;
1671
1672 ctl = reg_read(ohci, CONTROL_SET(regs));
1673 if (ctl & CONTEXT_DEAD)
1674 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1675 name, evts[ctl & 0x1f]);
1676 }
1677
1678 static void handle_dead_contexts(struct fw_ohci *ohci)
1679 {
1680 unsigned int i;
1681 char name[8];
1682
1683 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1684 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1685 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1686 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1687 for (i = 0; i < 32; ++i) {
1688 if (!(ohci->it_context_support & (1 << i)))
1689 continue;
1690 sprintf(name, "IT%u", i);
1691 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1692 }
1693 for (i = 0; i < 32; ++i) {
1694 if (!(ohci->ir_context_support & (1 << i)))
1695 continue;
1696 sprintf(name, "IR%u", i);
1697 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1698 }
1699 /* TODO: maybe try to flush and restart the dead contexts */
1700 }
1701
1702 static u32 cycle_timer_ticks(u32 cycle_timer)
1703 {
1704 u32 ticks;
1705
1706 ticks = cycle_timer & 0xfff;
1707 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1708 ticks += (3072 * 8000) * (cycle_timer >> 25);
1709
1710 return ticks;
1711 }
1712
1713 /*
1714 * Some controllers exhibit one or more of the following bugs when updating the
1715 * iso cycle timer register:
1716 * - When the lowest six bits are wrapping around to zero, a read that happens
1717 * at the same time will return garbage in the lowest ten bits.
1718 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1719 * not incremented for about 60 ns.
1720 * - Occasionally, the entire register reads zero.
1721 *
1722 * To catch these, we read the register three times and ensure that the
1723 * difference between each two consecutive reads is approximately the same, i.e.
1724 * less than twice the other. Furthermore, any negative difference indicates an
1725 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1726 * execute, so we have enough precision to compute the ratio of the differences.)
1727 */
1728 static u32 get_cycle_time(struct fw_ohci *ohci)
1729 {
1730 u32 c0, c1, c2;
1731 u32 t0, t1, t2;
1732 s32 diff01, diff12;
1733 int i;
1734
1735 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1736
1737 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1738 i = 0;
1739 c1 = c2;
1740 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1741 do {
1742 c0 = c1;
1743 c1 = c2;
1744 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1745 t0 = cycle_timer_ticks(c0);
1746 t1 = cycle_timer_ticks(c1);
1747 t2 = cycle_timer_ticks(c2);
1748 diff01 = t1 - t0;
1749 diff12 = t2 - t1;
1750 } while ((diff01 <= 0 || diff12 <= 0 ||
1751 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1752 && i++ < 20);
1753 }
1754
1755 return c2;
1756 }
1757
1758 /*
1759 * This function has to be called at least every 64 seconds. The bus_time
1760 * field stores not only the upper 25 bits of the BUS_TIME register but also
1761 * the most significant bit of the cycle timer in bit 6 so that we can detect
1762 * changes in this bit.
1763 */
1764 static u32 update_bus_time(struct fw_ohci *ohci)
1765 {
1766 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1767
1768 if (unlikely(!ohci->bus_time_running)) {
1769 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1770 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1771 (cycle_time_seconds & 0x40);
1772 ohci->bus_time_running = true;
1773 }
1774
1775 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1776 ohci->bus_time += 0x40;
1777
1778 return ohci->bus_time | cycle_time_seconds;
1779 }
1780
1781 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1782 {
1783 int reg;
1784
1785 mutex_lock(&ohci->phy_reg_mutex);
1786 reg = write_phy_reg(ohci, 7, port_index);
1787 if (reg >= 0)
1788 reg = read_phy_reg(ohci, 8);
1789 mutex_unlock(&ohci->phy_reg_mutex);
1790 if (reg < 0)
1791 return reg;
1792
1793 switch (reg & 0x0f) {
1794 case 0x06:
1795 return 2; /* is child node (connected to parent node) */
1796 case 0x0e:
1797 return 3; /* is parent node (connected to child node) */
1798 }
1799 return 1; /* not connected */
1800 }
1801
1802 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1803 int self_id_count)
1804 {
1805 int i;
1806 u32 entry;
1807
1808 for (i = 0; i < self_id_count; i++) {
1809 entry = ohci->self_id_buffer[i];
1810 if ((self_id & 0xff000000) == (entry & 0xff000000))
1811 return -1;
1812 if ((self_id & 0xff000000) < (entry & 0xff000000))
1813 return i;
1814 }
1815 return i;
1816 }
1817
1818 static int initiated_reset(struct fw_ohci *ohci)
1819 {
1820 int reg;
1821 int ret = 0;
1822
1823 mutex_lock(&ohci->phy_reg_mutex);
1824 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1825 if (reg >= 0) {
1826 reg = read_phy_reg(ohci, 8);
1827 reg |= 0x40;
1828 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1829 if (reg >= 0) {
1830 reg = read_phy_reg(ohci, 12); /* read register 12 */
1831 if (reg >= 0) {
1832 if ((reg & 0x08) == 0x08) {
1833 /* bit 3 indicates "initiated reset" */
1834 ret = 0x2;
1835 }
1836 }
1837 }
1838 }
1839 mutex_unlock(&ohci->phy_reg_mutex);
1840 return ret;
1841 }
1842
1843 /*
1844 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1845 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1846 * Construct the selfID from phy register contents.
1847 */
1848 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1849 {
1850 int reg, i, pos, status;
1851 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1852 u32 self_id = 0x8040c800;
1853
1854 reg = reg_read(ohci, OHCI1394_NodeID);
1855 if (!(reg & OHCI1394_NodeID_idValid)) {
1856 ohci_notice(ohci,
1857 "node ID not valid, new bus reset in progress\n");
1858 return -EBUSY;
1859 }
1860 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1861
1862 reg = ohci_read_phy_reg(&ohci->card, 4);
1863 if (reg < 0)
1864 return reg;
1865 self_id |= ((reg & 0x07) << 8); /* power class */
1866
1867 reg = ohci_read_phy_reg(&ohci->card, 1);
1868 if (reg < 0)
1869 return reg;
1870 self_id |= ((reg & 0x3f) << 16); /* gap count */
1871
1872 for (i = 0; i < 3; i++) {
1873 status = get_status_for_port(ohci, i);
1874 if (status < 0)
1875 return status;
1876 self_id |= ((status & 0x3) << (6 - (i * 2)));
1877 }
1878
1879 self_id |= initiated_reset(ohci);
1880
1881 pos = get_self_id_pos(ohci, self_id, self_id_count);
1882 if (pos >= 0) {
1883 memmove(&(ohci->self_id_buffer[pos+1]),
1884 &(ohci->self_id_buffer[pos]),
1885 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1886 ohci->self_id_buffer[pos] = self_id;
1887 self_id_count++;
1888 }
1889 return self_id_count;
1890 }
1891
1892 static void bus_reset_work(struct work_struct *work)
1893 {
1894 struct fw_ohci *ohci =
1895 container_of(work, struct fw_ohci, bus_reset_work);
1896 int self_id_count, generation, new_generation, i, j;
1897 u32 reg;
1898 void *free_rom = NULL;
1899 dma_addr_t free_rom_bus = 0;
1900 bool is_new_root;
1901
1902 reg = reg_read(ohci, OHCI1394_NodeID);
1903 if (!(reg & OHCI1394_NodeID_idValid)) {
1904 ohci_notice(ohci,
1905 "node ID not valid, new bus reset in progress\n");
1906 return;
1907 }
1908 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1909 ohci_notice(ohci, "malconfigured bus\n");
1910 return;
1911 }
1912 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1913 OHCI1394_NodeID_nodeNumber);
1914
1915 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1916 if (!(ohci->is_root && is_new_root))
1917 reg_write(ohci, OHCI1394_LinkControlSet,
1918 OHCI1394_LinkControl_cycleMaster);
1919 ohci->is_root = is_new_root;
1920
1921 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1922 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1923 ohci_notice(ohci, "self ID receive error\n");
1924 return;
1925 }
1926 /*
1927 * The count in the SelfIDCount register is the number of
1928 * bytes in the self ID receive buffer. Since we also receive
1929 * the inverted quadlets and a header quadlet, we shift one
1930 * bit extra to get the actual number of self IDs.
1931 */
1932 self_id_count = (reg >> 3) & 0xff;
1933
1934 if (self_id_count > 252) {
1935 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1936 return;
1937 }
1938
1939 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1940 rmb();
1941
1942 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1943 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1944 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1945
1946 if (id != ~id2) {
1947 /*
1948 * If the invalid data looks like a cycle start packet,
1949 * it's likely to be the result of the cycle master
1950 * having a wrong gap count. In this case, the self IDs
1951 * so far are valid and should be processed so that the
1952 * bus manager can then correct the gap count.
1953 */
1954 if (id == 0xffff008f) {
1955 ohci_notice(ohci, "ignoring spurious self IDs\n");
1956 self_id_count = j;
1957 break;
1958 }
1959
1960 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1961 j, self_id_count, id, id2);
1962 return;
1963 }
1964 ohci->self_id_buffer[j] = id;
1965 }
1966
1967 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1968 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1969 if (self_id_count < 0) {
1970 ohci_notice(ohci,
1971 "could not construct local self ID\n");
1972 return;
1973 }
1974 }
1975
1976 if (self_id_count == 0) {
1977 ohci_notice(ohci, "no self IDs\n");
1978 return;
1979 }
1980 rmb();
1981
1982 /*
1983 * Check the consistency of the self IDs we just read. The
1984 * problem we face is that a new bus reset can start while we
1985 * read out the self IDs from the DMA buffer. If this happens,
1986 * the DMA buffer will be overwritten with new self IDs and we
1987 * will read out inconsistent data. The OHCI specification
1988 * (section 11.2) recommends a technique similar to
1989 * linux/seqlock.h, where we remember the generation of the
1990 * self IDs in the buffer before reading them out and compare
1991 * it to the current generation after reading them out. If
1992 * the two generations match we know we have a consistent set
1993 * of self IDs.
1994 */
1995
1996 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1997 if (new_generation != generation) {
1998 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1999 return;
2000 }
2001
2002 /* FIXME: Document how the locking works. */
2003 spin_lock_irq(&ohci->lock);
2004
2005 ohci->generation = -1; /* prevent AT packet queueing */
2006 context_stop(&ohci->at_request_ctx);
2007 context_stop(&ohci->at_response_ctx);
2008
2009 spin_unlock_irq(&ohci->lock);
2010
2011 /*
2012 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2013 * packets in the AT queues and software needs to drain them.
2014 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2015 */
2016 at_context_flush(&ohci->at_request_ctx);
2017 at_context_flush(&ohci->at_response_ctx);
2018
2019 spin_lock_irq(&ohci->lock);
2020
2021 ohci->generation = generation;
2022 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2023
2024 if (ohci->quirks & QUIRK_RESET_PACKET)
2025 ohci->request_generation = generation;
2026
2027 /*
2028 * This next bit is unrelated to the AT context stuff but we
2029 * have to do it under the spinlock also. If a new config rom
2030 * was set up before this reset, the old one is now no longer
2031 * in use and we can free it. Update the config rom pointers
2032 * to point to the current config rom and clear the
2033 * next_config_rom pointer so a new update can take place.
2034 */
2035
2036 if (ohci->next_config_rom != NULL) {
2037 if (ohci->next_config_rom != ohci->config_rom) {
2038 free_rom = ohci->config_rom;
2039 free_rom_bus = ohci->config_rom_bus;
2040 }
2041 ohci->config_rom = ohci->next_config_rom;
2042 ohci->config_rom_bus = ohci->next_config_rom_bus;
2043 ohci->next_config_rom = NULL;
2044
2045 /*
2046 * Restore config_rom image and manually update
2047 * config_rom registers. Writing the header quadlet
2048 * will indicate that the config rom is ready, so we
2049 * do that last.
2050 */
2051 reg_write(ohci, OHCI1394_BusOptions,
2052 be32_to_cpu(ohci->config_rom[2]));
2053 ohci->config_rom[0] = ohci->next_header;
2054 reg_write(ohci, OHCI1394_ConfigROMhdr,
2055 be32_to_cpu(ohci->next_header));
2056 }
2057
2058 if (param_remote_dma) {
2059 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2060 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2061 }
2062
2063 spin_unlock_irq(&ohci->lock);
2064
2065 if (free_rom)
2066 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2067 free_rom, free_rom_bus);
2068
2069 log_selfids(ohci, generation, self_id_count);
2070
2071 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2072 self_id_count, ohci->self_id_buffer,
2073 ohci->csr_state_setclear_abdicate);
2074 ohci->csr_state_setclear_abdicate = false;
2075 }
2076
2077 static irqreturn_t irq_handler(int irq, void *data)
2078 {
2079 struct fw_ohci *ohci = data;
2080 u32 event, iso_event;
2081 int i;
2082
2083 event = reg_read(ohci, OHCI1394_IntEventClear);
2084
2085 if (!event || !~event)
2086 return IRQ_NONE;
2087
2088 /*
2089 * busReset and postedWriteErr must not be cleared yet
2090 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2091 */
2092 reg_write(ohci, OHCI1394_IntEventClear,
2093 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2094 log_irqs(ohci, event);
2095
2096 if (event & OHCI1394_selfIDComplete)
2097 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2098
2099 if (event & OHCI1394_RQPkt)
2100 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2101
2102 if (event & OHCI1394_RSPkt)
2103 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2104
2105 if (event & OHCI1394_reqTxComplete)
2106 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2107
2108 if (event & OHCI1394_respTxComplete)
2109 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2110
2111 if (event & OHCI1394_isochRx) {
2112 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2113 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2114
2115 while (iso_event) {
2116 i = ffs(iso_event) - 1;
2117 tasklet_schedule(
2118 &ohci->ir_context_list[i].context.tasklet);
2119 iso_event &= ~(1 << i);
2120 }
2121 }
2122
2123 if (event & OHCI1394_isochTx) {
2124 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2125 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2126
2127 while (iso_event) {
2128 i = ffs(iso_event) - 1;
2129 tasklet_schedule(
2130 &ohci->it_context_list[i].context.tasklet);
2131 iso_event &= ~(1 << i);
2132 }
2133 }
2134
2135 if (unlikely(event & OHCI1394_regAccessFail))
2136 ohci_err(ohci, "register access failure\n");
2137
2138 if (unlikely(event & OHCI1394_postedWriteErr)) {
2139 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2140 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2141 reg_write(ohci, OHCI1394_IntEventClear,
2142 OHCI1394_postedWriteErr);
2143 if (printk_ratelimit())
2144 ohci_err(ohci, "PCI posted write error\n");
2145 }
2146
2147 if (unlikely(event & OHCI1394_cycleTooLong)) {
2148 if (printk_ratelimit())
2149 ohci_notice(ohci, "isochronous cycle too long\n");
2150 reg_write(ohci, OHCI1394_LinkControlSet,
2151 OHCI1394_LinkControl_cycleMaster);
2152 }
2153
2154 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2155 /*
2156 * We need to clear this event bit in order to make
2157 * cycleMatch isochronous I/O work. In theory we should
2158 * stop active cycleMatch iso contexts now and restart
2159 * them at least two cycles later. (FIXME?)
2160 */
2161 if (printk_ratelimit())
2162 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2163 }
2164
2165 if (unlikely(event & OHCI1394_unrecoverableError))
2166 handle_dead_contexts(ohci);
2167
2168 if (event & OHCI1394_cycle64Seconds) {
2169 spin_lock(&ohci->lock);
2170 update_bus_time(ohci);
2171 spin_unlock(&ohci->lock);
2172 } else
2173 flush_writes(ohci);
2174
2175 return IRQ_HANDLED;
2176 }
2177
2178 static int software_reset(struct fw_ohci *ohci)
2179 {
2180 u32 val;
2181 int i;
2182
2183 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2184 for (i = 0; i < 500; i++) {
2185 val = reg_read(ohci, OHCI1394_HCControlSet);
2186 if (!~val)
2187 return -ENODEV; /* Card was ejected. */
2188
2189 if (!(val & OHCI1394_HCControl_softReset))
2190 return 0;
2191
2192 msleep(1);
2193 }
2194
2195 return -EBUSY;
2196 }
2197
2198 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2199 {
2200 size_t size = length * 4;
2201
2202 memcpy(dest, src, size);
2203 if (size < CONFIG_ROM_SIZE)
2204 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2205 }
2206
2207 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2208 {
2209 bool enable_1394a;
2210 int ret, clear, set, offset;
2211
2212 /* Check if the driver should configure link and PHY. */
2213 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2214 OHCI1394_HCControl_programPhyEnable))
2215 return 0;
2216
2217 /* Paranoia: check whether the PHY supports 1394a, too. */
2218 enable_1394a = false;
2219 ret = read_phy_reg(ohci, 2);
2220 if (ret < 0)
2221 return ret;
2222 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2223 ret = read_paged_phy_reg(ohci, 1, 8);
2224 if (ret < 0)
2225 return ret;
2226 if (ret >= 1)
2227 enable_1394a = true;
2228 }
2229
2230 if (ohci->quirks & QUIRK_NO_1394A)
2231 enable_1394a = false;
2232
2233 /* Configure PHY and link consistently. */
2234 if (enable_1394a) {
2235 clear = 0;
2236 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2237 } else {
2238 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2239 set = 0;
2240 }
2241 ret = update_phy_reg(ohci, 5, clear, set);
2242 if (ret < 0)
2243 return ret;
2244
2245 if (enable_1394a)
2246 offset = OHCI1394_HCControlSet;
2247 else
2248 offset = OHCI1394_HCControlClear;
2249 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2250
2251 /* Clean up: configuration has been taken care of. */
2252 reg_write(ohci, OHCI1394_HCControlClear,
2253 OHCI1394_HCControl_programPhyEnable);
2254
2255 return 0;
2256 }
2257
2258 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2259 {
2260 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2261 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2262 int reg, i;
2263
2264 reg = read_phy_reg(ohci, 2);
2265 if (reg < 0)
2266 return reg;
2267 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2268 return 0;
2269
2270 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2271 reg = read_paged_phy_reg(ohci, 1, i + 10);
2272 if (reg < 0)
2273 return reg;
2274 if (reg != id[i])
2275 return 0;
2276 }
2277 return 1;
2278 }
2279
2280 static int ohci_enable(struct fw_card *card,
2281 const __be32 *config_rom, size_t length)
2282 {
2283 struct fw_ohci *ohci = fw_ohci(card);
2284 u32 lps, version, irqs;
2285 int i, ret;
2286
2287 if (software_reset(ohci)) {
2288 ohci_err(ohci, "failed to reset ohci card\n");
2289 return -EBUSY;
2290 }
2291
2292 /*
2293 * Now enable LPS, which we need in order to start accessing
2294 * most of the registers. In fact, on some cards (ALI M5251),
2295 * accessing registers in the SClk domain without LPS enabled
2296 * will lock up the machine. Wait 50msec to make sure we have
2297 * full link enabled. However, with some cards (well, at least
2298 * a JMicron PCIe card), we have to try again sometimes.
2299 *
2300 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2301 * cannot actually use the phy at that time. These need tens of
2302 * millisecods pause between LPS write and first phy access too.
2303 */
2304
2305 reg_write(ohci, OHCI1394_HCControlSet,
2306 OHCI1394_HCControl_LPS |
2307 OHCI1394_HCControl_postedWriteEnable);
2308 flush_writes(ohci);
2309
2310 for (lps = 0, i = 0; !lps && i < 3; i++) {
2311 msleep(50);
2312 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2313 OHCI1394_HCControl_LPS;
2314 }
2315
2316 if (!lps) {
2317 ohci_err(ohci, "failed to set Link Power Status\n");
2318 return -EIO;
2319 }
2320
2321 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2322 ret = probe_tsb41ba3d(ohci);
2323 if (ret < 0)
2324 return ret;
2325 if (ret)
2326 ohci_notice(ohci, "local TSB41BA3D phy\n");
2327 else
2328 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2329 }
2330
2331 reg_write(ohci, OHCI1394_HCControlClear,
2332 OHCI1394_HCControl_noByteSwapData);
2333
2334 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2335 reg_write(ohci, OHCI1394_LinkControlSet,
2336 OHCI1394_LinkControl_cycleTimerEnable |
2337 OHCI1394_LinkControl_cycleMaster);
2338
2339 reg_write(ohci, OHCI1394_ATRetries,
2340 OHCI1394_MAX_AT_REQ_RETRIES |
2341 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2342 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2343 (200 << 16));
2344
2345 ohci->bus_time_running = false;
2346
2347 for (i = 0; i < 32; i++)
2348 if (ohci->ir_context_support & (1 << i))
2349 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2350 IR_CONTEXT_MULTI_CHANNEL_MODE);
2351
2352 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2353 if (version >= OHCI_VERSION_1_1) {
2354 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2355 0xfffffffe);
2356 card->broadcast_channel_auto_allocated = true;
2357 }
2358
2359 /* Get implemented bits of the priority arbitration request counter. */
2360 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2361 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2362 reg_write(ohci, OHCI1394_FairnessControl, 0);
2363 card->priority_budget_implemented = ohci->pri_req_max != 0;
2364
2365 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2366 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2367 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2368
2369 ret = configure_1394a_enhancements(ohci);
2370 if (ret < 0)
2371 return ret;
2372
2373 /* Activate link_on bit and contender bit in our self ID packets.*/
2374 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2375 if (ret < 0)
2376 return ret;
2377
2378 /*
2379 * When the link is not yet enabled, the atomic config rom
2380 * update mechanism described below in ohci_set_config_rom()
2381 * is not active. We have to update ConfigRomHeader and
2382 * BusOptions manually, and the write to ConfigROMmap takes
2383 * effect immediately. We tie this to the enabling of the
2384 * link, so we have a valid config rom before enabling - the
2385 * OHCI requires that ConfigROMhdr and BusOptions have valid
2386 * values before enabling.
2387 *
2388 * However, when the ConfigROMmap is written, some controllers
2389 * always read back quadlets 0 and 2 from the config rom to
2390 * the ConfigRomHeader and BusOptions registers on bus reset.
2391 * They shouldn't do that in this initial case where the link
2392 * isn't enabled. This means we have to use the same
2393 * workaround here, setting the bus header to 0 and then write
2394 * the right values in the bus reset tasklet.
2395 */
2396
2397 if (config_rom) {
2398 ohci->next_config_rom =
2399 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2400 &ohci->next_config_rom_bus,
2401 GFP_KERNEL);
2402 if (ohci->next_config_rom == NULL)
2403 return -ENOMEM;
2404
2405 copy_config_rom(ohci->next_config_rom, config_rom, length);
2406 } else {
2407 /*
2408 * In the suspend case, config_rom is NULL, which
2409 * means that we just reuse the old config rom.
2410 */
2411 ohci->next_config_rom = ohci->config_rom;
2412 ohci->next_config_rom_bus = ohci->config_rom_bus;
2413 }
2414
2415 ohci->next_header = ohci->next_config_rom[0];
2416 ohci->next_config_rom[0] = 0;
2417 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2418 reg_write(ohci, OHCI1394_BusOptions,
2419 be32_to_cpu(ohci->next_config_rom[2]));
2420 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2421
2422 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2423
2424 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2425 OHCI1394_RQPkt | OHCI1394_RSPkt |
2426 OHCI1394_isochTx | OHCI1394_isochRx |
2427 OHCI1394_postedWriteErr |
2428 OHCI1394_selfIDComplete |
2429 OHCI1394_regAccessFail |
2430 OHCI1394_cycleInconsistent |
2431 OHCI1394_unrecoverableError |
2432 OHCI1394_cycleTooLong |
2433 OHCI1394_masterIntEnable;
2434 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2435 irqs |= OHCI1394_busReset;
2436 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2437
2438 reg_write(ohci, OHCI1394_HCControlSet,
2439 OHCI1394_HCControl_linkEnable |
2440 OHCI1394_HCControl_BIBimageValid);
2441
2442 reg_write(ohci, OHCI1394_LinkControlSet,
2443 OHCI1394_LinkControl_rcvSelfID |
2444 OHCI1394_LinkControl_rcvPhyPkt);
2445
2446 ar_context_run(&ohci->ar_request_ctx);
2447 ar_context_run(&ohci->ar_response_ctx);
2448
2449 flush_writes(ohci);
2450
2451 /* We are ready to go, reset bus to finish initialization. */
2452 fw_schedule_bus_reset(&ohci->card, false, true);
2453
2454 return 0;
2455 }
2456
2457 static int ohci_set_config_rom(struct fw_card *card,
2458 const __be32 *config_rom, size_t length)
2459 {
2460 struct fw_ohci *ohci;
2461 __be32 *next_config_rom;
2462 dma_addr_t uninitialized_var(next_config_rom_bus);
2463
2464 ohci = fw_ohci(card);
2465
2466 /*
2467 * When the OHCI controller is enabled, the config rom update
2468 * mechanism is a bit tricky, but easy enough to use. See
2469 * section 5.5.6 in the OHCI specification.
2470 *
2471 * The OHCI controller caches the new config rom address in a
2472 * shadow register (ConfigROMmapNext) and needs a bus reset
2473 * for the changes to take place. When the bus reset is
2474 * detected, the controller loads the new values for the
2475 * ConfigRomHeader and BusOptions registers from the specified
2476 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2477 * shadow register. All automatically and atomically.
2478 *
2479 * Now, there's a twist to this story. The automatic load of
2480 * ConfigRomHeader and BusOptions doesn't honor the
2481 * noByteSwapData bit, so with a be32 config rom, the
2482 * controller will load be32 values in to these registers
2483 * during the atomic update, even on litte endian
2484 * architectures. The workaround we use is to put a 0 in the
2485 * header quadlet; 0 is endian agnostic and means that the
2486 * config rom isn't ready yet. In the bus reset tasklet we
2487 * then set up the real values for the two registers.
2488 *
2489 * We use ohci->lock to avoid racing with the code that sets
2490 * ohci->next_config_rom to NULL (see bus_reset_work).
2491 */
2492
2493 next_config_rom =
2494 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2495 &next_config_rom_bus, GFP_KERNEL);
2496 if (next_config_rom == NULL)
2497 return -ENOMEM;
2498
2499 spin_lock_irq(&ohci->lock);
2500
2501 /*
2502 * If there is not an already pending config_rom update,
2503 * push our new allocation into the ohci->next_config_rom
2504 * and then mark the local variable as null so that we
2505 * won't deallocate the new buffer.
2506 *
2507 * OTOH, if there is a pending config_rom update, just
2508 * use that buffer with the new config_rom data, and
2509 * let this routine free the unused DMA allocation.
2510 */
2511
2512 if (ohci->next_config_rom == NULL) {
2513 ohci->next_config_rom = next_config_rom;
2514 ohci->next_config_rom_bus = next_config_rom_bus;
2515 next_config_rom = NULL;
2516 }
2517
2518 copy_config_rom(ohci->next_config_rom, config_rom, length);
2519
2520 ohci->next_header = config_rom[0];
2521 ohci->next_config_rom[0] = 0;
2522
2523 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2524
2525 spin_unlock_irq(&ohci->lock);
2526
2527 /* If we didn't use the DMA allocation, delete it. */
2528 if (next_config_rom != NULL)
2529 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2530 next_config_rom, next_config_rom_bus);
2531
2532 /*
2533 * Now initiate a bus reset to have the changes take
2534 * effect. We clean up the old config rom memory and DMA
2535 * mappings in the bus reset tasklet, since the OHCI
2536 * controller could need to access it before the bus reset
2537 * takes effect.
2538 */
2539
2540 fw_schedule_bus_reset(&ohci->card, true, true);
2541
2542 return 0;
2543 }
2544
2545 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2546 {
2547 struct fw_ohci *ohci = fw_ohci(card);
2548
2549 at_context_transmit(&ohci->at_request_ctx, packet);
2550 }
2551
2552 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2553 {
2554 struct fw_ohci *ohci = fw_ohci(card);
2555
2556 at_context_transmit(&ohci->at_response_ctx, packet);
2557 }
2558
2559 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2560 {
2561 struct fw_ohci *ohci = fw_ohci(card);
2562 struct context *ctx = &ohci->at_request_ctx;
2563 struct driver_data *driver_data = packet->driver_data;
2564 int ret = -ENOENT;
2565
2566 tasklet_disable(&ctx->tasklet);
2567
2568 if (packet->ack != 0)
2569 goto out;
2570
2571 if (packet->payload_mapped)
2572 dma_unmap_single(ohci->card.device, packet->payload_bus,
2573 packet->payload_length, DMA_TO_DEVICE);
2574
2575 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2576 driver_data->packet = NULL;
2577 packet->ack = RCODE_CANCELLED;
2578 packet->callback(packet, &ohci->card, packet->ack);
2579 ret = 0;
2580 out:
2581 tasklet_enable(&ctx->tasklet);
2582
2583 return ret;
2584 }
2585
2586 static int ohci_enable_phys_dma(struct fw_card *card,
2587 int node_id, int generation)
2588 {
2589 struct fw_ohci *ohci = fw_ohci(card);
2590 unsigned long flags;
2591 int n, ret = 0;
2592
2593 if (param_remote_dma)
2594 return 0;
2595
2596 /*
2597 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2598 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2599 */
2600
2601 spin_lock_irqsave(&ohci->lock, flags);
2602
2603 if (ohci->generation != generation) {
2604 ret = -ESTALE;
2605 goto out;
2606 }
2607
2608 /*
2609 * Note, if the node ID contains a non-local bus ID, physical DMA is
2610 * enabled for _all_ nodes on remote buses.
2611 */
2612
2613 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2614 if (n < 32)
2615 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2616 else
2617 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2618
2619 flush_writes(ohci);
2620 out:
2621 spin_unlock_irqrestore(&ohci->lock, flags);
2622
2623 return ret;
2624 }
2625
2626 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2627 {
2628 struct fw_ohci *ohci = fw_ohci(card);
2629 unsigned long flags;
2630 u32 value;
2631
2632 switch (csr_offset) {
2633 case CSR_STATE_CLEAR:
2634 case CSR_STATE_SET:
2635 if (ohci->is_root &&
2636 (reg_read(ohci, OHCI1394_LinkControlSet) &
2637 OHCI1394_LinkControl_cycleMaster))
2638 value = CSR_STATE_BIT_CMSTR;
2639 else
2640 value = 0;
2641 if (ohci->csr_state_setclear_abdicate)
2642 value |= CSR_STATE_BIT_ABDICATE;
2643
2644 return value;
2645
2646 case CSR_NODE_IDS:
2647 return reg_read(ohci, OHCI1394_NodeID) << 16;
2648
2649 case CSR_CYCLE_TIME:
2650 return get_cycle_time(ohci);
2651
2652 case CSR_BUS_TIME:
2653 /*
2654 * We might be called just after the cycle timer has wrapped
2655 * around but just before the cycle64Seconds handler, so we
2656 * better check here, too, if the bus time needs to be updated.
2657 */
2658 spin_lock_irqsave(&ohci->lock, flags);
2659 value = update_bus_time(ohci);
2660 spin_unlock_irqrestore(&ohci->lock, flags);
2661 return value;
2662
2663 case CSR_BUSY_TIMEOUT:
2664 value = reg_read(ohci, OHCI1394_ATRetries);
2665 return (value >> 4) & 0x0ffff00f;
2666
2667 case CSR_PRIORITY_BUDGET:
2668 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2669 (ohci->pri_req_max << 8);
2670
2671 default:
2672 WARN_ON(1);
2673 return 0;
2674 }
2675 }
2676
2677 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2678 {
2679 struct fw_ohci *ohci = fw_ohci(card);
2680 unsigned long flags;
2681
2682 switch (csr_offset) {
2683 case CSR_STATE_CLEAR:
2684 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2685 reg_write(ohci, OHCI1394_LinkControlClear,
2686 OHCI1394_LinkControl_cycleMaster);
2687 flush_writes(ohci);
2688 }
2689 if (value & CSR_STATE_BIT_ABDICATE)
2690 ohci->csr_state_setclear_abdicate = false;
2691 break;
2692
2693 case CSR_STATE_SET:
2694 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2695 reg_write(ohci, OHCI1394_LinkControlSet,
2696 OHCI1394_LinkControl_cycleMaster);
2697 flush_writes(ohci);
2698 }
2699 if (value & CSR_STATE_BIT_ABDICATE)
2700 ohci->csr_state_setclear_abdicate = true;
2701 break;
2702
2703 case CSR_NODE_IDS:
2704 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2705 flush_writes(ohci);
2706 break;
2707
2708 case CSR_CYCLE_TIME:
2709 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2710 reg_write(ohci, OHCI1394_IntEventSet,
2711 OHCI1394_cycleInconsistent);
2712 flush_writes(ohci);
2713 break;
2714
2715 case CSR_BUS_TIME:
2716 spin_lock_irqsave(&ohci->lock, flags);
2717 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2718 (value & ~0x7f);
2719 spin_unlock_irqrestore(&ohci->lock, flags);
2720 break;
2721
2722 case CSR_BUSY_TIMEOUT:
2723 value = (value & 0xf) | ((value & 0xf) << 4) |
2724 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2725 reg_write(ohci, OHCI1394_ATRetries, value);
2726 flush_writes(ohci);
2727 break;
2728
2729 case CSR_PRIORITY_BUDGET:
2730 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2731 flush_writes(ohci);
2732 break;
2733
2734 default:
2735 WARN_ON(1);
2736 break;
2737 }
2738 }
2739
2740 static void flush_iso_completions(struct iso_context *ctx)
2741 {
2742 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2743 ctx->header_length, ctx->header,
2744 ctx->base.callback_data);
2745 ctx->header_length = 0;
2746 }
2747
2748 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2749 {
2750 u32 *ctx_hdr;
2751
2752 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2753 if (ctx->base.drop_overflow_headers)
2754 return;
2755 flush_iso_completions(ctx);
2756 }
2757
2758 ctx_hdr = ctx->header + ctx->header_length;
2759 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2760
2761 /*
2762 * The two iso header quadlets are byteswapped to little
2763 * endian by the controller, but we want to present them
2764 * as big endian for consistency with the bus endianness.
2765 */
2766 if (ctx->base.header_size > 0)
2767 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2768 if (ctx->base.header_size > 4)
2769 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2770 if (ctx->base.header_size > 8)
2771 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2772 ctx->header_length += ctx->base.header_size;
2773 }
2774
2775 static int handle_ir_packet_per_buffer(struct context *context,
2776 struct descriptor *d,
2777 struct descriptor *last)
2778 {
2779 struct iso_context *ctx =
2780 container_of(context, struct iso_context, context);
2781 struct descriptor *pd;
2782 u32 buffer_dma;
2783
2784 for (pd = d; pd <= last; pd++)
2785 if (pd->transfer_status)
2786 break;
2787 if (pd > last)
2788 /* Descriptor(s) not done yet, stop iteration */
2789 return 0;
2790
2791 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2792 d++;
2793 buffer_dma = le32_to_cpu(d->data_address);
2794 dma_sync_single_range_for_cpu(context->ohci->card.device,
2795 buffer_dma & PAGE_MASK,
2796 buffer_dma & ~PAGE_MASK,
2797 le16_to_cpu(d->req_count),
2798 DMA_FROM_DEVICE);
2799 }
2800
2801 copy_iso_headers(ctx, (u32 *) (last + 1));
2802
2803 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2804 flush_iso_completions(ctx);
2805
2806 return 1;
2807 }
2808
2809 /* d == last because each descriptor block is only a single descriptor. */
2810 static int handle_ir_buffer_fill(struct context *context,
2811 struct descriptor *d,
2812 struct descriptor *last)
2813 {
2814 struct iso_context *ctx =
2815 container_of(context, struct iso_context, context);
2816 unsigned int req_count, res_count, completed;
2817 u32 buffer_dma;
2818
2819 req_count = le16_to_cpu(last->req_count);
2820 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2821 completed = req_count - res_count;
2822 buffer_dma = le32_to_cpu(last->data_address);
2823
2824 if (completed > 0) {
2825 ctx->mc_buffer_bus = buffer_dma;
2826 ctx->mc_completed = completed;
2827 }
2828
2829 if (res_count != 0)
2830 /* Descriptor(s) not done yet, stop iteration */
2831 return 0;
2832
2833 dma_sync_single_range_for_cpu(context->ohci->card.device,
2834 buffer_dma & PAGE_MASK,
2835 buffer_dma & ~PAGE_MASK,
2836 completed, DMA_FROM_DEVICE);
2837
2838 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2839 ctx->base.callback.mc(&ctx->base,
2840 buffer_dma + completed,
2841 ctx->base.callback_data);
2842 ctx->mc_completed = 0;
2843 }
2844
2845 return 1;
2846 }
2847
2848 static void flush_ir_buffer_fill(struct iso_context *ctx)
2849 {
2850 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2851 ctx->mc_buffer_bus & PAGE_MASK,
2852 ctx->mc_buffer_bus & ~PAGE_MASK,
2853 ctx->mc_completed, DMA_FROM_DEVICE);
2854
2855 ctx->base.callback.mc(&ctx->base,
2856 ctx->mc_buffer_bus + ctx->mc_completed,
2857 ctx->base.callback_data);
2858 ctx->mc_completed = 0;
2859 }
2860
2861 static inline void sync_it_packet_for_cpu(struct context *context,
2862 struct descriptor *pd)
2863 {
2864 __le16 control;
2865 u32 buffer_dma;
2866
2867 /* only packets beginning with OUTPUT_MORE* have data buffers */
2868 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2869 return;
2870
2871 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2872 pd += 2;
2873
2874 /*
2875 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2876 * data buffer is in the context program's coherent page and must not
2877 * be synced.
2878 */
2879 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2880 (context->current_bus & PAGE_MASK)) {
2881 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2882 return;
2883 pd++;
2884 }
2885
2886 do {
2887 buffer_dma = le32_to_cpu(pd->data_address);
2888 dma_sync_single_range_for_cpu(context->ohci->card.device,
2889 buffer_dma & PAGE_MASK,
2890 buffer_dma & ~PAGE_MASK,
2891 le16_to_cpu(pd->req_count),
2892 DMA_TO_DEVICE);
2893 control = pd->control;
2894 pd++;
2895 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2896 }
2897
2898 static int handle_it_packet(struct context *context,
2899 struct descriptor *d,
2900 struct descriptor *last)
2901 {
2902 struct iso_context *ctx =
2903 container_of(context, struct iso_context, context);
2904 struct descriptor *pd;
2905 __be32 *ctx_hdr;
2906
2907 for (pd = d; pd <= last; pd++)
2908 if (pd->transfer_status)
2909 break;
2910 if (pd > last)
2911 /* Descriptor(s) not done yet, stop iteration */
2912 return 0;
2913
2914 sync_it_packet_for_cpu(context, d);
2915
2916 if (ctx->header_length + 4 > PAGE_SIZE) {
2917 if (ctx->base.drop_overflow_headers)
2918 return 1;
2919 flush_iso_completions(ctx);
2920 }
2921
2922 ctx_hdr = ctx->header + ctx->header_length;
2923 ctx->last_timestamp = le16_to_cpu(last->res_count);
2924 /* Present this value as big-endian to match the receive code */
2925 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2926 le16_to_cpu(pd->res_count));
2927 ctx->header_length += 4;
2928
2929 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2930 flush_iso_completions(ctx);
2931
2932 return 1;
2933 }
2934
2935 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2936 {
2937 u32 hi = channels >> 32, lo = channels;
2938
2939 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2940 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2941 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2942 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2943 mmiowb();
2944 ohci->mc_channels = channels;
2945 }
2946
2947 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2948 int type, int channel, size_t header_size)
2949 {
2950 struct fw_ohci *ohci = fw_ohci(card);
2951 struct iso_context *uninitialized_var(ctx);
2952 descriptor_callback_t uninitialized_var(callback);
2953 u64 *uninitialized_var(channels);
2954 u32 *uninitialized_var(mask), uninitialized_var(regs);
2955 int index, ret = -EBUSY;
2956
2957 spin_lock_irq(&ohci->lock);
2958
2959 switch (type) {
2960 case FW_ISO_CONTEXT_TRANSMIT:
2961 mask = &ohci->it_context_mask;
2962 callback = handle_it_packet;
2963 index = ffs(*mask) - 1;
2964 if (index >= 0) {
2965 *mask &= ~(1 << index);
2966 regs = OHCI1394_IsoXmitContextBase(index);
2967 ctx = &ohci->it_context_list[index];
2968 }
2969 break;
2970
2971 case FW_ISO_CONTEXT_RECEIVE:
2972 channels = &ohci->ir_context_channels;
2973 mask = &ohci->ir_context_mask;
2974 callback = handle_ir_packet_per_buffer;
2975 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2976 if (index >= 0) {
2977 *channels &= ~(1ULL << channel);
2978 *mask &= ~(1 << index);
2979 regs = OHCI1394_IsoRcvContextBase(index);
2980 ctx = &ohci->ir_context_list[index];
2981 }
2982 break;
2983
2984 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2985 mask = &ohci->ir_context_mask;
2986 callback = handle_ir_buffer_fill;
2987 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2988 if (index >= 0) {
2989 ohci->mc_allocated = true;
2990 *mask &= ~(1 << index);
2991 regs = OHCI1394_IsoRcvContextBase(index);
2992 ctx = &ohci->ir_context_list[index];
2993 }
2994 break;
2995
2996 default:
2997 index = -1;
2998 ret = -ENOSYS;
2999 }
3000
3001 spin_unlock_irq(&ohci->lock);
3002
3003 if (index < 0)
3004 return ERR_PTR(ret);
3005
3006 memset(ctx, 0, sizeof(*ctx));
3007 ctx->header_length = 0;
3008 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3009 if (ctx->header == NULL) {
3010 ret = -ENOMEM;
3011 goto out;
3012 }
3013 ret = context_init(&ctx->context, ohci, regs, callback);
3014 if (ret < 0)
3015 goto out_with_header;
3016
3017 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3018 set_multichannel_mask(ohci, 0);
3019 ctx->mc_completed = 0;
3020 }
3021
3022 return &ctx->base;
3023
3024 out_with_header:
3025 free_page((unsigned long)ctx->header);
3026 out:
3027 spin_lock_irq(&ohci->lock);
3028
3029 switch (type) {
3030 case FW_ISO_CONTEXT_RECEIVE:
3031 *channels |= 1ULL << channel;
3032 break;
3033
3034 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3035 ohci->mc_allocated = false;
3036 break;
3037 }
3038 *mask |= 1 << index;
3039
3040 spin_unlock_irq(&ohci->lock);
3041
3042 return ERR_PTR(ret);
3043 }
3044
3045 static int ohci_start_iso(struct fw_iso_context *base,
3046 s32 cycle, u32 sync, u32 tags)
3047 {
3048 struct iso_context *ctx = container_of(base, struct iso_context, base);
3049 struct fw_ohci *ohci = ctx->context.ohci;
3050 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3051 int index;
3052
3053 /* the controller cannot start without any queued packets */
3054 if (ctx->context.last->branch_address == 0)
3055 return -ENODATA;
3056
3057 switch (ctx->base.type) {
3058 case FW_ISO_CONTEXT_TRANSMIT:
3059 index = ctx - ohci->it_context_list;
3060 match = 0;
3061 if (cycle >= 0)
3062 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3063 (cycle & 0x7fff) << 16;
3064
3065 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3066 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3067 context_run(&ctx->context, match);
3068 break;
3069
3070 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3071 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3072 /* fall through */
3073 case FW_ISO_CONTEXT_RECEIVE:
3074 index = ctx - ohci->ir_context_list;
3075 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3076 if (cycle >= 0) {
3077 match |= (cycle & 0x07fff) << 12;
3078 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3079 }
3080
3081 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3082 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3083 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3084 context_run(&ctx->context, control);
3085
3086 ctx->sync = sync;
3087 ctx->tags = tags;
3088
3089 break;
3090 }
3091
3092 return 0;
3093 }
3094
3095 static int ohci_stop_iso(struct fw_iso_context *base)
3096 {
3097 struct fw_ohci *ohci = fw_ohci(base->card);
3098 struct iso_context *ctx = container_of(base, struct iso_context, base);
3099 int index;
3100
3101 switch (ctx->base.type) {
3102 case FW_ISO_CONTEXT_TRANSMIT:
3103 index = ctx - ohci->it_context_list;
3104 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3105 break;
3106
3107 case FW_ISO_CONTEXT_RECEIVE:
3108 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3109 index = ctx - ohci->ir_context_list;
3110 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3111 break;
3112 }
3113 flush_writes(ohci);
3114 context_stop(&ctx->context);
3115 tasklet_kill(&ctx->context.tasklet);
3116
3117 return 0;
3118 }
3119
3120 static void ohci_free_iso_context(struct fw_iso_context *base)
3121 {
3122 struct fw_ohci *ohci = fw_ohci(base->card);
3123 struct iso_context *ctx = container_of(base, struct iso_context, base);
3124 unsigned long flags;
3125 int index;
3126
3127 ohci_stop_iso(base);
3128 context_release(&ctx->context);
3129 free_page((unsigned long)ctx->header);
3130
3131 spin_lock_irqsave(&ohci->lock, flags);
3132
3133 switch (base->type) {
3134 case FW_ISO_CONTEXT_TRANSMIT:
3135 index = ctx - ohci->it_context_list;
3136 ohci->it_context_mask |= 1 << index;
3137 break;
3138
3139 case FW_ISO_CONTEXT_RECEIVE:
3140 index = ctx - ohci->ir_context_list;
3141 ohci->ir_context_mask |= 1 << index;
3142 ohci->ir_context_channels |= 1ULL << base->channel;
3143 break;
3144
3145 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3146 index = ctx - ohci->ir_context_list;
3147 ohci->ir_context_mask |= 1 << index;
3148 ohci->ir_context_channels |= ohci->mc_channels;
3149 ohci->mc_channels = 0;
3150 ohci->mc_allocated = false;
3151 break;
3152 }
3153
3154 spin_unlock_irqrestore(&ohci->lock, flags);
3155 }
3156
3157 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3158 {
3159 struct fw_ohci *ohci = fw_ohci(base->card);
3160 unsigned long flags;
3161 int ret;
3162
3163 switch (base->type) {
3164 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3165
3166 spin_lock_irqsave(&ohci->lock, flags);
3167
3168 /* Don't allow multichannel to grab other contexts' channels. */
3169 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3170 *channels = ohci->ir_context_channels;
3171 ret = -EBUSY;
3172 } else {
3173 set_multichannel_mask(ohci, *channels);
3174 ret = 0;
3175 }
3176
3177 spin_unlock_irqrestore(&ohci->lock, flags);
3178
3179 break;
3180 default:
3181 ret = -EINVAL;
3182 }
3183
3184 return ret;
3185 }
3186
3187 #ifdef CONFIG_PM
3188 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3189 {
3190 int i;
3191 struct iso_context *ctx;
3192
3193 for (i = 0 ; i < ohci->n_ir ; i++) {
3194 ctx = &ohci->ir_context_list[i];
3195 if (ctx->context.running)
3196 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3197 }
3198
3199 for (i = 0 ; i < ohci->n_it ; i++) {
3200 ctx = &ohci->it_context_list[i];
3201 if (ctx->context.running)
3202 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3203 }
3204 }
3205 #endif
3206
3207 static int queue_iso_transmit(struct iso_context *ctx,
3208 struct fw_iso_packet *packet,
3209 struct fw_iso_buffer *buffer,
3210 unsigned long payload)
3211 {
3212 struct descriptor *d, *last, *pd;
3213 struct fw_iso_packet *p;
3214 __le32 *header;
3215 dma_addr_t d_bus, page_bus;
3216 u32 z, header_z, payload_z, irq;
3217 u32 payload_index, payload_end_index, next_page_index;
3218 int page, end_page, i, length, offset;
3219
3220 p = packet;
3221 payload_index = payload;
3222
3223 if (p->skip)
3224 z = 1;
3225 else
3226 z = 2;
3227 if (p->header_length > 0)
3228 z++;
3229
3230 /* Determine the first page the payload isn't contained in. */
3231 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3232 if (p->payload_length > 0)
3233 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3234 else
3235 payload_z = 0;
3236
3237 z += payload_z;
3238
3239 /* Get header size in number of descriptors. */
3240 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3241
3242 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3243 if (d == NULL)
3244 return -ENOMEM;
3245
3246 if (!p->skip) {
3247 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3248 d[0].req_count = cpu_to_le16(8);
3249 /*
3250 * Link the skip address to this descriptor itself. This causes
3251 * a context to skip a cycle whenever lost cycles or FIFO
3252 * overruns occur, without dropping the data. The application
3253 * should then decide whether this is an error condition or not.
3254 * FIXME: Make the context's cycle-lost behaviour configurable?
3255 */
3256 d[0].branch_address = cpu_to_le32(d_bus | z);
3257
3258 header = (__le32 *) &d[1];
3259 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3260 IT_HEADER_TAG(p->tag) |
3261 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3262 IT_HEADER_CHANNEL(ctx->base.channel) |
3263 IT_HEADER_SPEED(ctx->base.speed));
3264 header[1] =
3265 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3266 p->payload_length));
3267 }
3268
3269 if (p->header_length > 0) {
3270 d[2].req_count = cpu_to_le16(p->header_length);
3271 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3272 memcpy(&d[z], p->header, p->header_length);
3273 }
3274
3275 pd = d + z - payload_z;
3276 payload_end_index = payload_index + p->payload_length;
3277 for (i = 0; i < payload_z; i++) {
3278 page = payload_index >> PAGE_SHIFT;
3279 offset = payload_index & ~PAGE_MASK;
3280 next_page_index = (page + 1) << PAGE_SHIFT;
3281 length =
3282 min(next_page_index, payload_end_index) - payload_index;
3283 pd[i].req_count = cpu_to_le16(length);
3284
3285 page_bus = page_private(buffer->pages[page]);
3286 pd[i].data_address = cpu_to_le32(page_bus + offset);
3287
3288 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3289 page_bus, offset, length,
3290 DMA_TO_DEVICE);
3291
3292 payload_index += length;
3293 }
3294
3295 if (p->interrupt)
3296 irq = DESCRIPTOR_IRQ_ALWAYS;
3297 else
3298 irq = DESCRIPTOR_NO_IRQ;
3299
3300 last = z == 2 ? d : d + z - 1;
3301 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3302 DESCRIPTOR_STATUS |
3303 DESCRIPTOR_BRANCH_ALWAYS |
3304 irq);
3305
3306 context_append(&ctx->context, d, z, header_z);
3307
3308 return 0;
3309 }
3310
3311 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3312 struct fw_iso_packet *packet,
3313 struct fw_iso_buffer *buffer,
3314 unsigned long payload)
3315 {
3316 struct device *device = ctx->context.ohci->card.device;
3317 struct descriptor *d, *pd;
3318 dma_addr_t d_bus, page_bus;
3319 u32 z, header_z, rest;
3320 int i, j, length;
3321 int page, offset, packet_count, header_size, payload_per_buffer;
3322
3323 /*
3324 * The OHCI controller puts the isochronous header and trailer in the
3325 * buffer, so we need at least 8 bytes.
3326 */
3327 packet_count = packet->header_length / ctx->base.header_size;
3328 header_size = max(ctx->base.header_size, (size_t)8);
3329
3330 /* Get header size in number of descriptors. */
3331 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3332 page = payload >> PAGE_SHIFT;
3333 offset = payload & ~PAGE_MASK;
3334 payload_per_buffer = packet->payload_length / packet_count;
3335
3336 for (i = 0; i < packet_count; i++) {
3337 /* d points to the header descriptor */
3338 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3339 d = context_get_descriptors(&ctx->context,
3340 z + header_z, &d_bus);
3341 if (d == NULL)
3342 return -ENOMEM;
3343
3344 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3345 DESCRIPTOR_INPUT_MORE);
3346 if (packet->skip && i == 0)
3347 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3348 d->req_count = cpu_to_le16(header_size);
3349 d->res_count = d->req_count;
3350 d->transfer_status = 0;
3351 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3352
3353 rest = payload_per_buffer;
3354 pd = d;
3355 for (j = 1; j < z; j++) {
3356 pd++;
3357 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3358 DESCRIPTOR_INPUT_MORE);
3359
3360 if (offset + rest < PAGE_SIZE)
3361 length = rest;
3362 else
3363 length = PAGE_SIZE - offset;
3364 pd->req_count = cpu_to_le16(length);
3365 pd->res_count = pd->req_count;
3366 pd->transfer_status = 0;
3367
3368 page_bus = page_private(buffer->pages[page]);
3369 pd->data_address = cpu_to_le32(page_bus + offset);
3370
3371 dma_sync_single_range_for_device(device, page_bus,
3372 offset, length,
3373 DMA_FROM_DEVICE);
3374
3375 offset = (offset + length) & ~PAGE_MASK;
3376 rest -= length;
3377 if (offset == 0)
3378 page++;
3379 }
3380 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3381 DESCRIPTOR_INPUT_LAST |
3382 DESCRIPTOR_BRANCH_ALWAYS);
3383 if (packet->interrupt && i == packet_count - 1)
3384 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3385
3386 context_append(&ctx->context, d, z, header_z);
3387 }
3388
3389 return 0;
3390 }
3391
3392 static int queue_iso_buffer_fill(struct iso_context *ctx,
3393 struct fw_iso_packet *packet,
3394 struct fw_iso_buffer *buffer,
3395 unsigned long payload)
3396 {
3397 struct descriptor *d;
3398 dma_addr_t d_bus, page_bus;
3399 int page, offset, rest, z, i, length;
3400
3401 page = payload >> PAGE_SHIFT;
3402 offset = payload & ~PAGE_MASK;
3403 rest = packet->payload_length;
3404
3405 /* We need one descriptor for each page in the buffer. */
3406 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3407
3408 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3409 return -EFAULT;
3410
3411 for (i = 0; i < z; i++) {
3412 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3413 if (d == NULL)
3414 return -ENOMEM;
3415
3416 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3417 DESCRIPTOR_BRANCH_ALWAYS);
3418 if (packet->skip && i == 0)
3419 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3420 if (packet->interrupt && i == z - 1)
3421 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3422
3423 if (offset + rest < PAGE_SIZE)
3424 length = rest;
3425 else
3426 length = PAGE_SIZE - offset;
3427 d->req_count = cpu_to_le16(length);
3428 d->res_count = d->req_count;
3429 d->transfer_status = 0;
3430
3431 page_bus = page_private(buffer->pages[page]);
3432 d->data_address = cpu_to_le32(page_bus + offset);
3433
3434 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3435 page_bus, offset, length,
3436 DMA_FROM_DEVICE);
3437
3438 rest -= length;
3439 offset = 0;
3440 page++;
3441
3442 context_append(&ctx->context, d, 1, 0);
3443 }
3444
3445 return 0;
3446 }
3447
3448 static int ohci_queue_iso(struct fw_iso_context *base,
3449 struct fw_iso_packet *packet,
3450 struct fw_iso_buffer *buffer,
3451 unsigned long payload)
3452 {
3453 struct iso_context *ctx = container_of(base, struct iso_context, base);
3454 unsigned long flags;
3455 int ret = -ENOSYS;
3456
3457 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3458 switch (base->type) {
3459 case FW_ISO_CONTEXT_TRANSMIT:
3460 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3461 break;
3462 case FW_ISO_CONTEXT_RECEIVE:
3463 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3464 break;
3465 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3466 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3467 break;
3468 }
3469 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3470
3471 return ret;
3472 }
3473
3474 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3475 {
3476 struct context *ctx =
3477 &container_of(base, struct iso_context, base)->context;
3478
3479 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3480 }
3481
3482 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3483 {
3484 struct iso_context *ctx = container_of(base, struct iso_context, base);
3485 int ret = 0;
3486
3487 tasklet_disable(&ctx->context.tasklet);
3488
3489 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3490 context_tasklet((unsigned long)&ctx->context);
3491
3492 switch (base->type) {
3493 case FW_ISO_CONTEXT_TRANSMIT:
3494 case FW_ISO_CONTEXT_RECEIVE:
3495 if (ctx->header_length != 0)
3496 flush_iso_completions(ctx);
3497 break;
3498 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3499 if (ctx->mc_completed != 0)
3500 flush_ir_buffer_fill(ctx);
3501 break;
3502 default:
3503 ret = -ENOSYS;
3504 }
3505
3506 clear_bit_unlock(0, &ctx->flushing_completions);
3507 smp_mb__after_atomic();
3508 }
3509
3510 tasklet_enable(&ctx->context.tasklet);
3511
3512 return ret;
3513 }
3514
3515 static const struct fw_card_driver ohci_driver = {
3516 .enable = ohci_enable,
3517 .read_phy_reg = ohci_read_phy_reg,
3518 .update_phy_reg = ohci_update_phy_reg,
3519 .set_config_rom = ohci_set_config_rom,
3520 .send_request = ohci_send_request,
3521 .send_response = ohci_send_response,
3522 .cancel_packet = ohci_cancel_packet,
3523 .enable_phys_dma = ohci_enable_phys_dma,
3524 .read_csr = ohci_read_csr,
3525 .write_csr = ohci_write_csr,
3526
3527 .allocate_iso_context = ohci_allocate_iso_context,
3528 .free_iso_context = ohci_free_iso_context,
3529 .set_iso_channels = ohci_set_iso_channels,
3530 .queue_iso = ohci_queue_iso,
3531 .flush_queue_iso = ohci_flush_queue_iso,
3532 .flush_iso_completions = ohci_flush_iso_completions,
3533 .start_iso = ohci_start_iso,
3534 .stop_iso = ohci_stop_iso,
3535 };
3536
3537 #ifdef CONFIG_PPC_PMAC
3538 static void pmac_ohci_on(struct pci_dev *dev)
3539 {
3540 if (machine_is(powermac)) {
3541 struct device_node *ofn = pci_device_to_OF_node(dev);
3542
3543 if (ofn) {
3544 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3545 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3546 }
3547 }
3548 }
3549
3550 static void pmac_ohci_off(struct pci_dev *dev)
3551 {
3552 if (machine_is(powermac)) {
3553 struct device_node *ofn = pci_device_to_OF_node(dev);
3554
3555 if (ofn) {
3556 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3557 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3558 }
3559 }
3560 }
3561 #else
3562 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3563 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3564 #endif /* CONFIG_PPC_PMAC */
3565
3566 static int pci_probe(struct pci_dev *dev,
3567 const struct pci_device_id *ent)
3568 {
3569 struct fw_ohci *ohci;
3570 u32 bus_options, max_receive, link_speed, version;
3571 u64 guid;
3572 int i, err;
3573 size_t size;
3574
3575 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3576 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3577 return -ENOSYS;
3578 }
3579
3580 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3581 if (ohci == NULL) {
3582 err = -ENOMEM;
3583 goto fail;
3584 }
3585
3586 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3587
3588 pmac_ohci_on(dev);
3589
3590 err = pci_enable_device(dev);
3591 if (err) {
3592 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3593 goto fail_free;
3594 }
3595
3596 pci_set_master(dev);
3597 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3598 pci_set_drvdata(dev, ohci);
3599
3600 spin_lock_init(&ohci->lock);
3601 mutex_init(&ohci->phy_reg_mutex);
3602
3603 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3604
3605 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3606 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3607 ohci_err(ohci, "invalid MMIO resource\n");
3608 err = -ENXIO;
3609 goto fail_disable;
3610 }
3611
3612 err = pci_request_region(dev, 0, ohci_driver_name);
3613 if (err) {
3614 ohci_err(ohci, "MMIO resource unavailable\n");
3615 goto fail_disable;
3616 }
3617
3618 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3619 if (ohci->registers == NULL) {
3620 ohci_err(ohci, "failed to remap registers\n");
3621 err = -ENXIO;
3622 goto fail_iomem;
3623 }
3624
3625 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3626 if ((ohci_quirks[i].vendor == dev->vendor) &&
3627 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3628 ohci_quirks[i].device == dev->device) &&
3629 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3630 ohci_quirks[i].revision >= dev->revision)) {
3631 ohci->quirks = ohci_quirks[i].flags;
3632 break;
3633 }
3634 if (param_quirks)
3635 ohci->quirks = param_quirks;
3636
3637 /*
3638 * Because dma_alloc_coherent() allocates at least one page,
3639 * we save space by using a common buffer for the AR request/
3640 * response descriptors and the self IDs buffer.
3641 */
3642 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3643 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3644 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3645 PAGE_SIZE,
3646 &ohci->misc_buffer_bus,
3647 GFP_KERNEL);
3648 if (!ohci->misc_buffer) {
3649 err = -ENOMEM;
3650 goto fail_iounmap;
3651 }
3652
3653 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3654 OHCI1394_AsReqRcvContextControlSet);
3655 if (err < 0)
3656 goto fail_misc_buf;
3657
3658 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3659 OHCI1394_AsRspRcvContextControlSet);
3660 if (err < 0)
3661 goto fail_arreq_ctx;
3662
3663 err = context_init(&ohci->at_request_ctx, ohci,
3664 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3665 if (err < 0)
3666 goto fail_arrsp_ctx;
3667
3668 err = context_init(&ohci->at_response_ctx, ohci,
3669 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3670 if (err < 0)
3671 goto fail_atreq_ctx;
3672
3673 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3674 ohci->ir_context_channels = ~0ULL;
3675 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3676 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3677 ohci->ir_context_mask = ohci->ir_context_support;
3678 ohci->n_ir = hweight32(ohci->ir_context_mask);
3679 size = sizeof(struct iso_context) * ohci->n_ir;
3680 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3681
3682 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3683 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3684 /* JMicron JMB38x often shows 0 at first read, just ignore it */
3685 if (!ohci->it_context_support) {
3686 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3687 ohci->it_context_support = 0xf;
3688 }
3689 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3690 ohci->it_context_mask = ohci->it_context_support;
3691 ohci->n_it = hweight32(ohci->it_context_mask);
3692 size = sizeof(struct iso_context) * ohci->n_it;
3693 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3694
3695 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3696 err = -ENOMEM;
3697 goto fail_contexts;
3698 }
3699
3700 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3701 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3702
3703 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3704 max_receive = (bus_options >> 12) & 0xf;
3705 link_speed = bus_options & 0x7;
3706 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3707 reg_read(ohci, OHCI1394_GUIDLo);
3708
3709 if (!(ohci->quirks & QUIRK_NO_MSI))
3710 pci_enable_msi(dev);
3711 if (request_irq(dev->irq, irq_handler,
3712 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3713 ohci_driver_name, ohci)) {
3714 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3715 err = -EIO;
3716 goto fail_msi;
3717 }
3718
3719 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3720 if (err)
3721 goto fail_irq;
3722
3723 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3724 ohci_notice(ohci,
3725 "added OHCI v%x.%x device as card %d, "
3726 "%d IR + %d IT contexts, quirks 0x%x%s\n",
3727 version >> 16, version & 0xff, ohci->card.index,
3728 ohci->n_ir, ohci->n_it, ohci->quirks,
3729 reg_read(ohci, OHCI1394_PhyUpperBound) ?
3730 ", physUB" : "");
3731
3732 return 0;
3733
3734 fail_irq:
3735 free_irq(dev->irq, ohci);
3736 fail_msi:
3737 pci_disable_msi(dev);
3738 fail_contexts:
3739 kfree(ohci->ir_context_list);
3740 kfree(ohci->it_context_list);
3741 context_release(&ohci->at_response_ctx);
3742 fail_atreq_ctx:
3743 context_release(&ohci->at_request_ctx);
3744 fail_arrsp_ctx:
3745 ar_context_release(&ohci->ar_response_ctx);
3746 fail_arreq_ctx:
3747 ar_context_release(&ohci->ar_request_ctx);
3748 fail_misc_buf:
3749 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3750 ohci->misc_buffer, ohci->misc_buffer_bus);
3751 fail_iounmap:
3752 pci_iounmap(dev, ohci->registers);
3753 fail_iomem:
3754 pci_release_region(dev, 0);
3755 fail_disable:
3756 pci_disable_device(dev);
3757 fail_free:
3758 kfree(ohci);
3759 pmac_ohci_off(dev);
3760 fail:
3761 return err;
3762 }
3763
3764 static void pci_remove(struct pci_dev *dev)
3765 {
3766 struct fw_ohci *ohci = pci_get_drvdata(dev);
3767
3768 /*
3769 * If the removal is happening from the suspend state, LPS won't be
3770 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3771 */
3772 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3773 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3774 flush_writes(ohci);
3775 }
3776 cancel_work_sync(&ohci->bus_reset_work);
3777 fw_core_remove_card(&ohci->card);
3778
3779 /*
3780 * FIXME: Fail all pending packets here, now that the upper
3781 * layers can't queue any more.
3782 */
3783
3784 software_reset(ohci);
3785 free_irq(dev->irq, ohci);
3786
3787 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3788 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3789 ohci->next_config_rom, ohci->next_config_rom_bus);
3790 if (ohci->config_rom)
3791 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3792 ohci->config_rom, ohci->config_rom_bus);
3793 ar_context_release(&ohci->ar_request_ctx);
3794 ar_context_release(&ohci->ar_response_ctx);
3795 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3796 ohci->misc_buffer, ohci->misc_buffer_bus);
3797 context_release(&ohci->at_request_ctx);
3798 context_release(&ohci->at_response_ctx);
3799 kfree(ohci->it_context_list);
3800 kfree(ohci->ir_context_list);
3801 pci_disable_msi(dev);
3802 pci_iounmap(dev, ohci->registers);
3803 pci_release_region(dev, 0);
3804 pci_disable_device(dev);
3805 kfree(ohci);
3806 pmac_ohci_off(dev);
3807
3808 dev_notice(&dev->dev, "removed fw-ohci device\n");
3809 }
3810
3811 #ifdef CONFIG_PM
3812 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3813 {
3814 struct fw_ohci *ohci = pci_get_drvdata(dev);
3815 int err;
3816
3817 software_reset(ohci);
3818 err = pci_save_state(dev);
3819 if (err) {
3820 ohci_err(ohci, "pci_save_state failed\n");
3821 return err;
3822 }
3823 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3824 if (err)
3825 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3826 pmac_ohci_off(dev);
3827
3828 return 0;
3829 }
3830
3831 static int pci_resume(struct pci_dev *dev)
3832 {
3833 struct fw_ohci *ohci = pci_get_drvdata(dev);
3834 int err;
3835
3836 pmac_ohci_on(dev);
3837 pci_set_power_state(dev, PCI_D0);
3838 pci_restore_state(dev);
3839 err = pci_enable_device(dev);
3840 if (err) {
3841 ohci_err(ohci, "pci_enable_device failed\n");
3842 return err;
3843 }
3844
3845 /* Some systems don't setup GUID register on resume from ram */
3846 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3847 !reg_read(ohci, OHCI1394_GUIDHi)) {
3848 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3849 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3850 }
3851
3852 err = ohci_enable(&ohci->card, NULL, 0);
3853 if (err)
3854 return err;
3855
3856 ohci_resume_iso_dma(ohci);
3857
3858 return 0;
3859 }
3860 #endif
3861
3862 static const struct pci_device_id pci_table[] = {
3863 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3864 { }
3865 };
3866
3867 MODULE_DEVICE_TABLE(pci, pci_table);
3868
3869 static struct pci_driver fw_ohci_pci_driver = {
3870 .name = ohci_driver_name,
3871 .id_table = pci_table,
3872 .probe = pci_probe,
3873 .remove = pci_remove,
3874 #ifdef CONFIG_PM
3875 .resume = pci_resume,
3876 .suspend = pci_suspend,
3877 #endif
3878 };
3879
3880 static int __init fw_ohci_init(void)
3881 {
3882 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3883 if (!selfid_workqueue)
3884 return -ENOMEM;
3885
3886 return pci_register_driver(&fw_ohci_pci_driver);
3887 }
3888
3889 static void __exit fw_ohci_cleanup(void)
3890 {
3891 pci_unregister_driver(&fw_ohci_pci_driver);
3892 destroy_workqueue(selfid_workqueue);
3893 }
3894
3895 module_init(fw_ohci_init);
3896 module_exit(fw_ohci_cleanup);
3897
3898 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3899 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3900 MODULE_LICENSE("GPL");
3901
3902 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3903 MODULE_ALIAS("ohci1394");
Linux with added FPC-III support