dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / gpio / gpio-bcm-kona.c
blob4ea71d505bcefc61ab764e3aee384333f693b54e
1 /*
2 * Copyright (C) 2012-2014 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/module.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/chained_irq.h>
24 #define BCM_GPIO_PASSWD 0x00a5a501
25 #define GPIO_PER_BANK 32
26 #define GPIO_MAX_BANK_NUM 8
28 #define GPIO_BANK(gpio) ((gpio) >> 5)
29 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
31 /* There is a GPIO control register for each GPIO */
32 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
34 /* The remaining registers are per GPIO bank */
35 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
36 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
37 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
38 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
39 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
40 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
41 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
42 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
44 #define GPIO_GPPWR_OFFSET 0x00000520
46 #define GPIO_GPCTR0_DBR_SHIFT 5
47 #define GPIO_GPCTR0_DBR_MASK 0x000001e0
49 #define GPIO_GPCTR0_ITR_SHIFT 3
50 #define GPIO_GPCTR0_ITR_MASK 0x00000018
51 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
52 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
53 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
55 #define GPIO_GPCTR0_IOTR_MASK 0x00000001
56 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
57 #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
59 #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
61 #define LOCK_CODE 0xffffffff
62 #define UNLOCK_CODE 0x00000000
64 struct bcm_kona_gpio {
65 void __iomem *reg_base;
66 int num_bank;
67 spinlock_t lock;
68 struct gpio_chip gpio_chip;
69 struct irq_domain *irq_domain;
70 struct bcm_kona_gpio_bank *banks;
71 struct platform_device *pdev;
74 struct bcm_kona_gpio_bank {
75 int id;
76 int irq;
77 /* Used in the interrupt handler */
78 struct bcm_kona_gpio *kona_gpio;
81 static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
83 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
86 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
87 int bank_id, u32 lockcode)
89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
93 static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
94 unsigned gpio)
96 u32 val;
97 unsigned long flags;
98 int bank_id = GPIO_BANK(gpio);
100 spin_lock_irqsave(&kona_gpio->lock, flags);
102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
103 val |= BIT(gpio);
104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
106 spin_unlock_irqrestore(&kona_gpio->lock, flags);
109 static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
110 unsigned gpio)
112 u32 val;
113 unsigned long flags;
114 int bank_id = GPIO_BANK(gpio);
116 spin_lock_irqsave(&kona_gpio->lock, flags);
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
119 val &= ~BIT(gpio);
120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
122 spin_unlock_irqrestore(&kona_gpio->lock, flags);
125 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
127 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
128 void __iomem *reg_base = kona_gpio->reg_base;
129 u32 val;
131 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
132 return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
135 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
137 struct bcm_kona_gpio *kona_gpio;
138 void __iomem *reg_base;
139 int bank_id = GPIO_BANK(gpio);
140 int bit = GPIO_BIT(gpio);
141 u32 val, reg_offset;
142 unsigned long flags;
144 kona_gpio = to_kona_gpio(chip);
145 reg_base = kona_gpio->reg_base;
146 spin_lock_irqsave(&kona_gpio->lock, flags);
148 /* this function only applies to output pin */
149 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
150 goto out;
152 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
154 val = readl(reg_base + reg_offset);
155 val |= BIT(bit);
156 writel(val, reg_base + reg_offset);
158 out:
159 spin_unlock_irqrestore(&kona_gpio->lock, flags);
162 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
164 struct bcm_kona_gpio *kona_gpio;
165 void __iomem *reg_base;
166 int bank_id = GPIO_BANK(gpio);
167 int bit = GPIO_BIT(gpio);
168 u32 val, reg_offset;
169 unsigned long flags;
171 kona_gpio = to_kona_gpio(chip);
172 reg_base = kona_gpio->reg_base;
173 spin_lock_irqsave(&kona_gpio->lock, flags);
175 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
176 reg_offset = GPIO_IN_STATUS(bank_id);
177 else
178 reg_offset = GPIO_OUT_STATUS(bank_id);
180 /* read the GPIO bank status */
181 val = readl(reg_base + reg_offset);
183 spin_unlock_irqrestore(&kona_gpio->lock, flags);
185 /* return the specified bit status */
186 return !!(val & BIT(bit));
189 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
191 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
193 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
194 return 0;
197 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
199 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
201 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
204 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
206 struct bcm_kona_gpio *kona_gpio;
207 void __iomem *reg_base;
208 u32 val;
209 unsigned long flags;
211 kona_gpio = to_kona_gpio(chip);
212 reg_base = kona_gpio->reg_base;
213 spin_lock_irqsave(&kona_gpio->lock, flags);
215 val = readl(reg_base + GPIO_CONTROL(gpio));
216 val &= ~GPIO_GPCTR0_IOTR_MASK;
217 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
218 writel(val, reg_base + GPIO_CONTROL(gpio));
220 spin_unlock_irqrestore(&kona_gpio->lock, flags);
222 return 0;
225 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
226 unsigned gpio, int value)
228 struct bcm_kona_gpio *kona_gpio;
229 void __iomem *reg_base;
230 int bank_id = GPIO_BANK(gpio);
231 int bit = GPIO_BIT(gpio);
232 u32 val, reg_offset;
233 unsigned long flags;
235 kona_gpio = to_kona_gpio(chip);
236 reg_base = kona_gpio->reg_base;
237 spin_lock_irqsave(&kona_gpio->lock, flags);
239 val = readl(reg_base + GPIO_CONTROL(gpio));
240 val &= ~GPIO_GPCTR0_IOTR_MASK;
241 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
242 writel(val, reg_base + GPIO_CONTROL(gpio));
243 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
245 val = readl(reg_base + reg_offset);
246 val |= BIT(bit);
247 writel(val, reg_base + reg_offset);
249 spin_unlock_irqrestore(&kona_gpio->lock, flags);
251 return 0;
254 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
256 struct bcm_kona_gpio *kona_gpio;
258 kona_gpio = to_kona_gpio(chip);
259 if (gpio >= kona_gpio->gpio_chip.ngpio)
260 return -ENXIO;
261 return irq_create_mapping(kona_gpio->irq_domain, gpio);
264 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
265 unsigned debounce)
267 struct bcm_kona_gpio *kona_gpio;
268 void __iomem *reg_base;
269 u32 val, res;
270 unsigned long flags;
272 kona_gpio = to_kona_gpio(chip);
273 reg_base = kona_gpio->reg_base;
274 /* debounce must be 1-128ms (or 0) */
275 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
276 dev_err(chip->dev, "Debounce value %u not in range\n",
277 debounce);
278 return -EINVAL;
281 /* calculate debounce bit value */
282 if (debounce != 0) {
283 /* Convert to ms */
284 debounce /= 1000;
285 /* find the MSB */
286 res = fls(debounce) - 1;
287 /* Check if MSB-1 is set (round up or down) */
288 if (res > 0 && (debounce & BIT(res - 1)))
289 res++;
292 /* spin lock for read-modify-write of the GPIO register */
293 spin_lock_irqsave(&kona_gpio->lock, flags);
295 val = readl(reg_base + GPIO_CONTROL(gpio));
296 val &= ~GPIO_GPCTR0_DBR_MASK;
298 if (debounce == 0) {
299 /* disable debounce */
300 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
301 } else {
302 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
303 (res << GPIO_GPCTR0_DBR_SHIFT);
306 writel(val, reg_base + GPIO_CONTROL(gpio));
308 spin_unlock_irqrestore(&kona_gpio->lock, flags);
310 return 0;
313 static struct gpio_chip template_chip = {
314 .label = "bcm-kona-gpio",
315 .owner = THIS_MODULE,
316 .request = bcm_kona_gpio_request,
317 .free = bcm_kona_gpio_free,
318 .get_direction = bcm_kona_gpio_get_dir,
319 .direction_input = bcm_kona_gpio_direction_input,
320 .get = bcm_kona_gpio_get,
321 .direction_output = bcm_kona_gpio_direction_output,
322 .set = bcm_kona_gpio_set,
323 .set_debounce = bcm_kona_gpio_set_debounce,
324 .to_irq = bcm_kona_gpio_to_irq,
325 .base = 0,
328 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
330 struct bcm_kona_gpio *kona_gpio;
331 void __iomem *reg_base;
332 unsigned gpio = d->hwirq;
333 int bank_id = GPIO_BANK(gpio);
334 int bit = GPIO_BIT(gpio);
335 u32 val;
336 unsigned long flags;
338 kona_gpio = irq_data_get_irq_chip_data(d);
339 reg_base = kona_gpio->reg_base;
340 spin_lock_irqsave(&kona_gpio->lock, flags);
342 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
343 val |= BIT(bit);
344 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
346 spin_unlock_irqrestore(&kona_gpio->lock, flags);
349 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
351 struct bcm_kona_gpio *kona_gpio;
352 void __iomem *reg_base;
353 unsigned gpio = d->hwirq;
354 int bank_id = GPIO_BANK(gpio);
355 int bit = GPIO_BIT(gpio);
356 u32 val;
357 unsigned long flags;
359 kona_gpio = irq_data_get_irq_chip_data(d);
360 reg_base = kona_gpio->reg_base;
361 spin_lock_irqsave(&kona_gpio->lock, flags);
363 val = readl(reg_base + GPIO_INT_MASK(bank_id));
364 val |= BIT(bit);
365 writel(val, reg_base + GPIO_INT_MASK(bank_id));
367 spin_unlock_irqrestore(&kona_gpio->lock, flags);
370 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
372 struct bcm_kona_gpio *kona_gpio;
373 void __iomem *reg_base;
374 unsigned gpio = d->hwirq;
375 int bank_id = GPIO_BANK(gpio);
376 int bit = GPIO_BIT(gpio);
377 u32 val;
378 unsigned long flags;
380 kona_gpio = irq_data_get_irq_chip_data(d);
381 reg_base = kona_gpio->reg_base;
382 spin_lock_irqsave(&kona_gpio->lock, flags);
384 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
385 val |= BIT(bit);
386 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
388 spin_unlock_irqrestore(&kona_gpio->lock, flags);
391 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
393 struct bcm_kona_gpio *kona_gpio;
394 void __iomem *reg_base;
395 unsigned gpio = d->hwirq;
396 u32 lvl_type;
397 u32 val;
398 unsigned long flags;
400 kona_gpio = irq_data_get_irq_chip_data(d);
401 reg_base = kona_gpio->reg_base;
402 switch (type & IRQ_TYPE_SENSE_MASK) {
403 case IRQ_TYPE_EDGE_RISING:
404 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
405 break;
407 case IRQ_TYPE_EDGE_FALLING:
408 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
409 break;
411 case IRQ_TYPE_EDGE_BOTH:
412 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
413 break;
415 case IRQ_TYPE_LEVEL_HIGH:
416 case IRQ_TYPE_LEVEL_LOW:
417 /* BCM GPIO doesn't support level triggering */
418 default:
419 dev_err(kona_gpio->gpio_chip.dev,
420 "Invalid BCM GPIO irq type 0x%x\n", type);
421 return -EINVAL;
424 spin_lock_irqsave(&kona_gpio->lock, flags);
426 val = readl(reg_base + GPIO_CONTROL(gpio));
427 val &= ~GPIO_GPCTR0_ITR_MASK;
428 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
429 writel(val, reg_base + GPIO_CONTROL(gpio));
431 spin_unlock_irqrestore(&kona_gpio->lock, flags);
433 return 0;
436 static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
438 void __iomem *reg_base;
439 int bit, bank_id;
440 unsigned long sta;
441 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
442 struct irq_chip *chip = irq_desc_get_chip(desc);
444 chained_irq_enter(chip, desc);
447 * For bank interrupts, we can't use chip_data to store the kona_gpio
448 * pointer, since GIC needs it for its own purposes. Therefore, we get
449 * our pointer from the bank structure.
451 reg_base = bank->kona_gpio->reg_base;
452 bank_id = bank->id;
454 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
455 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
456 for_each_set_bit(bit, &sta, 32) {
457 int hwirq = GPIO_PER_BANK * bank_id + bit;
458 int child_irq =
459 irq_find_mapping(bank->kona_gpio->irq_domain,
460 hwirq);
462 * Clear interrupt before handler is called so we don't
463 * miss any interrupt occurred during executing them.
465 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
466 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
467 /* Invoke interrupt handler */
468 generic_handle_irq(child_irq);
472 chained_irq_exit(chip, desc);
475 static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
477 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
479 if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
480 dev_err(kona_gpio->gpio_chip.dev,
481 "unable to lock HW IRQ %lu for IRQ\n",
482 d->hwirq);
483 return -EINVAL;
485 return 0;
488 static void bcm_kona_gpio_irq_relres(struct irq_data *d)
490 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
492 gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
495 static struct irq_chip bcm_gpio_irq_chip = {
496 .name = "bcm-kona-gpio",
497 .irq_ack = bcm_kona_gpio_irq_ack,
498 .irq_mask = bcm_kona_gpio_irq_mask,
499 .irq_unmask = bcm_kona_gpio_irq_unmask,
500 .irq_set_type = bcm_kona_gpio_irq_set_type,
501 .irq_request_resources = bcm_kona_gpio_irq_reqres,
502 .irq_release_resources = bcm_kona_gpio_irq_relres,
505 static struct of_device_id const bcm_kona_gpio_of_match[] = {
506 { .compatible = "brcm,kona-gpio" },
510 MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
513 * This lock class tells lockdep that GPIO irqs are in a different
514 * category than their parents, so it won't report false recursion.
516 static struct lock_class_key gpio_lock_class;
518 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
519 irq_hw_number_t hwirq)
521 int ret;
523 ret = irq_set_chip_data(irq, d->host_data);
524 if (ret < 0)
525 return ret;
526 irq_set_lockdep_class(irq, &gpio_lock_class);
527 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
528 irq_set_noprobe(irq);
530 return 0;
533 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
535 irq_set_chip_and_handler(irq, NULL, NULL);
536 irq_set_chip_data(irq, NULL);
539 static const struct irq_domain_ops bcm_kona_irq_ops = {
540 .map = bcm_kona_gpio_irq_map,
541 .unmap = bcm_kona_gpio_irq_unmap,
542 .xlate = irq_domain_xlate_twocell,
545 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
547 void __iomem *reg_base;
548 int i;
550 reg_base = kona_gpio->reg_base;
551 /* disable interrupts and clear status */
552 for (i = 0; i < kona_gpio->num_bank; i++) {
553 /* Unlock the entire bank first */
554 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
555 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
556 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
557 /* Now re-lock the bank */
558 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
562 static int bcm_kona_gpio_probe(struct platform_device *pdev)
564 struct device *dev = &pdev->dev;
565 const struct of_device_id *match;
566 struct resource *res;
567 struct bcm_kona_gpio_bank *bank;
568 struct bcm_kona_gpio *kona_gpio;
569 struct gpio_chip *chip;
570 int ret;
571 int i;
573 match = of_match_device(bcm_kona_gpio_of_match, dev);
574 if (!match) {
575 dev_err(dev, "Failed to find gpio controller\n");
576 return -ENODEV;
579 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
580 if (!kona_gpio)
581 return -ENOMEM;
583 kona_gpio->gpio_chip = template_chip;
584 chip = &kona_gpio->gpio_chip;
585 kona_gpio->num_bank = of_irq_count(dev->of_node);
586 if (kona_gpio->num_bank == 0) {
587 dev_err(dev, "Couldn't determine # GPIO banks\n");
588 return -ENOENT;
590 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
591 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
592 GPIO_MAX_BANK_NUM);
593 return -ENXIO;
595 kona_gpio->banks = devm_kzalloc(dev,
596 kona_gpio->num_bank *
597 sizeof(*kona_gpio->banks), GFP_KERNEL);
598 if (!kona_gpio->banks)
599 return -ENOMEM;
601 kona_gpio->pdev = pdev;
602 platform_set_drvdata(pdev, kona_gpio);
603 chip->of_node = dev->of_node;
604 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
606 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
607 chip->ngpio,
608 &bcm_kona_irq_ops,
609 kona_gpio);
610 if (!kona_gpio->irq_domain) {
611 dev_err(dev, "Couldn't allocate IRQ domain\n");
612 return -ENXIO;
615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
616 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
617 if (IS_ERR(kona_gpio->reg_base)) {
618 ret = -ENXIO;
619 goto err_irq_domain;
622 for (i = 0; i < kona_gpio->num_bank; i++) {
623 bank = &kona_gpio->banks[i];
624 bank->id = i;
625 bank->irq = platform_get_irq(pdev, i);
626 bank->kona_gpio = kona_gpio;
627 if (bank->irq < 0) {
628 dev_err(dev, "Couldn't get IRQ for bank %d", i);
629 ret = -ENOENT;
630 goto err_irq_domain;
634 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
636 bcm_kona_gpio_reset(kona_gpio);
638 ret = gpiochip_add(chip);
639 if (ret < 0) {
640 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
641 goto err_irq_domain;
643 for (i = 0; i < kona_gpio->num_bank; i++) {
644 bank = &kona_gpio->banks[i];
645 irq_set_chained_handler_and_data(bank->irq,
646 bcm_kona_gpio_irq_handler,
647 bank);
650 spin_lock_init(&kona_gpio->lock);
652 return 0;
654 err_irq_domain:
655 irq_domain_remove(kona_gpio->irq_domain);
657 return ret;
660 static struct platform_driver bcm_kona_gpio_driver = {
661 .driver = {
662 .name = "bcm-kona-gpio",
663 .of_match_table = bcm_kona_gpio_of_match,
665 .probe = bcm_kona_gpio_probe,
668 module_platform_driver(bcm_kona_gpio_driver);
670 MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
671 MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
672 MODULE_LICENSE("GPL v2");