drivers/gpio/gpio-intel-mid.c

   1 /*
   2  * Intel MID GPIO driver
   3  *
   4  * Copyright (c) 2008-2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* Supports:
  17  * Moorestown platform Langwell chip.
  18  * Medfield platform Penwell chip.
  19  * Clovertrail platform Cloverview chip.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/kernel.h>
  26 #include <linux/delay.h>
  27 #include <linux/stddef.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/init.h>
  30 #include <linux/io.h>
  31 #include <linux/gpio/driver.h>
  32 #include <linux/slab.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #define INTEL_MID_IRQ_TYPE_EDGE         (1 << 0)
  36 #define INTEL_MID_IRQ_TYPE_LEVEL        (1 << 1)
  37
  38 /*
  39  * Langwell chip has 64 pins and thus there are 2 32bit registers to control
  40  * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
  41  * registers to control them, so we only define the order here instead of a
  42  * structure, to get a bit offset for a pin (use GPDR as an example):
  43  *
  44  * nreg = ngpio / 32;
  45  * reg = offset / 32;
  46  * bit = offset % 32;
  47  * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
  48  *
  49  * so the bit of reg_addr is to control pin offset's GPDR feature
  50 */
  51
  52 enum GPIO_REG {
  53         GPLR = 0,       /* pin level read-only */
  54         GPDR,           /* pin direction */
  55         GPSR,           /* pin set */
  56         GPCR,           /* pin clear */
  57         GRER,           /* rising edge detect */
  58         GFER,           /* falling edge detect */
  59         GEDR,           /* edge detect result */
  60         GAFR,           /* alt function */
  61 };
  62
  63 /* intel_mid gpio driver data */
  64 struct intel_mid_gpio_ddata {
  65         u16 ngpio;              /* number of gpio pins */
  66         u32 chip_irq_type;      /* chip interrupt type */
  67 };
  68
  69 struct intel_mid_gpio {
  70         struct gpio_chip                chip;
  71         void __iomem                    *reg_base;
  72         spinlock_t                      lock;
  73         struct pci_dev                  *pdev;
  74 };
  75
  76 static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc)
  77 {
  78         return container_of(gc, struct intel_mid_gpio, chip);
  79 }
  80
  81 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
  82                               enum GPIO_REG reg_type)
  83 {
  84         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  85         unsigned nreg = chip->ngpio / 32;
  86         u8 reg = offset / 32;
  87
  88         return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  89 }
  90
  91 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
  92                                    enum GPIO_REG reg_type)
  93 {
  94         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  95         unsigned nreg = chip->ngpio / 32;
  96         u8 reg = offset / 16;
  97
  98         return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  99 }
 100
 101 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
 102 {
 103         void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
 104         u32 value = readl(gafr);
 105         int shift = (offset % 16) << 1, af = (value >> shift) & 3;
 106
 107         if (af) {
 108                 value &= ~(3 << shift);
 109                 writel(value, gafr);
 110         }
 111         return 0;
 112 }
 113
 114 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 115 {
 116         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
 117
 118         return readl(gplr) & BIT(offset % 32);
 119 }
 120
 121 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 122 {
 123         void __iomem *gpsr, *gpcr;
 124
 125         if (value) {
 126                 gpsr = gpio_reg(chip, offset, GPSR);
 127                 writel(BIT(offset % 32), gpsr);
 128         } else {
 129                 gpcr = gpio_reg(chip, offset, GPCR);
 130                 writel(BIT(offset % 32), gpcr);
 131         }
 132 }
 133
 134 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 135 {
 136         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 137         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 138         u32 value;
 139         unsigned long flags;
 140
 141         if (priv->pdev)
 142                 pm_runtime_get(&priv->pdev->dev);
 143
 144         spin_lock_irqsave(&priv->lock, flags);
 145         value = readl(gpdr);
 146         value &= ~BIT(offset % 32);
 147         writel(value, gpdr);
 148         spin_unlock_irqrestore(&priv->lock, flags);
 149
 150         if (priv->pdev)
 151                 pm_runtime_put(&priv->pdev->dev);
 152
 153         return 0;
 154 }
 155
 156 static int intel_gpio_direction_output(struct gpio_chip *chip,
 157                         unsigned offset, int value)
 158 {
 159         struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
 160         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 161         unsigned long flags;
 162
 163         intel_gpio_set(chip, offset, value);
 164
 165         if (priv->pdev)
 166                 pm_runtime_get(&priv->pdev->dev);
 167
 168         spin_lock_irqsave(&priv->lock, flags);
 169         value = readl(gpdr);
 170         value |= BIT(offset % 32);
 171         writel(value, gpdr);
 172         spin_unlock_irqrestore(&priv->lock, flags);
 173
 174         if (priv->pdev)
 175                 pm_runtime_put(&priv->pdev->dev);
 176
 177         return 0;
 178 }
 179
 180 static int intel_mid_irq_type(struct irq_data *d, unsigned type)
 181 {
 182         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 183         struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
 184         u32 gpio = irqd_to_hwirq(d);
 185         unsigned long flags;
 186         u32 value;
 187         void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
 188         void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
 189
 190         if (gpio >= priv->chip.ngpio)
 191                 return -EINVAL;
 192
 193         if (priv->pdev)
 194                 pm_runtime_get(&priv->pdev->dev);
 195
 196         spin_lock_irqsave(&priv->lock, flags);
 197         if (type & IRQ_TYPE_EDGE_RISING)
 198                 value = readl(grer) | BIT(gpio % 32);
 199         else
 200                 value = readl(grer) & (~BIT(gpio % 32));
 201         writel(value, grer);
 202
 203         if (type & IRQ_TYPE_EDGE_FALLING)
 204                 value = readl(gfer) | BIT(gpio % 32);
 205         else
 206                 value = readl(gfer) & (~BIT(gpio % 32));
 207         writel(value, gfer);
 208         spin_unlock_irqrestore(&priv->lock, flags);
 209
 210         if (priv->pdev)
 211                 pm_runtime_put(&priv->pdev->dev);
 212
 213         return 0;
 214 }
 215
 216 static void intel_mid_irq_unmask(struct irq_data *d)
 217 {
 218 }
 219
 220 static void intel_mid_irq_mask(struct irq_data *d)
 221 {
 222 }
 223
 224 static struct irq_chip intel_mid_irqchip = {
 225         .name           = "INTEL_MID-GPIO",
 226         .irq_mask       = intel_mid_irq_mask,
 227         .irq_unmask     = intel_mid_irq_unmask,
 228         .irq_set_type   = intel_mid_irq_type,
 229 };
 230
 231 static const struct intel_mid_gpio_ddata gpio_lincroft = {
 232         .ngpio = 64,
 233 };
 234
 235 static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
 236         .ngpio = 96,
 237         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 238 };
 239
 240 static const struct intel_mid_gpio_ddata gpio_penwell_core = {
 241         .ngpio = 96,
 242         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 243 };
 244
 245 static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
 246         .ngpio = 96,
 247         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
 248 };
 249
 250 static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
 251         .ngpio = 96,
 252         .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
 253 };
 254
 255 static const struct pci_device_id intel_gpio_ids[] = {
 256         {
 257                 /* Lincroft */
 258                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
 259                 .driver_data = (kernel_ulong_t)&gpio_lincroft,
 260         },
 261         {
 262                 /* Penwell AON */
 263                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
 264                 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
 265         },
 266         {
 267                 /* Penwell Core */
 268                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
 269                 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
 270         },
 271         {
 272                 /* Cloverview Aon */
 273                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
 274                 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
 275         },
 276         {
 277                 /* Cloverview Core */
 278                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
 279                 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
 280         },
 281         { 0 }
 282 };
 283 MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
 284
 285 static void intel_mid_irq_handler(struct irq_desc *desc)
 286 {
 287         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 288         struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
 289         struct irq_data *data = irq_desc_get_irq_data(desc);
 290         struct irq_chip *chip = irq_data_get_irq_chip(data);
 291         u32 base, gpio, mask;
 292         unsigned long pending;
 293         void __iomem *gedr;
 294
 295         /* check GPIO controller to check which pin triggered the interrupt */
 296         for (base = 0; base < priv->chip.ngpio; base += 32) {
 297                 gedr = gpio_reg(&priv->chip, base, GEDR);
 298                 while ((pending = readl(gedr))) {
 299                         gpio = __ffs(pending);
 300                         mask = BIT(gpio);
 301                         /* Clear before handling so we can't lose an edge */
 302                         writel(mask, gedr);
 303                         generic_handle_irq(irq_find_mapping(gc->irqdomain,
 304                                                             base + gpio));
 305                 }
 306         }
 307
 308         chip->irq_eoi(data);
 309 }
 310
 311 static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
 312 {
 313         void __iomem *reg;
 314         unsigned base;
 315
 316         for (base = 0; base < priv->chip.ngpio; base += 32) {
 317                 /* Clear the rising-edge detect register */
 318                 reg = gpio_reg(&priv->chip, base, GRER);
 319                 writel(0, reg);
 320                 /* Clear the falling-edge detect register */
 321                 reg = gpio_reg(&priv->chip, base, GFER);
 322                 writel(0, reg);
 323                 /* Clear the edge detect status register */
 324                 reg = gpio_reg(&priv->chip, base, GEDR);
 325                 writel(~0, reg);
 326         }
 327 }
 328
 329 static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
 330 {
 331         int err = pm_schedule_suspend(dev, 500);
 332         return err ?: -EBUSY;
 333 }
 334
 335 static const struct dev_pm_ops intel_gpio_pm_ops = {
 336         SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
 337 };
 338
 339 static int intel_gpio_probe(struct pci_dev *pdev,
 340                           const struct pci_device_id *id)
 341 {
 342         void __iomem *base;
 343         struct intel_mid_gpio *priv;
 344         u32 gpio_base;
 345         u32 irq_base;
 346         int retval;
 347         struct intel_mid_gpio_ddata *ddata =
 348                                 (struct intel_mid_gpio_ddata *)id->driver_data;
 349
 350         retval = pcim_enable_device(pdev);
 351         if (retval)
 352                 return retval;
 353
 354         retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
 355         if (retval) {
 356                 dev_err(&pdev->dev, "I/O memory mapping error\n");
 357                 return retval;
 358         }
 359
 360         base = pcim_iomap_table(pdev)[1];
 361
 362         irq_base = readl(base);
 363         gpio_base = readl(sizeof(u32) + base);
 364
 365         /* release the IO mapping, since we already get the info from bar1 */
 366         pcim_iounmap_regions(pdev, 1 << 1);
 367
 368         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 369         if (!priv) {
 370                 dev_err(&pdev->dev, "can't allocate chip data\n");
 371                 return -ENOMEM;
 372         }
 373
 374         priv->reg_base = pcim_iomap_table(pdev)[0];
 375         priv->chip.label = dev_name(&pdev->dev);
 376         priv->chip.dev = &pdev->dev;
 377         priv->chip.request = intel_gpio_request;
 378         priv->chip.direction_input = intel_gpio_direction_input;
 379         priv->chip.direction_output = intel_gpio_direction_output;
 380         priv->chip.get = intel_gpio_get;
 381         priv->chip.set = intel_gpio_set;
 382         priv->chip.base = gpio_base;
 383         priv->chip.ngpio = ddata->ngpio;
 384         priv->chip.can_sleep = false;
 385         priv->pdev = pdev;
 386
 387         spin_lock_init(&priv->lock);
 388
 389         pci_set_drvdata(pdev, priv);
 390         retval = gpiochip_add(&priv->chip);
 391         if (retval) {
 392                 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
 393                 return retval;
 394         }
 395
 396         retval = gpiochip_irqchip_add(&priv->chip,
 397                                       &intel_mid_irqchip,
 398                                       irq_base,
 399                                       handle_simple_irq,
 400                                       IRQ_TYPE_NONE);
 401         if (retval) {
 402                 dev_err(&pdev->dev,
 403                         "could not connect irqchip to gpiochip\n");
 404                 return retval;
 405         }
 406
 407         intel_mid_irq_init_hw(priv);
 408
 409         gpiochip_set_chained_irqchip(&priv->chip,
 410                                      &intel_mid_irqchip,
 411                                      pdev->irq,
 412                                      intel_mid_irq_handler);
 413
 414         pm_runtime_put_noidle(&pdev->dev);
 415         pm_runtime_allow(&pdev->dev);
 416
 417         return 0;
 418 }
 419
 420 static struct pci_driver intel_gpio_driver = {
 421         .name           = "intel_mid_gpio",
 422         .id_table       = intel_gpio_ids,
 423         .probe          = intel_gpio_probe,
 424         .driver         = {
 425                 .pm     = &intel_gpio_pm_ops,
 426         },
 427 };
 428
 429 static int __init intel_gpio_init(void)
 430 {
 431         return pci_register_driver(&intel_gpio_driver);
 432 }
 433
 434 device_initcall(intel_gpio_init);