drivers/i2c/busses/i2c-efm32.c

   1 /*
   2  * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it under
   5  * the terms of the GNU General Public License version 2 as published by the
   6  * Free Software Foundation.
   7  */
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/i2c.h>
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/err.h>
  14 #include <linux/clk.h>
  15
  16 #define DRIVER_NAME "efm32-i2c"
  17
  18 #define MASK_VAL(mask, val)             ((val << __ffs(mask)) & mask)
  19
  20 #define REG_CTRL                0x00
  21 #define REG_CTRL_EN                     0x00001
  22 #define REG_CTRL_SLAVE                  0x00002
  23 #define REG_CTRL_AUTOACK                0x00004
  24 #define REG_CTRL_AUTOSE                 0x00008
  25 #define REG_CTRL_AUTOSN                 0x00010
  26 #define REG_CTRL_ARBDIS                 0x00020
  27 #define REG_CTRL_GCAMEN                 0x00040
  28 #define REG_CTRL_CLHR__MASK             0x00300
  29 #define REG_CTRL_BITO__MASK             0x03000
  30 #define REG_CTRL_BITO_OFF               0x00000
  31 #define REG_CTRL_BITO_40PCC             0x01000
  32 #define REG_CTRL_BITO_80PCC             0x02000
  33 #define REG_CTRL_BITO_160PCC            0x03000
  34 #define REG_CTRL_GIBITO                 0x08000
  35 #define REG_CTRL_CLTO__MASK             0x70000
  36 #define REG_CTRL_CLTO_OFF               0x00000
  37
  38 #define REG_CMD                 0x04
  39 #define REG_CMD_START                   0x00001
  40 #define REG_CMD_STOP                    0x00002
  41 #define REG_CMD_ACK                     0x00004
  42 #define REG_CMD_NACK                    0x00008
  43 #define REG_CMD_CONT                    0x00010
  44 #define REG_CMD_ABORT                   0x00020
  45 #define REG_CMD_CLEARTX                 0x00040
  46 #define REG_CMD_CLEARPC                 0x00080
  47
  48 #define REG_STATE               0x08
  49 #define REG_STATE_BUSY                  0x00001
  50 #define REG_STATE_MASTER                0x00002
  51 #define REG_STATE_TRANSMITTER           0x00004
  52 #define REG_STATE_NACKED                0x00008
  53 #define REG_STATE_BUSHOLD               0x00010
  54 #define REG_STATE_STATE__MASK           0x000e0
  55 #define REG_STATE_STATE_IDLE            0x00000
  56 #define REG_STATE_STATE_WAIT            0x00020
  57 #define REG_STATE_STATE_START           0x00040
  58 #define REG_STATE_STATE_ADDR            0x00060
  59 #define REG_STATE_STATE_ADDRACK         0x00080
  60 #define REG_STATE_STATE_DATA            0x000a0
  61 #define REG_STATE_STATE_DATAACK         0x000c0
  62
  63 #define REG_STATUS              0x0c
  64 #define REG_STATUS_PSTART               0x00001
  65 #define REG_STATUS_PSTOP                0x00002
  66 #define REG_STATUS_PACK                 0x00004
  67 #define REG_STATUS_PNACK                0x00008
  68 #define REG_STATUS_PCONT                0x00010
  69 #define REG_STATUS_PABORT               0x00020
  70 #define REG_STATUS_TXC                  0x00040
  71 #define REG_STATUS_TXBL                 0x00080
  72 #define REG_STATUS_RXDATAV              0x00100
  73
  74 #define REG_CLKDIV              0x10
  75 #define REG_CLKDIV_DIV__MASK            0x001ff
  76 #define REG_CLKDIV_DIV(div)             MASK_VAL(REG_CLKDIV_DIV__MASK, (div))
  77
  78 #define REG_SADDR               0x14
  79 #define REG_SADDRMASK           0x18
  80 #define REG_RXDATA              0x1c
  81 #define REG_RXDATAP             0x20
  82 #define REG_TXDATA              0x24
  83 #define REG_IF                  0x28
  84 #define REG_IF_START                    0x00001
  85 #define REG_IF_RSTART                   0x00002
  86 #define REG_IF_ADDR                     0x00004
  87 #define REG_IF_TXC                      0x00008
  88 #define REG_IF_TXBL                     0x00010
  89 #define REG_IF_RXDATAV                  0x00020
  90 #define REG_IF_ACK                      0x00040
  91 #define REG_IF_NACK                     0x00080
  92 #define REG_IF_MSTOP                    0x00100
  93 #define REG_IF_ARBLOST                  0x00200
  94 #define REG_IF_BUSERR                   0x00400
  95 #define REG_IF_BUSHOLD                  0x00800
  96 #define REG_IF_TXOF                     0x01000
  97 #define REG_IF_RXUF                     0x02000
  98 #define REG_IF_BITO                     0x04000
  99 #define REG_IF_CLTO                     0x08000
 100 #define REG_IF_SSTOP                    0x10000
 101
 102 #define REG_IFS                 0x2c
 103 #define REG_IFC                 0x30
 104 #define REG_IFC__MASK                   0x1ffcf
 105
 106 #define REG_IEN                 0x34
 107
 108 #define REG_ROUTE               0x38
 109 #define REG_ROUTE_SDAPEN                0x00001
 110 #define REG_ROUTE_SCLPEN                0x00002
 111 #define REG_ROUTE_LOCATION__MASK        0x00700
 112 #define REG_ROUTE_LOCATION(n)           MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
 113
 114 struct efm32_i2c_ddata {
 115         struct i2c_adapter adapter;
 116
 117         struct clk *clk;
 118         void __iomem *base;
 119         unsigned int irq;
 120         u8 location;
 121         unsigned long frequency;
 122
 123         /* transfer data */
 124         struct completion done;
 125         struct i2c_msg *msgs;
 126         size_t num_msgs;
 127         size_t current_word, current_msg;
 128         int retval;
 129 };
 130
 131 static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset)
 132 {
 133         return readl(ddata->base + offset);
 134 }
 135
 136 static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata,
 137                 unsigned offset, u32 value)
 138 {
 139         writel(value, ddata->base + offset);
 140 }
 141
 142 static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata)
 143 {
 144         struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
 145
 146         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START);
 147         efm32_i2c_write32(ddata, REG_TXDATA, cur_msg->addr << 1 |
 148                         (cur_msg->flags & I2C_M_RD ? 1 : 0));
 149 }
 150
 151 static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata)
 152 {
 153         struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
 154
 155         if (ddata->current_word >= cur_msg->len) {
 156                 /* cur_msg completely transferred */
 157                 ddata->current_word = 0;
 158                 ddata->current_msg += 1;
 159
 160                 if (ddata->current_msg >= ddata->num_msgs) {
 161                         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
 162                         complete(&ddata->done);
 163                 } else {
 164                         efm32_i2c_send_next_msg(ddata);
 165                 }
 166         } else {
 167                 efm32_i2c_write32(ddata, REG_TXDATA,
 168                                 cur_msg->buf[ddata->current_word++]);
 169         }
 170 }
 171
 172 static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata)
 173 {
 174         struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
 175
 176         cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA);
 177         ddata->current_word += 1;
 178         if (ddata->current_word >= cur_msg->len) {
 179                 /* cur_msg completely transferred */
 180                 ddata->current_word = 0;
 181                 ddata->current_msg += 1;
 182
 183                 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK);
 184
 185                 if (ddata->current_msg >= ddata->num_msgs) {
 186                         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
 187                         complete(&ddata->done);
 188                 } else {
 189                         efm32_i2c_send_next_msg(ddata);
 190                 }
 191         } else {
 192                 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK);
 193         }
 194 }
 195
 196 static irqreturn_t efm32_i2c_irq(int irq, void *dev_id)
 197 {
 198         struct efm32_i2c_ddata *ddata = dev_id;
 199         struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
 200         u32 irqflag = efm32_i2c_read32(ddata, REG_IF);
 201         u32 state = efm32_i2c_read32(ddata, REG_STATE);
 202
 203         efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK);
 204
 205         switch (state & REG_STATE_STATE__MASK) {
 206         case REG_STATE_STATE_IDLE:
 207                 /* arbitration lost? */
 208                 ddata->retval = -EAGAIN;
 209                 complete(&ddata->done);
 210                 break;
 211         case REG_STATE_STATE_WAIT:
 212                 /*
 213                  * huh, this shouldn't happen.
 214                  * Reset hardware state and get out
 215                  */
 216                 ddata->retval = -EIO;
 217                 efm32_i2c_write32(ddata, REG_CMD,
 218                                 REG_CMD_STOP | REG_CMD_ABORT |
 219                                 REG_CMD_CLEARTX | REG_CMD_CLEARPC);
 220                 complete(&ddata->done);
 221                 break;
 222         case REG_STATE_STATE_START:
 223                 /* "caller" is expected to send an address */
 224                 break;
 225         case REG_STATE_STATE_ADDR:
 226                 /* wait for Ack or NAck of slave */
 227                 break;
 228         case REG_STATE_STATE_ADDRACK:
 229                 if (state & REG_STATE_NACKED) {
 230                         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
 231                         ddata->retval = -ENXIO;
 232                         complete(&ddata->done);
 233                 } else if (cur_msg->flags & I2C_M_RD) {
 234                         /* wait for slave to send first data byte */
 235                 } else {
 236                         efm32_i2c_send_next_byte(ddata);
 237                 }
 238                 break;
 239         case REG_STATE_STATE_DATA:
 240                 if (cur_msg->flags & I2C_M_RD) {
 241                         efm32_i2c_recv_next_byte(ddata);
 242                 } else {
 243                         /* wait for Ack or Nack of slave */
 244                 }
 245                 break;
 246         case REG_STATE_STATE_DATAACK:
 247                 if (state & REG_STATE_NACKED) {
 248                         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
 249                         complete(&ddata->done);
 250                 } else {
 251                         efm32_i2c_send_next_byte(ddata);
 252                 }
 253         }
 254
 255         return IRQ_HANDLED;
 256 }
 257
 258 static int efm32_i2c_master_xfer(struct i2c_adapter *adap,
 259                 struct i2c_msg *msgs, int num)
 260 {
 261         struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap);
 262         int ret;
 263
 264         if (ddata->msgs)
 265                 return -EBUSY;
 266
 267         ddata->msgs = msgs;
 268         ddata->num_msgs = num;
 269         ddata->current_word = 0;
 270         ddata->current_msg = 0;
 271         ddata->retval = -EIO;
 272
 273         reinit_completion(&ddata->done);
 274
 275         dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n",
 276                         efm32_i2c_read32(ddata, REG_STATE),
 277                         efm32_i2c_read32(ddata, REG_STATUS));
 278
 279         efm32_i2c_send_next_msg(ddata);
 280
 281         wait_for_completion(&ddata->done);
 282
 283         if (ddata->current_msg >= ddata->num_msgs)
 284                 ret = ddata->num_msgs;
 285         else
 286                 ret = ddata->retval;
 287
 288         return ret;
 289 }
 290
 291 static u32 efm32_i2c_functionality(struct i2c_adapter *adap)
 292 {
 293         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 294 }
 295
 296 static const struct i2c_algorithm efm32_i2c_algo = {
 297         .master_xfer = efm32_i2c_master_xfer,
 298         .functionality = efm32_i2c_functionality,
 299 };
 300
 301 static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata)
 302 {
 303         u32 reg = efm32_i2c_read32(ddata, REG_ROUTE);
 304
 305         return (reg & REG_ROUTE_LOCATION__MASK) >>
 306                 __ffs(REG_ROUTE_LOCATION__MASK);
 307 }
 308
 309 static int efm32_i2c_probe(struct platform_device *pdev)
 310 {
 311         struct efm32_i2c_ddata *ddata;
 312         struct resource *res;
 313         unsigned long rate;
 314         struct device_node *np = pdev->dev.of_node;
 315         u32 location, frequency;
 316         int ret;
 317         u32 clkdiv;
 318
 319         if (!np)
 320                 return -EINVAL;
 321
 322         ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
 323         if (!ddata)
 324                 return -ENOMEM;
 325         platform_set_drvdata(pdev, ddata);
 326
 327         init_completion(&ddata->done);
 328         strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name));
 329         ddata->adapter.owner = THIS_MODULE;
 330         ddata->adapter.algo = &efm32_i2c_algo;
 331         ddata->adapter.dev.parent = &pdev->dev;
 332         ddata->adapter.dev.of_node = pdev->dev.of_node;
 333         i2c_set_adapdata(&ddata->adapter, ddata);
 334
 335         ddata->clk = devm_clk_get(&pdev->dev, NULL);
 336         if (IS_ERR(ddata->clk)) {
 337                 ret = PTR_ERR(ddata->clk);
 338                 dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
 339                 return ret;
 340         }
 341
 342         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 343         if (!res) {
 344                 dev_err(&pdev->dev, "failed to determine base address\n");
 345                 return -ENODEV;
 346         }
 347
 348         if (resource_size(res) < 0x42) {
 349                 dev_err(&pdev->dev, "memory resource too small\n");
 350                 return -EINVAL;
 351         }
 352
 353         ddata->base = devm_ioremap_resource(&pdev->dev, res);
 354         if (IS_ERR(ddata->base))
 355                 return PTR_ERR(ddata->base);
 356
 357         ret = platform_get_irq(pdev, 0);
 358         if (ret <= 0) {
 359                 dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
 360                 if (!ret)
 361                         ret = -EINVAL;
 362                 return ret;
 363         }
 364
 365         ddata->irq = ret;
 366
 367         ret = clk_prepare_enable(ddata->clk);
 368         if (ret < 0) {
 369                 dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
 370                 return ret;
 371         }
 372
 373
 374         ret = of_property_read_u32(np, "energymicro,location", &location);
 375
 376         if (ret)
 377                 /* fall back to wrongly namespaced property */
 378                 ret = of_property_read_u32(np, "efm32,location", &location);
 379
 380         if (!ret) {
 381                 dev_dbg(&pdev->dev, "using location %u\n", location);
 382         } else {
 383                 /* default to location configured in hardware */
 384                 location = efm32_i2c_get_configured_location(ddata);
 385
 386                 dev_info(&pdev->dev, "fall back to location %u\n", location);
 387         }
 388
 389         ddata->location = location;
 390
 391         ret = of_property_read_u32(np, "clock-frequency", &frequency);
 392         if (!ret) {
 393                 dev_dbg(&pdev->dev, "using frequency %u\n", frequency);
 394         } else {
 395                 frequency = 100000;
 396                 dev_info(&pdev->dev, "defaulting to 100 kHz\n");
 397         }
 398         ddata->frequency = frequency;
 399
 400         rate = clk_get_rate(ddata->clk);
 401         if (!rate) {
 402                 dev_err(&pdev->dev, "there is no input clock available\n");
 403                 ret = -EINVAL;
 404                 goto err_disable_clk;
 405         }
 406         clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1;
 407         if (clkdiv >= 0x200) {
 408                 dev_err(&pdev->dev,
 409                                 "input clock too fast (%lu) to divide down to bus freq (%lu)",
 410                                 rate, ddata->frequency);
 411                 ret = -EINVAL;
 412                 goto err_disable_clk;
 413         }
 414
 415         dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n",
 416                         rate, ddata->frequency, (unsigned long)clkdiv);
 417         efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv));
 418
 419         efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN |
 420                         REG_ROUTE_SCLPEN |
 421                         REG_ROUTE_LOCATION(ddata->location));
 422
 423         efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN |
 424                         REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO);
 425
 426         efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK);
 427         efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK
 428                         | REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV);
 429
 430         /* to make bus idle */
 431         efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT);
 432
 433         ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata);
 434         if (ret < 0) {
 435                 dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
 436                 goto err_disable_clk;
 437         }
 438
 439         ret = i2c_add_adapter(&ddata->adapter);
 440         if (ret) {
 441                 dev_err(&pdev->dev, "failed to add i2c adapter (%d)\n", ret);
 442                 free_irq(ddata->irq, ddata);
 443
 444 err_disable_clk:
 445                 clk_disable_unprepare(ddata->clk);
 446         }
 447         return ret;
 448 }
 449
 450 static int efm32_i2c_remove(struct platform_device *pdev)
 451 {
 452         struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev);
 453
 454         i2c_del_adapter(&ddata->adapter);
 455         free_irq(ddata->irq, ddata);
 456         clk_disable_unprepare(ddata->clk);
 457
 458         return 0;
 459 }
 460
 461 static const struct of_device_id efm32_i2c_dt_ids[] = {
 462         {
 463                 .compatible = "energymicro,efm32-i2c",
 464         }, {
 465                 /* sentinel */
 466         }
 467 };
 468 MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids);
 469
 470 static struct platform_driver efm32_i2c_driver = {
 471         .probe = efm32_i2c_probe,
 472         .remove = efm32_i2c_remove,
 473
 474         .driver = {
 475                 .name = DRIVER_NAME,
 476                 .of_match_table = efm32_i2c_dt_ids,
 477         },
 478 };
 479 module_platform_driver(efm32_i2c_driver);
 480
 481 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 482 MODULE_DESCRIPTION("EFM32 i2c driver");
 483 MODULE_LICENSE("GPL v2");
 484 MODULE_ALIAS("platform:" DRIVER_NAME);