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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-i801.c
blobf78069cd8d5381b63406ab4c435332a3a40cbdc6
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 *
68 * Features supported by this driver:
69 * Software PEC no
70 * Hardware PEC yes
71 * Block buffer yes
72 * Block process call transaction no
73 * I2C block read transaction yes (doesn't use the block buffer)
74 * Slave mode no
75 * Interrupt processing yes
76 *
77 * See the file Documentation/i2c/busses/i2c-i801 for details.
78 */
79
80 #include <linux/interrupt.h>
81 #include <linux/module.h>
82 #include <linux/pci.h>
83 #include <linux/kernel.h>
84 #include <linux/stddef.h>
85 #include <linux/delay.h>
86 #include <linux/ioport.h>
87 #include <linux/init.h>
88 #include <linux/i2c.h>
89 #include <linux/acpi.h>
90 #include <linux/io.h>
91 #include <linux/dmi.h>
92 #include <linux/slab.h>
93 #include <linux/wait.h>
94 #include <linux/err.h>
95 #include <linux/platform_device.h>
96 #include <linux/platform_data/itco_wdt.h>
97
98 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
99 defined CONFIG_DMI
100 #include <linux/gpio.h>
101 #include <linux/i2c-mux-gpio.h>
102 #endif
103
104 /* I801 SMBus address offsets */
105 #define SMBHSTSTS(p) (0 + (p)->smba)
106 #define SMBHSTCNT(p) (2 + (p)->smba)
107 #define SMBHSTCMD(p) (3 + (p)->smba)
108 #define SMBHSTADD(p) (4 + (p)->smba)
109 #define SMBHSTDAT0(p) (5 + (p)->smba)
110 #define SMBHSTDAT1(p) (6 + (p)->smba)
111 #define SMBBLKDAT(p) (7 + (p)->smba)
112 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
113 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
114 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
115
116 /* PCI Address Constants */
117 #define SMBBAR 4
118 #define SMBPCICTL 0x004
119 #define SMBPCISTS 0x006
120 #define SMBHSTCFG 0x040
121 #define TCOBASE 0x050
122 #define TCOCTL 0x054
123
124 #define ACPIBASE 0x040
125 #define ACPIBASE_SMI_OFF 0x030
126 #define ACPICTRL 0x044
127 #define ACPICTRL_EN 0x080
128
129 #define SBREG_BAR 0x10
130 #define SBREG_SMBCTRL 0xc6000c
131 #define SBREG_SMBCTRL_DNV 0xcf000c
132
133 /* Host status bits for SMBPCISTS */
134 #define SMBPCISTS_INTS 0x08
135
136 /* Control bits for SMBPCICTL */
137 #define SMBPCICTL_INTDIS 0x0400
138
139 /* Host configuration bits for SMBHSTCFG */
140 #define SMBHSTCFG_HST_EN 1
141 #define SMBHSTCFG_SMB_SMI_EN 2
142 #define SMBHSTCFG_I2C_EN 4
143
144 /* TCO configuration bits for TCOCTL */
145 #define TCOCTL_EN 0x0100
146
147 /* Auxiliary control register bits, ICH4+ only */
148 #define SMBAUXCTL_CRC 1
149 #define SMBAUXCTL_E32B 2
150
151 /* Other settings */
152 #define MAX_RETRIES 400
153
154 /* I801 command constants */
155 #define I801_QUICK 0x00
156 #define I801_BYTE 0x04
157 #define I801_BYTE_DATA 0x08
158 #define I801_WORD_DATA 0x0C
159 #define I801_PROC_CALL 0x10 /* unimplemented */
160 #define I801_BLOCK_DATA 0x14
161 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
162
163 /* I801 Host Control register bits */
164 #define SMBHSTCNT_INTREN 0x01
165 #define SMBHSTCNT_KILL 0x02
166 #define SMBHSTCNT_LAST_BYTE 0x20
167 #define SMBHSTCNT_START 0x40
168 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
169
170 /* I801 Hosts Status register bits */
171 #define SMBHSTSTS_BYTE_DONE 0x80
172 #define SMBHSTSTS_INUSE_STS 0x40
173 #define SMBHSTSTS_SMBALERT_STS 0x20
174 #define SMBHSTSTS_FAILED 0x10
175 #define SMBHSTSTS_BUS_ERR 0x08
176 #define SMBHSTSTS_DEV_ERR 0x04
177 #define SMBHSTSTS_INTR 0x02
178 #define SMBHSTSTS_HOST_BUSY 0x01
179
180 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
181 SMBHSTSTS_DEV_ERR)
182
183 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
184 STATUS_ERROR_FLAGS)
185
186 /* Older devices have their ID defined in <linux/pci_ids.h> */
187 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
188 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
189 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
191 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
194 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
195 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
196 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
197 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
198 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
199 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
200 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
201 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
202 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
203 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
205 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
206 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
207 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
208 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
209 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
211 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
213 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
214
215 struct i801_mux_config {
216 char *gpio_chip;
217 unsigned values[3];
218 int n_values;
219 unsigned classes[3];
220 unsigned gpios[2]; /* Relative to gpio_chip->base */
221 int n_gpios;
222 };
223
224 struct i801_priv {
225 struct i2c_adapter adapter;
226 unsigned long smba;
227 unsigned char original_hstcfg;
228 struct pci_dev *pci_dev;
229 unsigned int features;
230
231 /* isr processing */
232 wait_queue_head_t waitq;
233 u8 status;
234
235 /* Command state used by isr for byte-by-byte block transactions */
236 u8 cmd;
237 bool is_read;
238 int count;
239 int len;
240 u8 *data;
241
242 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
243 defined CONFIG_DMI
244 const struct i801_mux_config *mux_drvdata;
245 struct platform_device *mux_pdev;
246 #endif
247 struct platform_device *tco_pdev;
248
249 /*
250 * If set to true the host controller registers are reserved for
251 * ACPI AML use. Protected by acpi_lock.
252 */
253 bool acpi_reserved;
254 struct mutex acpi_lock;
255 };
256
257 #define FEATURE_SMBUS_PEC (1 << 0)
258 #define FEATURE_BLOCK_BUFFER (1 << 1)
259 #define FEATURE_BLOCK_PROC (1 << 2)
260 #define FEATURE_I2C_BLOCK_READ (1 << 3)
261 #define FEATURE_IRQ (1 << 4)
262 /* Not really a feature, but it's convenient to handle it as such */
263 #define FEATURE_IDF (1 << 15)
264 #define FEATURE_TCO (1 << 16)
265
266 static const char *i801_feature_names[] = {
267 "SMBus PEC",
268 "Block buffer",
269 "Block process call",
270 "I2C block read",
271 "Interrupt",
272 };
273
274 static unsigned int disable_features;
275 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
276 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
277 "\t\t 0x01 disable SMBus PEC\n"
278 "\t\t 0x02 disable the block buffer\n"
279 "\t\t 0x08 disable the I2C block read functionality\n"
280 "\t\t 0x10 don't use interrupts ");
281
282 /* Make sure the SMBus host is ready to start transmitting.
283 Return 0 if it is, -EBUSY if it is not. */
284 static int i801_check_pre(struct i801_priv *priv)
285 {
286 int status;
287
288 status = inb_p(SMBHSTSTS(priv));
289 if (status & SMBHSTSTS_HOST_BUSY) {
290 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
291 return -EBUSY;
292 }
293
294 status &= STATUS_FLAGS;
295 if (status) {
296 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
297 status);
298 outb_p(status, SMBHSTSTS(priv));
299 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
300 if (status) {
301 dev_err(&priv->pci_dev->dev,
302 "Failed clearing status flags (%02x)\n",
303 status);
304 return -EBUSY;
305 }
306 }
307
308 return 0;
309 }
310
311 /*
312 * Convert the status register to an error code, and clear it.
313 * Note that status only contains the bits we want to clear, not the
314 * actual register value.
315 */
316 static int i801_check_post(struct i801_priv *priv, int status)
317 {
318 int result = 0;
319
320 /*
321 * If the SMBus is still busy, we give up
322 * Note: This timeout condition only happens when using polling
323 * transactions. For interrupt operation, NAK/timeout is indicated by
324 * DEV_ERR.
325 */
326 if (unlikely(status < 0)) {
327 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
328 /* try to stop the current command */
329 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
330 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
331 SMBHSTCNT(priv));
332 usleep_range(1000, 2000);
333 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
334 SMBHSTCNT(priv));
335
336 /* Check if it worked */
337 status = inb_p(SMBHSTSTS(priv));
338 if ((status & SMBHSTSTS_HOST_BUSY) ||
339 !(status & SMBHSTSTS_FAILED))
340 dev_err(&priv->pci_dev->dev,
341 "Failed terminating the transaction\n");
342 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
343 return -ETIMEDOUT;
344 }
345
346 if (status & SMBHSTSTS_FAILED) {
347 result = -EIO;
348 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
349 }
350 if (status & SMBHSTSTS_DEV_ERR) {
351 result = -ENXIO;
352 dev_dbg(&priv->pci_dev->dev, "No response\n");
353 }
354 if (status & SMBHSTSTS_BUS_ERR) {
355 result = -EAGAIN;
356 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
357 }
358
359 /* Clear status flags except BYTE_DONE, to be cleared by caller */
360 outb_p(status, SMBHSTSTS(priv));
361
362 return result;
363 }
364
365 /* Wait for BUSY being cleared and either INTR or an error flag being set */
366 static int i801_wait_intr(struct i801_priv *priv)
367 {
368 int timeout = 0;
369 int status;
370
371 /* We will always wait for a fraction of a second! */
372 do {
373 usleep_range(250, 500);
374 status = inb_p(SMBHSTSTS(priv));
375 } while (((status & SMBHSTSTS_HOST_BUSY) ||
376 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
377 (timeout++ < MAX_RETRIES));
378
379 if (timeout > MAX_RETRIES) {
380 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
381 return -ETIMEDOUT;
382 }
383 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
384 }
385
386 /* Wait for either BYTE_DONE or an error flag being set */
387 static int i801_wait_byte_done(struct i801_priv *priv)
388 {
389 int timeout = 0;
390 int status;
391
392 /* We will always wait for a fraction of a second! */
393 do {
394 usleep_range(250, 500);
395 status = inb_p(SMBHSTSTS(priv));
396 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
397 (timeout++ < MAX_RETRIES));
398
399 if (timeout > MAX_RETRIES) {
400 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
401 return -ETIMEDOUT;
402 }
403 return status & STATUS_ERROR_FLAGS;
404 }
405
406 static int i801_transaction(struct i801_priv *priv, int xact)
407 {
408 int status;
409 int result;
410 const struct i2c_adapter *adap = &priv->adapter;
411
412 result = i801_check_pre(priv);
413 if (result < 0)
414 return result;
415
416 if (priv->features & FEATURE_IRQ) {
417 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
418 SMBHSTCNT(priv));
419 result = wait_event_timeout(priv->waitq,
420 (status = priv->status),
421 adap->timeout);
422 if (!result) {
423 status = -ETIMEDOUT;
424 dev_warn(&priv->pci_dev->dev,
425 "Timeout waiting for interrupt!\n");
426 }
427 priv->status = 0;
428 return i801_check_post(priv, status);
429 }
430
431 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
432 * SMBSCMD are passed in xact */
433 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
434
435 status = i801_wait_intr(priv);
436 return i801_check_post(priv, status);
437 }
438
439 static int i801_block_transaction_by_block(struct i801_priv *priv,
440 union i2c_smbus_data *data,
441 char read_write, int hwpec)
442 {
443 int i, len;
444 int status;
445
446 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
447
448 /* Use 32-byte buffer to process this transaction */
449 if (read_write == I2C_SMBUS_WRITE) {
450 len = data->block[0];
451 outb_p(len, SMBHSTDAT0(priv));
452 for (i = 0; i < len; i++)
453 outb_p(data->block[i+1], SMBBLKDAT(priv));
454 }
455
456 status = i801_transaction(priv, I801_BLOCK_DATA |
457 (hwpec ? SMBHSTCNT_PEC_EN : 0));
458 if (status)
459 return status;
460
461 if (read_write == I2C_SMBUS_READ) {
462 len = inb_p(SMBHSTDAT0(priv));
463 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
464 return -EPROTO;
465
466 data->block[0] = len;
467 for (i = 0; i < len; i++)
468 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
469 }
470 return 0;
471 }
472
473 static void i801_isr_byte_done(struct i801_priv *priv)
474 {
475 if (priv->is_read) {
476 /* For SMBus block reads, length is received with first byte */
477 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
478 (priv->count == 0)) {
479 priv->len = inb_p(SMBHSTDAT0(priv));
480 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
481 dev_err(&priv->pci_dev->dev,
482 "Illegal SMBus block read size %d\n",
483 priv->len);
484 /* FIXME: Recover */
485 priv->len = I2C_SMBUS_BLOCK_MAX;
486 } else {
487 dev_dbg(&priv->pci_dev->dev,
488 "SMBus block read size is %d\n",
489 priv->len);
490 }
491 priv->data[-1] = priv->len;
492 }
493
494 /* Read next byte */
495 if (priv->count < priv->len)
496 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
497 else
498 dev_dbg(&priv->pci_dev->dev,
499 "Discarding extra byte on block read\n");
500
501 /* Set LAST_BYTE for last byte of read transaction */
502 if (priv->count == priv->len - 1)
503 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
504 SMBHSTCNT(priv));
505 } else if (priv->count < priv->len - 1) {
506 /* Write next byte, except for IRQ after last byte */
507 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
508 }
509
510 /* Clear BYTE_DONE to continue with next byte */
511 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
512 }
513
514 /*
515 * There are two kinds of interrupts:
516 *
517 * 1) i801 signals transaction completion with one of these interrupts:
518 * INTR - Success
519 * DEV_ERR - Invalid command, NAK or communication timeout
520 * BUS_ERR - SMI# transaction collision
521 * FAILED - transaction was canceled due to a KILL request
522 * When any of these occur, update ->status and wake up the waitq.
523 * ->status must be cleared before kicking off the next transaction.
524 *
525 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
526 * occurs for each byte of a byte-by-byte to prepare the next byte.
527 */
528 static irqreturn_t i801_isr(int irq, void *dev_id)
529 {
530 struct i801_priv *priv = dev_id;
531 u16 pcists;
532 u8 status;
533
534 /* Confirm this is our interrupt */
535 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
536 if (!(pcists & SMBPCISTS_INTS))
537 return IRQ_NONE;
538
539 status = inb_p(SMBHSTSTS(priv));
540 if (status & SMBHSTSTS_BYTE_DONE)
541 i801_isr_byte_done(priv);
542
543 /*
544 * Clear irq sources and report transaction result.
545 * ->status must be cleared before the next transaction is started.
546 */
547 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
548 if (status) {
549 outb_p(status, SMBHSTSTS(priv));
550 priv->status |= status;
551 wake_up(&priv->waitq);
552 }
553
554 return IRQ_HANDLED;
555 }
556
557 /*
558 * For "byte-by-byte" block transactions:
559 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
560 * I2C read uses cmd=I801_I2C_BLOCK_DATA
561 */
562 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
563 union i2c_smbus_data *data,
564 char read_write, int command,
565 int hwpec)
566 {
567 int i, len;
568 int smbcmd;
569 int status;
570 int result;
571 const struct i2c_adapter *adap = &priv->adapter;
572
573 result = i801_check_pre(priv);
574 if (result < 0)
575 return result;
576
577 len = data->block[0];
578
579 if (read_write == I2C_SMBUS_WRITE) {
580 outb_p(len, SMBHSTDAT0(priv));
581 outb_p(data->block[1], SMBBLKDAT(priv));
582 }
583
584 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
585 read_write == I2C_SMBUS_READ)
586 smbcmd = I801_I2C_BLOCK_DATA;
587 else
588 smbcmd = I801_BLOCK_DATA;
589
590 if (priv->features & FEATURE_IRQ) {
591 priv->is_read = (read_write == I2C_SMBUS_READ);
592 if (len == 1 && priv->is_read)
593 smbcmd |= SMBHSTCNT_LAST_BYTE;
594 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
595 priv->len = len;
596 priv->count = 0;
597 priv->data = &data->block[1];
598
599 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
600 result = wait_event_timeout(priv->waitq,
601 (status = priv->status),
602 adap->timeout);
603 if (!result) {
604 status = -ETIMEDOUT;
605 dev_warn(&priv->pci_dev->dev,
606 "Timeout waiting for interrupt!\n");
607 }
608 priv->status = 0;
609 return i801_check_post(priv, status);
610 }
611
612 for (i = 1; i <= len; i++) {
613 if (i == len && read_write == I2C_SMBUS_READ)
614 smbcmd |= SMBHSTCNT_LAST_BYTE;
615 outb_p(smbcmd, SMBHSTCNT(priv));
616
617 if (i == 1)
618 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
619 SMBHSTCNT(priv));
620
621 status = i801_wait_byte_done(priv);
622 if (status)
623 goto exit;
624
625 if (i == 1 && read_write == I2C_SMBUS_READ
626 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
627 len = inb_p(SMBHSTDAT0(priv));
628 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
629 dev_err(&priv->pci_dev->dev,
630 "Illegal SMBus block read size %d\n",
631 len);
632 /* Recover */
633 while (inb_p(SMBHSTSTS(priv)) &
634 SMBHSTSTS_HOST_BUSY)
635 outb_p(SMBHSTSTS_BYTE_DONE,
636 SMBHSTSTS(priv));
637 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
638 return -EPROTO;
639 }
640 data->block[0] = len;
641 }
642
643 /* Retrieve/store value in SMBBLKDAT */
644 if (read_write == I2C_SMBUS_READ)
645 data->block[i] = inb_p(SMBBLKDAT(priv));
646 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
647 outb_p(data->block[i+1], SMBBLKDAT(priv));
648
649 /* signals SMBBLKDAT ready */
650 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
651 }
652
653 status = i801_wait_intr(priv);
654 exit:
655 return i801_check_post(priv, status);
656 }
657
658 static int i801_set_block_buffer_mode(struct i801_priv *priv)
659 {
660 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
661 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
662 return -EIO;
663 return 0;
664 }
665
666 /* Block transaction function */
667 static int i801_block_transaction(struct i801_priv *priv,
668 union i2c_smbus_data *data, char read_write,
669 int command, int hwpec)
670 {
671 int result = 0;
672 unsigned char hostc;
673
674 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
675 if (read_write == I2C_SMBUS_WRITE) {
676 /* set I2C_EN bit in configuration register */
677 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
678 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
679 hostc | SMBHSTCFG_I2C_EN);
680 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
681 dev_err(&priv->pci_dev->dev,
682 "I2C block read is unsupported!\n");
683 return -EOPNOTSUPP;
684 }
685 }
686
687 if (read_write == I2C_SMBUS_WRITE
688 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
689 if (data->block[0] < 1)
690 data->block[0] = 1;
691 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
692 data->block[0] = I2C_SMBUS_BLOCK_MAX;
693 } else {
694 data->block[0] = 32; /* max for SMBus block reads */
695 }
696
697 /* Experience has shown that the block buffer can only be used for
698 SMBus (not I2C) block transactions, even though the datasheet
699 doesn't mention this limitation. */
700 if ((priv->features & FEATURE_BLOCK_BUFFER)
701 && command != I2C_SMBUS_I2C_BLOCK_DATA
702 && i801_set_block_buffer_mode(priv) == 0)
703 result = i801_block_transaction_by_block(priv, data,
704 read_write, hwpec);
705 else
706 result = i801_block_transaction_byte_by_byte(priv, data,
707 read_write,
708 command, hwpec);
709
710 if (command == I2C_SMBUS_I2C_BLOCK_DATA
711 && read_write == I2C_SMBUS_WRITE) {
712 /* restore saved configuration register value */
713 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
714 }
715 return result;
716 }
717
718 /* Return negative errno on error. */
719 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
720 unsigned short flags, char read_write, u8 command,
721 int size, union i2c_smbus_data *data)
722 {
723 int hwpec;
724 int block = 0;
725 int ret = 0, xact = 0;
726 struct i801_priv *priv = i2c_get_adapdata(adap);
727
728 mutex_lock(&priv->acpi_lock);
729 if (priv->acpi_reserved) {
730 mutex_unlock(&priv->acpi_lock);
731 return -EBUSY;
732 }
733
734 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
735 && size != I2C_SMBUS_QUICK
736 && size != I2C_SMBUS_I2C_BLOCK_DATA;
737
738 switch (size) {
739 case I2C_SMBUS_QUICK:
740 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
741 SMBHSTADD(priv));
742 xact = I801_QUICK;
743 break;
744 case I2C_SMBUS_BYTE:
745 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
746 SMBHSTADD(priv));
747 if (read_write == I2C_SMBUS_WRITE)
748 outb_p(command, SMBHSTCMD(priv));
749 xact = I801_BYTE;
750 break;
751 case I2C_SMBUS_BYTE_DATA:
752 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
753 SMBHSTADD(priv));
754 outb_p(command, SMBHSTCMD(priv));
755 if (read_write == I2C_SMBUS_WRITE)
756 outb_p(data->byte, SMBHSTDAT0(priv));
757 xact = I801_BYTE_DATA;
758 break;
759 case I2C_SMBUS_WORD_DATA:
760 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
761 SMBHSTADD(priv));
762 outb_p(command, SMBHSTCMD(priv));
763 if (read_write == I2C_SMBUS_WRITE) {
764 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
765 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
766 }
767 xact = I801_WORD_DATA;
768 break;
769 case I2C_SMBUS_BLOCK_DATA:
770 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
771 SMBHSTADD(priv));
772 outb_p(command, SMBHSTCMD(priv));
773 block = 1;
774 break;
775 case I2C_SMBUS_I2C_BLOCK_DATA:
776 /* NB: page 240 of ICH5 datasheet shows that the R/#W
777 * bit should be cleared here, even when reading */
778 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
779 if (read_write == I2C_SMBUS_READ) {
780 /* NB: page 240 of ICH5 datasheet also shows
781 * that DATA1 is the cmd field when reading */
782 outb_p(command, SMBHSTDAT1(priv));
783 } else
784 outb_p(command, SMBHSTCMD(priv));
785 block = 1;
786 break;
787 default:
788 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
789 size);
790 ret = -EOPNOTSUPP;
791 goto out;
792 }
793
794 if (hwpec) /* enable/disable hardware PEC */
795 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
796 else
797 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
798 SMBAUXCTL(priv));
799
800 if (block)
801 ret = i801_block_transaction(priv, data, read_write, size,
802 hwpec);
803 else
804 ret = i801_transaction(priv, xact);
805
806 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
807 time, so we forcibly disable it after every transaction. Turn off
808 E32B for the same reason. */
809 if (hwpec || block)
810 outb_p(inb_p(SMBAUXCTL(priv)) &
811 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
812
813 if (block)
814 goto out;
815 if (ret)
816 goto out;
817 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
818 goto out;
819
820 switch (xact & 0x7f) {
821 case I801_BYTE: /* Result put in SMBHSTDAT0 */
822 case I801_BYTE_DATA:
823 data->byte = inb_p(SMBHSTDAT0(priv));
824 break;
825 case I801_WORD_DATA:
826 data->word = inb_p(SMBHSTDAT0(priv)) +
827 (inb_p(SMBHSTDAT1(priv)) << 8);
828 break;
829 }
830
831 out:
832 mutex_unlock(&priv->acpi_lock);
833 return ret;
834 }
835
836
837 static u32 i801_func(struct i2c_adapter *adapter)
838 {
839 struct i801_priv *priv = i2c_get_adapdata(adapter);
840
841 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
842 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
843 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
844 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
845 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
846 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
847 }
848
849 static const struct i2c_algorithm smbus_algorithm = {
850 .smbus_xfer = i801_access,
851 .functionality = i801_func,
852 };
853
854 static const struct pci_device_id i801_ids[] = {
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
868 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
869 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
870 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
871 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
872 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
873 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
874 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
875 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
876 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
878 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
879 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
880 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
881 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
882 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
883 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
884 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
885 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
886 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
887 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
888 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
889 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
890 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
891 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
892 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
893 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
894 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
895 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
896 { 0, }
897 };
898
899 MODULE_DEVICE_TABLE(pci, i801_ids);
900
901 #if defined CONFIG_X86 && defined CONFIG_DMI
902 static unsigned char apanel_addr;
903
904 /* Scan the system ROM for the signature "FJKEYINF" */
905 static __init const void __iomem *bios_signature(const void __iomem *bios)
906 {
907 ssize_t offset;
908 const unsigned char signature[] = "FJKEYINF";
909
910 for (offset = 0; offset < 0x10000; offset += 0x10) {
911 if (check_signature(bios + offset, signature,
912 sizeof(signature)-1))
913 return bios + offset;
914 }
915 return NULL;
916 }
917
918 static void __init input_apanel_init(void)
919 {
920 void __iomem *bios;
921 const void __iomem *p;
922
923 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
924 p = bios_signature(bios);
925 if (p) {
926 /* just use the first address */
927 apanel_addr = readb(p + 8 + 3) >> 1;
928 }
929 iounmap(bios);
930 }
931
932 struct dmi_onboard_device_info {
933 const char *name;
934 u8 type;
935 unsigned short i2c_addr;
936 const char *i2c_type;
937 };
938
939 static const struct dmi_onboard_device_info dmi_devices[] = {
940 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
941 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
942 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
943 };
944
945 static void dmi_check_onboard_device(u8 type, const char *name,
946 struct i2c_adapter *adap)
947 {
948 int i;
949 struct i2c_board_info info;
950
951 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
952 /* & ~0x80, ignore enabled/disabled bit */
953 if ((type & ~0x80) != dmi_devices[i].type)
954 continue;
955 if (strcasecmp(name, dmi_devices[i].name))
956 continue;
957
958 memset(&info, 0, sizeof(struct i2c_board_info));
959 info.addr = dmi_devices[i].i2c_addr;
960 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
961 i2c_new_device(adap, &info);
962 break;
963 }
964 }
965
966 /* We use our own function to check for onboard devices instead of
967 dmi_find_device() as some buggy BIOS's have the devices we are interested
968 in marked as disabled */
969 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
970 {
971 int i, count;
972
973 if (dm->type != 10)
974 return;
975
976 count = (dm->length - sizeof(struct dmi_header)) / 2;
977 for (i = 0; i < count; i++) {
978 const u8 *d = (char *)(dm + 1) + (i * 2);
979 const char *name = ((char *) dm) + dm->length;
980 u8 type = d[0];
981 u8 s = d[1];
982
983 if (!s)
984 continue;
985 s--;
986 while (s > 0 && name[0]) {
987 name += strlen(name) + 1;
988 s--;
989 }
990 if (name[0] == 0) /* Bogus string reference */
991 continue;
992
993 dmi_check_onboard_device(type, name, adap);
994 }
995 }
996
997 /* Register optional slaves */
998 static void i801_probe_optional_slaves(struct i801_priv *priv)
999 {
1000 /* Only register slaves on main SMBus channel */
1001 if (priv->features & FEATURE_IDF)
1002 return;
1003
1004 if (apanel_addr) {
1005 struct i2c_board_info info;
1006
1007 memset(&info, 0, sizeof(struct i2c_board_info));
1008 info.addr = apanel_addr;
1009 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1010 i2c_new_device(&priv->adapter, &info);
1011 }
1012
1013 if (dmi_name_in_vendors("FUJITSU"))
1014 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1015 }
1016 #else
1017 static void __init input_apanel_init(void) {}
1018 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1019 #endif /* CONFIG_X86 && CONFIG_DMI */
1020
1021 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1022 defined CONFIG_DMI
1023 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1024 .gpio_chip = "gpio_ich",
1025 .values = { 0x02, 0x03 },
1026 .n_values = 2,
1027 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1028 .gpios = { 52, 53 },
1029 .n_gpios = 2,
1030 };
1031
1032 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1033 .gpio_chip = "gpio_ich",
1034 .values = { 0x02, 0x03, 0x01 },
1035 .n_values = 3,
1036 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1037 .gpios = { 52, 53 },
1038 .n_gpios = 2,
1039 };
1040
1041 static const struct dmi_system_id mux_dmi_table[] = {
1042 {
1043 .matches = {
1044 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1045 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1046 },
1047 .driver_data = &i801_mux_config_asus_z8_d12,
1048 },
1049 {
1050 .matches = {
1051 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1052 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1053 },
1054 .driver_data = &i801_mux_config_asus_z8_d12,
1055 },
1056 {
1057 .matches = {
1058 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1059 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1060 },
1061 .driver_data = &i801_mux_config_asus_z8_d12,
1062 },
1063 {
1064 .matches = {
1065 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1066 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1067 },
1068 .driver_data = &i801_mux_config_asus_z8_d12,
1069 },
1070 {
1071 .matches = {
1072 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1073 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1074 },
1075 .driver_data = &i801_mux_config_asus_z8_d12,
1076 },
1077 {
1078 .matches = {
1079 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1080 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1081 },
1082 .driver_data = &i801_mux_config_asus_z8_d12,
1083 },
1084 {
1085 .matches = {
1086 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1087 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1088 },
1089 .driver_data = &i801_mux_config_asus_z8_d18,
1090 },
1091 {
1092 .matches = {
1093 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1094 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1095 },
1096 .driver_data = &i801_mux_config_asus_z8_d18,
1097 },
1098 {
1099 .matches = {
1100 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1101 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1102 },
1103 .driver_data = &i801_mux_config_asus_z8_d12,
1104 },
1105 { }
1106 };
1107
1108 /* Setup multiplexing if needed */
1109 static int i801_add_mux(struct i801_priv *priv)
1110 {
1111 struct device *dev = &priv->adapter.dev;
1112 const struct i801_mux_config *mux_config;
1113 struct i2c_mux_gpio_platform_data gpio_data;
1114 int err;
1115
1116 if (!priv->mux_drvdata)
1117 return 0;
1118 mux_config = priv->mux_drvdata;
1119
1120 /* Prepare the platform data */
1121 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1122 gpio_data.parent = priv->adapter.nr;
1123 gpio_data.values = mux_config->values;
1124 gpio_data.n_values = mux_config->n_values;
1125 gpio_data.classes = mux_config->classes;
1126 gpio_data.gpio_chip = mux_config->gpio_chip;
1127 gpio_data.gpios = mux_config->gpios;
1128 gpio_data.n_gpios = mux_config->n_gpios;
1129 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1130
1131 /* Register the mux device */
1132 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1133 PLATFORM_DEVID_AUTO, &gpio_data,
1134 sizeof(struct i2c_mux_gpio_platform_data));
1135 if (IS_ERR(priv->mux_pdev)) {
1136 err = PTR_ERR(priv->mux_pdev);
1137 priv->mux_pdev = NULL;
1138 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1139 return err;
1140 }
1141
1142 return 0;
1143 }
1144
1145 static void i801_del_mux(struct i801_priv *priv)
1146 {
1147 if (priv->mux_pdev)
1148 platform_device_unregister(priv->mux_pdev);
1149 }
1150
1151 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1152 {
1153 const struct dmi_system_id *id;
1154 const struct i801_mux_config *mux_config;
1155 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1156 int i;
1157
1158 id = dmi_first_match(mux_dmi_table);
1159 if (id) {
1160 /* Remove branch classes from trunk */
1161 mux_config = id->driver_data;
1162 for (i = 0; i < mux_config->n_values; i++)
1163 class &= ~mux_config->classes[i];
1164
1165 /* Remember for later */
1166 priv->mux_drvdata = mux_config;
1167 }
1168
1169 return class;
1170 }
1171 #else
1172 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1173 static inline void i801_del_mux(struct i801_priv *priv) { }
1174
1175 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1176 {
1177 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1178 }
1179 #endif
1180
1181 static const struct itco_wdt_platform_data tco_platform_data = {
1182 .name = "Intel PCH",
1183 .version = 4,
1184 };
1185
1186 static DEFINE_SPINLOCK(p2sb_spinlock);
1187
1188 static void i801_add_tco(struct i801_priv *priv)
1189 {
1190 struct pci_dev *pci_dev = priv->pci_dev;
1191 struct resource tco_res[3], *res;
1192 struct platform_device *pdev;
1193 unsigned int devfn;
1194 u32 tco_base, tco_ctl;
1195 u32 base_addr, ctrl_val;
1196 u64 base64_addr;
1197
1198 if (!(priv->features & FEATURE_TCO))
1199 return;
1200
1201 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1202 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1203 if (!(tco_ctl & TCOCTL_EN))
1204 return;
1205
1206 memset(tco_res, 0, sizeof(tco_res));
1207
1208 res = &tco_res[ICH_RES_IO_TCO];
1209 res->start = tco_base & ~1;
1210 res->end = res->start + 32 - 1;
1211 res->flags = IORESOURCE_IO;
1212
1213 /*
1214 * Power Management registers.
1215 */
1216 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1217 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1218
1219 res = &tco_res[ICH_RES_IO_SMI];
1220 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1221 res->end = res->start + 3;
1222 res->flags = IORESOURCE_IO;
1223
1224 /*
1225 * Enable the ACPI I/O space.
1226 */
1227 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1228 ctrl_val |= ACPICTRL_EN;
1229 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1230
1231 /*
1232 * We must access the NO_REBOOT bit over the Primary to Sideband
1233 * bridge (P2SB). The BIOS prevents the P2SB device from being
1234 * enumerated by the PCI subsystem, so we need to unhide/hide it
1235 * to lookup the P2SB BAR.
1236 */
1237 spin_lock(&p2sb_spinlock);
1238
1239 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1240
1241 /* Unhide the P2SB device */
1242 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1243
1244 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1245 base64_addr = base_addr & 0xfffffff0;
1246
1247 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1248 base64_addr |= (u64)base_addr << 32;
1249
1250 /* Hide the P2SB device */
1251 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1252 spin_unlock(&p2sb_spinlock);
1253
1254 res = &tco_res[ICH_RES_MEM_OFF];
1255 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1256 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1257 else
1258 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1259
1260 res->end = res->start + 3;
1261 res->flags = IORESOURCE_MEM;
1262
1263 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1264 tco_res, 3, &tco_platform_data,
1265 sizeof(tco_platform_data));
1266 if (IS_ERR(pdev)) {
1267 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1268 return;
1269 }
1270
1271 priv->tco_pdev = pdev;
1272 }
1273
1274 #ifdef CONFIG_ACPI
1275 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1276 acpi_physical_address address)
1277 {
1278 return address >= priv->smba &&
1279 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1280 }
1281
1282 static acpi_status
1283 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1284 u64 *value, void *handler_context, void *region_context)
1285 {
1286 struct i801_priv *priv = handler_context;
1287 struct pci_dev *pdev = priv->pci_dev;
1288 acpi_status status;
1289
1290 /*
1291 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1292 * further access from the driver itself. This device is now owned
1293 * by the system firmware.
1294 */
1295 mutex_lock(&priv->acpi_lock);
1296
1297 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1298 priv->acpi_reserved = true;
1299
1300 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1301 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1302 }
1303
1304 if ((function & ACPI_IO_MASK) == ACPI_READ)
1305 status = acpi_os_read_port(address, (u32 *)value, bits);
1306 else
1307 status = acpi_os_write_port(address, (u32)*value, bits);
1308
1309 mutex_unlock(&priv->acpi_lock);
1310
1311 return status;
1312 }
1313
1314 static int i801_acpi_probe(struct i801_priv *priv)
1315 {
1316 struct acpi_device *adev;
1317 acpi_status status;
1318
1319 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1320 if (adev) {
1321 status = acpi_install_address_space_handler(adev->handle,
1322 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1323 NULL, priv);
1324 if (ACPI_SUCCESS(status))
1325 return 0;
1326 }
1327
1328 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1329 }
1330
1331 static void i801_acpi_remove(struct i801_priv *priv)
1332 {
1333 struct acpi_device *adev;
1334
1335 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1336 if (!adev)
1337 return;
1338
1339 acpi_remove_address_space_handler(adev->handle,
1340 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1341 }
1342 #else
1343 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1344 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1345 #endif
1346
1347 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1348 {
1349 unsigned char temp;
1350 int err, i;
1351 struct i801_priv *priv;
1352
1353 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1354 if (!priv)
1355 return -ENOMEM;
1356
1357 i2c_set_adapdata(&priv->adapter, priv);
1358 priv->adapter.owner = THIS_MODULE;
1359 priv->adapter.class = i801_get_adapter_class(priv);
1360 priv->adapter.algo = &smbus_algorithm;
1361 priv->adapter.dev.parent = &dev->dev;
1362 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1363 priv->adapter.retries = 3;
1364 mutex_init(&priv->acpi_lock);
1365
1366 priv->pci_dev = dev;
1367 switch (dev->device) {
1368 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1369 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1370 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1371 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1372 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1373 priv->features |= FEATURE_I2C_BLOCK_READ;
1374 priv->features |= FEATURE_IRQ;
1375 priv->features |= FEATURE_SMBUS_PEC;
1376 priv->features |= FEATURE_BLOCK_BUFFER;
1377 priv->features |= FEATURE_TCO;
1378 break;
1379
1380 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1381 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1382 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1383 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1384 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1385 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1386 priv->features |= FEATURE_IDF;
1387 /* fall through */
1388 default:
1389 priv->features |= FEATURE_I2C_BLOCK_READ;
1390 priv->features |= FEATURE_IRQ;
1391 /* fall through */
1392 case PCI_DEVICE_ID_INTEL_82801DB_3:
1393 priv->features |= FEATURE_SMBUS_PEC;
1394 priv->features |= FEATURE_BLOCK_BUFFER;
1395 /* fall through */
1396 case PCI_DEVICE_ID_INTEL_82801CA_3:
1397 case PCI_DEVICE_ID_INTEL_82801BA_2:
1398 case PCI_DEVICE_ID_INTEL_82801AB_3:
1399 case PCI_DEVICE_ID_INTEL_82801AA_3:
1400 break;
1401 }
1402
1403 /* Disable features on user request */
1404 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1405 if (priv->features & disable_features & (1 << i))
1406 dev_notice(&dev->dev, "%s disabled by user\n",
1407 i801_feature_names[i]);
1408 }
1409 priv->features &= ~disable_features;
1410
1411 err = pcim_enable_device(dev);
1412 if (err) {
1413 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1414 err);
1415 return err;
1416 }
1417 pcim_pin_device(dev);
1418
1419 /* Determine the address of the SMBus area */
1420 priv->smba = pci_resource_start(dev, SMBBAR);
1421 if (!priv->smba) {
1422 dev_err(&dev->dev,
1423 "SMBus base address uninitialized, upgrade BIOS\n");
1424 return -ENODEV;
1425 }
1426
1427 if (i801_acpi_probe(priv))
1428 return -ENODEV;
1429
1430 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1431 dev_driver_string(&dev->dev));
1432 if (err) {
1433 dev_err(&dev->dev,
1434 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1435 priv->smba,
1436 (unsigned long long)pci_resource_end(dev, SMBBAR));
1437 i801_acpi_remove(priv);
1438 return err;
1439 }
1440
1441 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1442 priv->original_hstcfg = temp;
1443 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1444 if (!(temp & SMBHSTCFG_HST_EN)) {
1445 dev_info(&dev->dev, "Enabling SMBus device\n");
1446 temp |= SMBHSTCFG_HST_EN;
1447 }
1448 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1449
1450 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1451 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1452 /* Disable SMBus interrupt feature if SMBus using SMI# */
1453 priv->features &= ~FEATURE_IRQ;
1454 }
1455
1456 /* Clear special mode bits */
1457 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1458 outb_p(inb_p(SMBAUXCTL(priv)) &
1459 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1460
1461 /* Default timeout in interrupt mode: 200 ms */
1462 priv->adapter.timeout = HZ / 5;
1463
1464 if (priv->features & FEATURE_IRQ) {
1465 u16 pcictl, pcists;
1466
1467 /* Complain if an interrupt is already pending */
1468 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1469 if (pcists & SMBPCISTS_INTS)
1470 dev_warn(&dev->dev, "An interrupt is pending!\n");
1471
1472 /* Check if interrupts have been disabled */
1473 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1474 if (pcictl & SMBPCICTL_INTDIS) {
1475 dev_info(&dev->dev, "Interrupts are disabled\n");
1476 priv->features &= ~FEATURE_IRQ;
1477 }
1478 }
1479
1480 if (priv->features & FEATURE_IRQ) {
1481 init_waitqueue_head(&priv->waitq);
1482
1483 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1484 IRQF_SHARED,
1485 dev_driver_string(&dev->dev), priv);
1486 if (err) {
1487 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1488 dev->irq, err);
1489 priv->features &= ~FEATURE_IRQ;
1490 }
1491 }
1492 dev_info(&dev->dev, "SMBus using %s\n",
1493 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1494
1495 i801_add_tco(priv);
1496
1497 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1498 "SMBus I801 adapter at %04lx", priv->smba);
1499 err = i2c_add_adapter(&priv->adapter);
1500 if (err) {
1501 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1502 i801_acpi_remove(priv);
1503 return err;
1504 }
1505
1506 i801_probe_optional_slaves(priv);
1507 /* We ignore errors - multiplexing is optional */
1508 i801_add_mux(priv);
1509
1510 pci_set_drvdata(dev, priv);
1511
1512 return 0;
1513 }
1514
1515 static void i801_remove(struct pci_dev *dev)
1516 {
1517 struct i801_priv *priv = pci_get_drvdata(dev);
1518
1519 i801_del_mux(priv);
1520 i2c_del_adapter(&priv->adapter);
1521 i801_acpi_remove(priv);
1522 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1523
1524 platform_device_unregister(priv->tco_pdev);
1525
1526 /*
1527 * do not call pci_disable_device(dev) since it can cause hard hangs on
1528 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1529 */
1530 }
1531
1532 #ifdef CONFIG_PM
1533 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1534 {
1535 struct i801_priv *priv = pci_get_drvdata(dev);
1536
1537 pci_save_state(dev);
1538 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1539 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1540 return 0;
1541 }
1542
1543 static int i801_resume(struct pci_dev *dev)
1544 {
1545 pci_set_power_state(dev, PCI_D0);
1546 pci_restore_state(dev);
1547 return 0;
1548 }
1549 #else
1550 #define i801_suspend NULL
1551 #define i801_resume NULL
1552 #endif
1553
1554 static struct pci_driver i801_driver = {
1555 .name = "i801_smbus",
1556 .id_table = i801_ids,
1557 .probe = i801_probe,
1558 .remove = i801_remove,
1559 .suspend = i801_suspend,
1560 .resume = i801_resume,
1561 };
1562
1563 static int __init i2c_i801_init(void)
1564 {
1565 if (dmi_name_in_vendors("FUJITSU"))
1566 input_apanel_init();
1567 return pci_register_driver(&i801_driver);
1568 }
1569
1570 static void __exit i2c_i801_exit(void)
1571 {
1572 pci_unregister_driver(&i801_driver);
1573 }
1574
1575 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1576 MODULE_DESCRIPTION("I801 SMBus driver");
1577 MODULE_LICENSE("GPL");
1578
1579 module_init(i2c_i801_init);
1580 module_exit(i2c_i801_exit);
Linux with added FPC-III support