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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-omap.c
blob08d26ba61ed3326a8905c99cdb6ee8caaef45727
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/completion.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/io.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/slab.h>
39 #include <linux/i2c-omap.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/pinctrl/consumer.h>
42
43 /* I2C controller revisions */
44 #define OMAP_I2C_OMAP1_REV_2 0x20
45
46 /* I2C controller revisions present on specific hardware */
47 #define OMAP_I2C_REV_ON_2430 0x00000036
48 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
49 #define OMAP_I2C_REV_ON_3630 0x00000040
50 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
51
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55 /* timeout for pm runtime autosuspend */
56 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
57
58 /* timeout for making decision on bus free status */
59 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
60
61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
62 enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
87 };
88
89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
90 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
92 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98 /* I2C Status Register (OMAP_I2C_STAT): */
99 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
101 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
105 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
106 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
112 /* I2C WE wakeup enable register */
113 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
132 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
133 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
134 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
135
136 /* I2C Configuration Register (OMAP_I2C_CON): */
137 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
139 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
140 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
148 /* I2C SCL time value when Master */
149 #define OMAP_I2C_SCLL_HSSCLL 8
150 #define OMAP_I2C_SCLH_HSSCLH 8
151
152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
153 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
154 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
155 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
156 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
157 /* Functional mode */
158 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
159 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
160 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
161 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
162 /* SDA/SCL IO mode */
163 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
164 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
165 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
166 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
167
168 /* OCP_SYSSTATUS bit definitions */
169 #define SYSS_RESETDONE_MASK (1 << 0)
170
171 /* OCP_SYSCONFIG bit definitions */
172 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
173 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
174 #define SYSC_ENAWAKEUP_MASK (1 << 2)
175 #define SYSC_SOFTRESET_MASK (1 << 1)
176 #define SYSC_AUTOIDLE_MASK (1 << 0)
177
178 #define SYSC_IDLEMODE_SMART 0x2
179 #define SYSC_CLOCKACTIVITY_FCLK 0x2
180
181 /* Errata definitions */
182 #define I2C_OMAP_ERRATA_I207 (1 << 0)
183 #define I2C_OMAP_ERRATA_I462 (1 << 1)
184
185 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
186
187 struct omap_i2c_dev {
188 spinlock_t lock; /* IRQ synchronization */
189 struct device *dev;
190 void __iomem *base; /* virtual */
191 int irq;
192 int reg_shift; /* bit shift for I2C register addresses */
193 struct completion cmd_complete;
194 struct resource *ioarea;
195 u32 latency; /* maximum mpu wkup latency */
196 void (*set_mpu_wkup_lat)(struct device *dev,
197 long latency);
198 u32 speed; /* Speed of bus in kHz */
199 u32 flags;
200 u16 scheme;
201 u16 cmd_err;
202 u8 *buf;
203 u8 *regs;
204 size_t buf_len;
205 struct i2c_adapter adapter;
206 u8 threshold;
207 u8 fifo_size; /* use as flag and value
208 * fifo_size==0 implies no fifo
209 * if set, should be trsh+1
210 */
211 u32 rev;
212 unsigned b_hw:1; /* bad h/w fixes */
213 unsigned bb_valid:1; /* true when BB-bit reflects
214 * the I2C bus state
215 */
216 unsigned receiver:1; /* true when we're in receiver mode */
217 u16 iestate; /* Saved interrupt register */
218 u16 pscstate;
219 u16 scllstate;
220 u16 sclhstate;
221 u16 syscstate;
222 u16 westate;
223 u16 errata;
224 };
225
226 static const u8 reg_map_ip_v1[] = {
227 [OMAP_I2C_REV_REG] = 0x00,
228 [OMAP_I2C_IE_REG] = 0x01,
229 [OMAP_I2C_STAT_REG] = 0x02,
230 [OMAP_I2C_IV_REG] = 0x03,
231 [OMAP_I2C_WE_REG] = 0x03,
232 [OMAP_I2C_SYSS_REG] = 0x04,
233 [OMAP_I2C_BUF_REG] = 0x05,
234 [OMAP_I2C_CNT_REG] = 0x06,
235 [OMAP_I2C_DATA_REG] = 0x07,
236 [OMAP_I2C_SYSC_REG] = 0x08,
237 [OMAP_I2C_CON_REG] = 0x09,
238 [OMAP_I2C_OA_REG] = 0x0a,
239 [OMAP_I2C_SA_REG] = 0x0b,
240 [OMAP_I2C_PSC_REG] = 0x0c,
241 [OMAP_I2C_SCLL_REG] = 0x0d,
242 [OMAP_I2C_SCLH_REG] = 0x0e,
243 [OMAP_I2C_SYSTEST_REG] = 0x0f,
244 [OMAP_I2C_BUFSTAT_REG] = 0x10,
245 };
246
247 static const u8 reg_map_ip_v2[] = {
248 [OMAP_I2C_REV_REG] = 0x04,
249 [OMAP_I2C_IE_REG] = 0x2c,
250 [OMAP_I2C_STAT_REG] = 0x28,
251 [OMAP_I2C_IV_REG] = 0x34,
252 [OMAP_I2C_WE_REG] = 0x34,
253 [OMAP_I2C_SYSS_REG] = 0x90,
254 [OMAP_I2C_BUF_REG] = 0x94,
255 [OMAP_I2C_CNT_REG] = 0x98,
256 [OMAP_I2C_DATA_REG] = 0x9c,
257 [OMAP_I2C_SYSC_REG] = 0x10,
258 [OMAP_I2C_CON_REG] = 0xa4,
259 [OMAP_I2C_OA_REG] = 0xa8,
260 [OMAP_I2C_SA_REG] = 0xac,
261 [OMAP_I2C_PSC_REG] = 0xb0,
262 [OMAP_I2C_SCLL_REG] = 0xb4,
263 [OMAP_I2C_SCLH_REG] = 0xb8,
264 [OMAP_I2C_SYSTEST_REG] = 0xbC,
265 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
266 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
267 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
268 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
269 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
270 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
271 };
272
273 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
274 int reg, u16 val)
275 {
276 writew_relaxed(val, omap->base +
277 (omap->regs[reg] << omap->reg_shift));
278 }
279
280 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
281 {
282 return readw_relaxed(omap->base +
283 (omap->regs[reg] << omap->reg_shift));
284 }
285
286 static void __omap_i2c_init(struct omap_i2c_dev *omap)
287 {
288
289 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
290
291 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
292 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
293
294 /* SCL low and high time values */
295 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
296 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
297 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
298 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
299
300 /* Take the I2C module out of reset: */
301 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302
303 /*
304 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
305 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
306 * udelay(1) will be enough to fix that.
307 */
308
309 /*
310 * Don't write to this register if the IE state is 0 as it can
311 * cause deadlock.
312 */
313 if (omap->iestate)
314 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
315 }
316
317 static int omap_i2c_reset(struct omap_i2c_dev *omap)
318 {
319 unsigned long timeout;
320 u16 sysc;
321
322 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
323 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
324
325 /* Disable I2C controller before soft reset */
326 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
327 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
328 ~(OMAP_I2C_CON_EN));
329
330 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
331 /* For some reason we need to set the EN bit before the
332 * reset done bit gets set. */
333 timeout = jiffies + OMAP_I2C_TIMEOUT;
334 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
336 SYSS_RESETDONE_MASK)) {
337 if (time_after(jiffies, timeout)) {
338 dev_warn(omap->dev, "timeout waiting "
339 "for controller reset\n");
340 return -ETIMEDOUT;
341 }
342 msleep(1);
343 }
344
345 /* SYSC register is cleared by the reset; rewrite it */
346 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
347
348 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
349 /* Schedule I2C-bus monitoring on the next transfer */
350 omap->bb_valid = 0;
351 }
352 }
353
354 return 0;
355 }
356
357 static int omap_i2c_init(struct omap_i2c_dev *omap)
358 {
359 u16 psc = 0, scll = 0, sclh = 0;
360 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
361 unsigned long fclk_rate = 12000000;
362 unsigned long internal_clk = 0;
363 struct clk *fclk;
364
365 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
366 /*
367 * Enabling all wakup sources to stop I2C freezing on
368 * WFI instruction.
369 * REVISIT: Some wkup sources might not be needed.
370 */
371 omap->westate = OMAP_I2C_WE_ALL;
372 }
373
374 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
375 /*
376 * The I2C functional clock is the armxor_ck, so there's
377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378 * always returns 12MHz for the functional clock, we can
379 * do this bit unconditionally.
380 */
381 fclk = clk_get(omap->dev, "fck");
382 fclk_rate = clk_get_rate(fclk);
383 clk_put(fclk);
384
385 /* TRM for 5912 says the I2C clock must be prescaled to be
386 * between 7 - 12 MHz. The XOR input clock is typically
387 * 12, 13 or 19.2 MHz. So we should have code that produces:
388 *
389 * XOR MHz Divider Prescaler
390 * 12 1 0
391 * 13 2 1
392 * 19.2 2 1
393 */
394 if (fclk_rate > 12000000)
395 psc = fclk_rate / 12000000;
396 }
397
398 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
399
400 /*
401 * HSI2C controller internal clk rate should be 19.2 Mhz for
402 * HS and for all modes on 2430. On 34xx we can use lower rate
403 * to get longer filter period for better noise suppression.
404 * The filter is iclk (fclk for HS) period.
405 */
406 if (omap->speed > 400 ||
407 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
408 internal_clk = 19200;
409 else if (omap->speed > 100)
410 internal_clk = 9600;
411 else
412 internal_clk = 4000;
413 fclk = clk_get(omap->dev, "fck");
414 fclk_rate = clk_get_rate(fclk) / 1000;
415 clk_put(fclk);
416
417 /* Compute prescaler divisor */
418 psc = fclk_rate / internal_clk;
419 psc = psc - 1;
420
421 /* If configured for High Speed */
422 if (omap->speed > 400) {
423 unsigned long scl;
424
425 /* For first phase of HS mode */
426 scl = internal_clk / 400;
427 fsscll = scl - (scl / 3) - 7;
428 fssclh = (scl / 3) - 5;
429
430 /* For second phase of HS mode */
431 scl = fclk_rate / omap->speed;
432 hsscll = scl - (scl / 3) - 7;
433 hssclh = (scl / 3) - 5;
434 } else if (omap->speed > 100) {
435 unsigned long scl;
436
437 /* Fast mode */
438 scl = internal_clk / omap->speed;
439 fsscll = scl - (scl / 3) - 7;
440 fssclh = (scl / 3) - 5;
441 } else {
442 /* Standard mode */
443 fsscll = internal_clk / (omap->speed * 2) - 7;
444 fssclh = internal_clk / (omap->speed * 2) - 5;
445 }
446 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
447 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
448 } else {
449 /* Program desired operating rate */
450 fclk_rate /= (psc + 1) * 1000;
451 if (psc > 2)
452 psc = 2;
453 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
454 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
455 }
456
457 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
458 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
459 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
460 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
461
462 omap->pscstate = psc;
463 omap->scllstate = scll;
464 omap->sclhstate = sclh;
465
466 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
467 /* Not implemented */
468 omap->bb_valid = 1;
469 }
470
471 __omap_i2c_init(omap);
472
473 return 0;
474 }
475
476 /*
477 * Waiting on Bus Busy
478 */
479 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
480 {
481 unsigned long timeout;
482
483 timeout = jiffies + OMAP_I2C_TIMEOUT;
484 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
485 if (time_after(jiffies, timeout))
486 return i2c_recover_bus(&omap->adapter);
487 msleep(1);
488 }
489
490 return 0;
491 }
492
493 /*
494 * Wait while BB-bit doesn't reflect the I2C bus state
495 *
496 * In a multimaster environment, after IP software reset, BB-bit value doesn't
497 * correspond to the current bus state. It may happen what BB-bit will be 0,
498 * while the bus is busy due to another I2C master activity.
499 * Here are BB-bit values after reset:
500 * SDA SCL BB NOTES
501 * 0 0 0 1, 2
502 * 1 0 0 1, 2
503 * 0 1 1
504 * 1 1 0 3
505 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
506 * combinations on the bus, it set BB-bit to 1.
507 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
508 * it set BB-bit to 0 and BF to 1.
509 * BB and BF bits correctly tracks the bus state while IP is suspended
510 * BB bit became valid on the next FCLK clock after CON_EN bit set
511 *
512 * NOTES:
513 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
514 * completed by IP and results in controller timeout.
515 * 2. Any transfer started when BB=0 and SCL=0 results in IP
516 * starting to drive SDA low. In that case IP corrupt data
517 * on the bus.
518 * 3. Any transfer started in the middle of another master's transfer
519 * results in unpredictable results and data corruption
520 */
521 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
522 {
523 unsigned long bus_free_timeout = 0;
524 unsigned long timeout;
525 int bus_free = 0;
526 u16 stat, systest;
527
528 if (omap->bb_valid)
529 return 0;
530
531 timeout = jiffies + OMAP_I2C_TIMEOUT;
532 while (1) {
533 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
534 /*
535 * We will see BB or BF event in a case IP had detected any
536 * activity on the I2C bus. Now IP correctly tracks the bus
537 * state. BB-bit value is valid.
538 */
539 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
540 break;
541
542 /*
543 * Otherwise, we must look signals on the bus to make
544 * the right decision.
545 */
546 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
547 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
548 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
549 if (!bus_free) {
550 bus_free_timeout = jiffies +
551 OMAP_I2C_BUS_FREE_TIMEOUT;
552 bus_free = 1;
553 }
554
555 /*
556 * SDA and SCL lines was high for 10 ms without bus
557 * activity detected. The bus is free. Consider
558 * BB-bit value is valid.
559 */
560 if (time_after(jiffies, bus_free_timeout))
561 break;
562 } else {
563 bus_free = 0;
564 }
565
566 if (time_after(jiffies, timeout)) {
567 dev_warn(omap->dev, "timeout waiting for bus ready\n");
568 return -ETIMEDOUT;
569 }
570
571 msleep(1);
572 }
573
574 omap->bb_valid = 1;
575 return 0;
576 }
577
578 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
579 {
580 u16 buf;
581
582 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
583 return;
584
585 /*
586 * Set up notification threshold based on message size. We're doing
587 * this to try and avoid draining feature as much as possible. Whenever
588 * we have big messages to transfer (bigger than our total fifo size)
589 * then we might use draining feature to transfer the remaining bytes.
590 */
591
592 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
593
594 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
595
596 if (is_rx) {
597 /* Clear RX Threshold */
598 buf &= ~(0x3f << 8);
599 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
600 } else {
601 /* Clear TX Threshold */
602 buf &= ~0x3f;
603 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
604 }
605
606 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
607
608 if (omap->rev < OMAP_I2C_REV_ON_3630)
609 omap->b_hw = 1; /* Enable hardware fixes */
610
611 /* calculate wakeup latency constraint for MPU */
612 if (omap->set_mpu_wkup_lat != NULL)
613 omap->latency = (1000000 * omap->threshold) /
614 (1000 * omap->speed / 8);
615 }
616
617 /*
618 * Low level master read/write transaction.
619 */
620 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
621 struct i2c_msg *msg, int stop)
622 {
623 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
624 unsigned long timeout;
625 u16 w;
626
627 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
628 msg->addr, msg->len, msg->flags, stop);
629
630 if (msg->len == 0)
631 return -EINVAL;
632
633 omap->receiver = !!(msg->flags & I2C_M_RD);
634 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
635
636 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
637
638 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
639 omap->buf = msg->buf;
640 omap->buf_len = msg->len;
641
642 /* make sure writes to omap->buf_len are ordered */
643 barrier();
644
645 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
646
647 /* Clear the FIFO Buffers */
648 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
649 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
650 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
651
652 reinit_completion(&omap->cmd_complete);
653 omap->cmd_err = 0;
654
655 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
656
657 /* High speed configuration */
658 if (omap->speed > 400)
659 w |= OMAP_I2C_CON_OPMODE_HS;
660
661 if (msg->flags & I2C_M_STOP)
662 stop = 1;
663 if (msg->flags & I2C_M_TEN)
664 w |= OMAP_I2C_CON_XA;
665 if (!(msg->flags & I2C_M_RD))
666 w |= OMAP_I2C_CON_TRX;
667
668 if (!omap->b_hw && stop)
669 w |= OMAP_I2C_CON_STP;
670 /*
671 * NOTE: STAT_BB bit could became 1 here if another master occupy
672 * the bus. IP successfully complete transfer when the bus will be
673 * free again (BB reset to 0).
674 */
675 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
676
677 /*
678 * Don't write stt and stp together on some hardware.
679 */
680 if (omap->b_hw && stop) {
681 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
682 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
683 while (con & OMAP_I2C_CON_STT) {
684 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
685
686 /* Let the user know if i2c is in a bad state */
687 if (time_after(jiffies, delay)) {
688 dev_err(omap->dev, "controller timed out "
689 "waiting for start condition to finish\n");
690 return -ETIMEDOUT;
691 }
692 cpu_relax();
693 }
694
695 w |= OMAP_I2C_CON_STP;
696 w &= ~OMAP_I2C_CON_STT;
697 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
698 }
699
700 /*
701 * REVISIT: We should abort the transfer on signals, but the bus goes
702 * into arbitration and we're currently unable to recover from it.
703 */
704 timeout = wait_for_completion_timeout(&omap->cmd_complete,
705 OMAP_I2C_TIMEOUT);
706 if (timeout == 0) {
707 dev_err(omap->dev, "controller timed out\n");
708 omap_i2c_reset(omap);
709 __omap_i2c_init(omap);
710 return -ETIMEDOUT;
711 }
712
713 if (likely(!omap->cmd_err))
714 return 0;
715
716 /* We have an error */
717 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
718 omap_i2c_reset(omap);
719 __omap_i2c_init(omap);
720 return -EIO;
721 }
722
723 if (omap->cmd_err & OMAP_I2C_STAT_AL)
724 return -EAGAIN;
725
726 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
727 if (msg->flags & I2C_M_IGNORE_NAK)
728 return 0;
729
730 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
731 w |= OMAP_I2C_CON_STP;
732 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
733 return -EREMOTEIO;
734 }
735 return -EIO;
736 }
737
738
739 /*
740 * Prepare controller for a transaction and call omap_i2c_xfer_msg
741 * to do the work during IRQ processing.
742 */
743 static int
744 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
745 {
746 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
747 int i;
748 int r;
749
750 r = pm_runtime_get_sync(omap->dev);
751 if (r < 0)
752 goto out;
753
754 r = omap_i2c_wait_for_bb_valid(omap);
755 if (r < 0)
756 goto out;
757
758 r = omap_i2c_wait_for_bb(omap);
759 if (r < 0)
760 goto out;
761
762 if (omap->set_mpu_wkup_lat != NULL)
763 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
764
765 for (i = 0; i < num; i++) {
766 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
767 if (r != 0)
768 break;
769 }
770
771 if (r == 0)
772 r = num;
773
774 omap_i2c_wait_for_bb(omap);
775
776 if (omap->set_mpu_wkup_lat != NULL)
777 omap->set_mpu_wkup_lat(omap->dev, -1);
778
779 out:
780 pm_runtime_mark_last_busy(omap->dev);
781 pm_runtime_put_autosuspend(omap->dev);
782 return r;
783 }
784
785 static u32
786 omap_i2c_func(struct i2c_adapter *adap)
787 {
788 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
789 I2C_FUNC_PROTOCOL_MANGLING;
790 }
791
792 static inline void
793 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
794 {
795 omap->cmd_err |= err;
796 complete(&omap->cmd_complete);
797 }
798
799 static inline void
800 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
801 {
802 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
803 }
804
805 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
806 {
807 /*
808 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
809 * Not applicable for OMAP4.
810 * Under certain rare conditions, RDR could be set again
811 * when the bus is busy, then ignore the interrupt and
812 * clear the interrupt.
813 */
814 if (stat & OMAP_I2C_STAT_RDR) {
815 /* Step 1: If RDR is set, clear it */
816 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
817
818 /* Step 2: */
819 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
820 & OMAP_I2C_STAT_BB)) {
821
822 /* Step 3: */
823 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
824 & OMAP_I2C_STAT_RDR) {
825 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
826 dev_dbg(omap->dev, "RDR when bus is busy.\n");
827 }
828
829 }
830 }
831 }
832
833 /* rev1 devices are apparently only on some 15xx */
834 #ifdef CONFIG_ARCH_OMAP15XX
835
836 static irqreturn_t
837 omap_i2c_omap1_isr(int this_irq, void *dev_id)
838 {
839 struct omap_i2c_dev *omap = dev_id;
840 u16 iv, w;
841
842 if (pm_runtime_suspended(omap->dev))
843 return IRQ_NONE;
844
845 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
846 switch (iv) {
847 case 0x00: /* None */
848 break;
849 case 0x01: /* Arbitration lost */
850 dev_err(omap->dev, "Arbitration lost\n");
851 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
852 break;
853 case 0x02: /* No acknowledgement */
854 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
855 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
856 break;
857 case 0x03: /* Register access ready */
858 omap_i2c_complete_cmd(omap, 0);
859 break;
860 case 0x04: /* Receive data ready */
861 if (omap->buf_len) {
862 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
863 *omap->buf++ = w;
864 omap->buf_len--;
865 if (omap->buf_len) {
866 *omap->buf++ = w >> 8;
867 omap->buf_len--;
868 }
869 } else
870 dev_err(omap->dev, "RRDY IRQ while no data requested\n");
871 break;
872 case 0x05: /* Transmit data ready */
873 if (omap->buf_len) {
874 w = *omap->buf++;
875 omap->buf_len--;
876 if (omap->buf_len) {
877 w |= *omap->buf++ << 8;
878 omap->buf_len--;
879 }
880 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
881 } else
882 dev_err(omap->dev, "XRDY IRQ while no data to send\n");
883 break;
884 default:
885 return IRQ_NONE;
886 }
887
888 return IRQ_HANDLED;
889 }
890 #else
891 #define omap_i2c_omap1_isr NULL
892 #endif
893
894 /*
895 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
896 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
897 * them from the memory to the I2C interface.
898 */
899 static int errata_omap3_i462(struct omap_i2c_dev *omap)
900 {
901 unsigned long timeout = 10000;
902 u16 stat;
903
904 do {
905 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
906 if (stat & OMAP_I2C_STAT_XUDF)
907 break;
908
909 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
910 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
911 OMAP_I2C_STAT_XDR));
912 if (stat & OMAP_I2C_STAT_NACK) {
913 omap->cmd_err |= OMAP_I2C_STAT_NACK;
914 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
915 }
916
917 if (stat & OMAP_I2C_STAT_AL) {
918 dev_err(omap->dev, "Arbitration lost\n");
919 omap->cmd_err |= OMAP_I2C_STAT_AL;
920 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
921 }
922
923 return -EIO;
924 }
925
926 cpu_relax();
927 } while (--timeout);
928
929 if (!timeout) {
930 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
931 return 0;
932 }
933
934 return 0;
935 }
936
937 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
938 bool is_rdr)
939 {
940 u16 w;
941
942 while (num_bytes--) {
943 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
944 *omap->buf++ = w;
945 omap->buf_len--;
946
947 /*
948 * Data reg in 2430, omap3 and
949 * omap4 is 8 bit wide
950 */
951 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
952 *omap->buf++ = w >> 8;
953 omap->buf_len--;
954 }
955 }
956 }
957
958 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
959 bool is_xdr)
960 {
961 u16 w;
962
963 while (num_bytes--) {
964 w = *omap->buf++;
965 omap->buf_len--;
966
967 /*
968 * Data reg in 2430, omap3 and
969 * omap4 is 8 bit wide
970 */
971 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
972 w |= *omap->buf++ << 8;
973 omap->buf_len--;
974 }
975
976 if (omap->errata & I2C_OMAP_ERRATA_I462) {
977 int ret;
978
979 ret = errata_omap3_i462(omap);
980 if (ret < 0)
981 return ret;
982 }
983
984 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
985 }
986
987 return 0;
988 }
989
990 static irqreturn_t
991 omap_i2c_isr(int irq, void *dev_id)
992 {
993 struct omap_i2c_dev *omap = dev_id;
994 irqreturn_t ret = IRQ_HANDLED;
995 u16 mask;
996 u16 stat;
997
998 spin_lock(&omap->lock);
999 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1000 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1001
1002 if (stat & mask)
1003 ret = IRQ_WAKE_THREAD;
1004
1005 spin_unlock(&omap->lock);
1006
1007 return ret;
1008 }
1009
1010 static irqreturn_t
1011 omap_i2c_isr_thread(int this_irq, void *dev_id)
1012 {
1013 struct omap_i2c_dev *omap = dev_id;
1014 unsigned long flags;
1015 u16 bits;
1016 u16 stat;
1017 int err = 0, count = 0;
1018
1019 spin_lock_irqsave(&omap->lock, flags);
1020 do {
1021 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1022 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1023 stat &= bits;
1024
1025 /* If we're in receiver mode, ignore XDR/XRDY */
1026 if (omap->receiver)
1027 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1028 else
1029 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1030
1031 if (!stat) {
1032 /* my work here is done */
1033 goto out;
1034 }
1035
1036 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1037 if (count++ == 100) {
1038 dev_warn(omap->dev, "Too much work in one IRQ\n");
1039 break;
1040 }
1041
1042 if (stat & OMAP_I2C_STAT_NACK) {
1043 err |= OMAP_I2C_STAT_NACK;
1044 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1045 }
1046
1047 if (stat & OMAP_I2C_STAT_AL) {
1048 dev_err(omap->dev, "Arbitration lost\n");
1049 err |= OMAP_I2C_STAT_AL;
1050 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1051 }
1052
1053 /*
1054 * ProDB0017052: Clear ARDY bit twice
1055 */
1056 if (stat & OMAP_I2C_STAT_ARDY)
1057 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1058
1059 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1060 OMAP_I2C_STAT_AL)) {
1061 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1062 OMAP_I2C_STAT_RDR |
1063 OMAP_I2C_STAT_XRDY |
1064 OMAP_I2C_STAT_XDR |
1065 OMAP_I2C_STAT_ARDY));
1066 break;
1067 }
1068
1069 if (stat & OMAP_I2C_STAT_RDR) {
1070 u8 num_bytes = 1;
1071
1072 if (omap->fifo_size)
1073 num_bytes = omap->buf_len;
1074
1075 if (omap->errata & I2C_OMAP_ERRATA_I207) {
1076 i2c_omap_errata_i207(omap, stat);
1077 num_bytes = (omap_i2c_read_reg(omap,
1078 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1079 }
1080
1081 omap_i2c_receive_data(omap, num_bytes, true);
1082 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1083 continue;
1084 }
1085
1086 if (stat & OMAP_I2C_STAT_RRDY) {
1087 u8 num_bytes = 1;
1088
1089 if (omap->threshold)
1090 num_bytes = omap->threshold;
1091
1092 omap_i2c_receive_data(omap, num_bytes, false);
1093 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1094 continue;
1095 }
1096
1097 if (stat & OMAP_I2C_STAT_XDR) {
1098 u8 num_bytes = 1;
1099 int ret;
1100
1101 if (omap->fifo_size)
1102 num_bytes = omap->buf_len;
1103
1104 ret = omap_i2c_transmit_data(omap, num_bytes, true);
1105 if (ret < 0)
1106 break;
1107
1108 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1109 continue;
1110 }
1111
1112 if (stat & OMAP_I2C_STAT_XRDY) {
1113 u8 num_bytes = 1;
1114 int ret;
1115
1116 if (omap->threshold)
1117 num_bytes = omap->threshold;
1118
1119 ret = omap_i2c_transmit_data(omap, num_bytes, false);
1120 if (ret < 0)
1121 break;
1122
1123 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1124 continue;
1125 }
1126
1127 if (stat & OMAP_I2C_STAT_ROVR) {
1128 dev_err(omap->dev, "Receive overrun\n");
1129 err |= OMAP_I2C_STAT_ROVR;
1130 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1131 break;
1132 }
1133
1134 if (stat & OMAP_I2C_STAT_XUDF) {
1135 dev_err(omap->dev, "Transmit underflow\n");
1136 err |= OMAP_I2C_STAT_XUDF;
1137 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1138 break;
1139 }
1140 } while (stat);
1141
1142 omap_i2c_complete_cmd(omap, err);
1143
1144 out:
1145 spin_unlock_irqrestore(&omap->lock, flags);
1146
1147 return IRQ_HANDLED;
1148 }
1149
1150 static const struct i2c_algorithm omap_i2c_algo = {
1151 .master_xfer = omap_i2c_xfer,
1152 .functionality = omap_i2c_func,
1153 };
1154
1155 #ifdef CONFIG_OF
1156 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1157 .rev = OMAP_I2C_IP_VERSION_1,
1158 .flags = OMAP_I2C_FLAG_NO_FIFO |
1159 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1160 OMAP_I2C_FLAG_16BIT_DATA_REG |
1161 OMAP_I2C_FLAG_BUS_SHIFT_2,
1162 };
1163
1164 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1165 .rev = OMAP_I2C_IP_VERSION_1,
1166 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1167 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1168 };
1169
1170 static struct omap_i2c_bus_platform_data omap3_pdata = {
1171 .rev = OMAP_I2C_IP_VERSION_1,
1172 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1173 };
1174
1175 static struct omap_i2c_bus_platform_data omap4_pdata = {
1176 .rev = OMAP_I2C_IP_VERSION_2,
1177 };
1178
1179 static const struct of_device_id omap_i2c_of_match[] = {
1180 {
1181 .compatible = "ti,omap4-i2c",
1182 .data = &omap4_pdata,
1183 },
1184 {
1185 .compatible = "ti,omap3-i2c",
1186 .data = &omap3_pdata,
1187 },
1188 {
1189 .compatible = "ti,omap2430-i2c",
1190 .data = &omap2430_pdata,
1191 },
1192 {
1193 .compatible = "ti,omap2420-i2c",
1194 .data = &omap2420_pdata,
1195 },
1196 { },
1197 };
1198 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1199 #endif
1200
1201 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1202
1203 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1204 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1205
1206 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1207 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1208 #define OMAP_I2C_SCHEME_0 0
1209 #define OMAP_I2C_SCHEME_1 1
1210
1211 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1212 {
1213 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1214 u32 reg;
1215
1216 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1217
1218 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1219 }
1220
1221 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1222 {
1223 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1224 u32 reg;
1225
1226 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1227
1228 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1229 }
1230
1231 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1232 {
1233 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1234 u32 reg;
1235
1236 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1237 if (val)
1238 reg |= OMAP_I2C_SYSTEST_SCL_O;
1239 else
1240 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1241 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1242 }
1243
1244 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1245 {
1246 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1247 u32 reg;
1248
1249 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1250 /* enable test mode */
1251 reg |= OMAP_I2C_SYSTEST_ST_EN;
1252 /* select SDA/SCL IO mode */
1253 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1254 /* set SCL to high-impedance state (reset value is 0) */
1255 reg |= OMAP_I2C_SYSTEST_SCL_O;
1256 /* set SDA to high-impedance state (reset value is 0) */
1257 reg |= OMAP_I2C_SYSTEST_SDA_O;
1258 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1259 }
1260
1261 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1262 {
1263 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1264 u32 reg;
1265
1266 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1267 /* restore reset values */
1268 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1269 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1270 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1271 reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1272 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1273 }
1274
1275 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1276 .get_scl = omap_i2c_get_scl,
1277 .get_sda = omap_i2c_get_sda,
1278 .set_scl = omap_i2c_set_scl,
1279 .prepare_recovery = omap_i2c_prepare_recovery,
1280 .unprepare_recovery = omap_i2c_unprepare_recovery,
1281 .recover_bus = i2c_generic_scl_recovery,
1282 };
1283
1284 static int
1285 omap_i2c_probe(struct platform_device *pdev)
1286 {
1287 struct omap_i2c_dev *omap;
1288 struct i2c_adapter *adap;
1289 struct resource *mem;
1290 const struct omap_i2c_bus_platform_data *pdata =
1291 dev_get_platdata(&pdev->dev);
1292 struct device_node *node = pdev->dev.of_node;
1293 const struct of_device_id *match;
1294 int irq;
1295 int r;
1296 u32 rev;
1297 u16 minor, major;
1298
1299 irq = platform_get_irq(pdev, 0);
1300 if (irq < 0) {
1301 dev_err(&pdev->dev, "no irq resource?\n");
1302 return irq;
1303 }
1304
1305 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1306 if (!omap)
1307 return -ENOMEM;
1308
1309 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1310 omap->base = devm_ioremap_resource(&pdev->dev, mem);
1311 if (IS_ERR(omap->base))
1312 return PTR_ERR(omap->base);
1313
1314 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1315 if (match) {
1316 u32 freq = 100000; /* default to 100000 Hz */
1317
1318 pdata = match->data;
1319 omap->flags = pdata->flags;
1320
1321 of_property_read_u32(node, "clock-frequency", &freq);
1322 /* convert DT freq value in Hz into kHz for speed */
1323 omap->speed = freq / 1000;
1324 } else if (pdata != NULL) {
1325 omap->speed = pdata->clkrate;
1326 omap->flags = pdata->flags;
1327 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1328 }
1329
1330 omap->dev = &pdev->dev;
1331 omap->irq = irq;
1332
1333 spin_lock_init(&omap->lock);
1334
1335 platform_set_drvdata(pdev, omap);
1336 init_completion(&omap->cmd_complete);
1337
1338 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1339
1340 pm_runtime_enable(omap->dev);
1341 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1342 pm_runtime_use_autosuspend(omap->dev);
1343
1344 r = pm_runtime_get_sync(omap->dev);
1345 if (r < 0)
1346 goto err_free_mem;
1347
1348 /*
1349 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1350 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1351 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1352 * readw_relaxed is done.
1353 */
1354 rev = readw_relaxed(omap->base + 0x04);
1355
1356 omap->scheme = OMAP_I2C_SCHEME(rev);
1357 switch (omap->scheme) {
1358 case OMAP_I2C_SCHEME_0:
1359 omap->regs = (u8 *)reg_map_ip_v1;
1360 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1361 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1362 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1363 break;
1364 case OMAP_I2C_SCHEME_1:
1365 /* FALLTHROUGH */
1366 default:
1367 omap->regs = (u8 *)reg_map_ip_v2;
1368 rev = (rev << 16) |
1369 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1370 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1371 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1372 omap->rev = rev;
1373 }
1374
1375 omap->errata = 0;
1376
1377 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1378 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1379 omap->errata |= I2C_OMAP_ERRATA_I207;
1380
1381 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1382 omap->errata |= I2C_OMAP_ERRATA_I462;
1383
1384 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1385 u16 s;
1386
1387 /* Set up the fifo size - Get total size */
1388 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1389 omap->fifo_size = 0x8 << s;
1390
1391 /*
1392 * Set up notification threshold as half the total available
1393 * size. This is to ensure that we can handle the status on int
1394 * call back latencies.
1395 */
1396
1397 omap->fifo_size = (omap->fifo_size / 2);
1398
1399 if (omap->rev < OMAP_I2C_REV_ON_3630)
1400 omap->b_hw = 1; /* Enable hardware fixes */
1401
1402 /* calculate wakeup latency constraint for MPU */
1403 if (omap->set_mpu_wkup_lat != NULL)
1404 omap->latency = (1000000 * omap->fifo_size) /
1405 (1000 * omap->speed / 8);
1406 }
1407
1408 /* reset ASAP, clearing any IRQs */
1409 omap_i2c_init(omap);
1410
1411 if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1412 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1413 IRQF_NO_SUSPEND, pdev->name, omap);
1414 else
1415 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1416 omap_i2c_isr, omap_i2c_isr_thread,
1417 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1418 pdev->name, omap);
1419
1420 if (r) {
1421 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1422 goto err_unuse_clocks;
1423 }
1424
1425 adap = &omap->adapter;
1426 i2c_set_adapdata(adap, omap);
1427 adap->owner = THIS_MODULE;
1428 adap->class = I2C_CLASS_DEPRECATED;
1429 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1430 adap->algo = &omap_i2c_algo;
1431 adap->dev.parent = &pdev->dev;
1432 adap->dev.of_node = pdev->dev.of_node;
1433 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1434
1435 /* i2c device drivers may be active on return from add_adapter() */
1436 adap->nr = pdev->id;
1437 r = i2c_add_numbered_adapter(adap);
1438 if (r) {
1439 dev_err(omap->dev, "failure adding adapter\n");
1440 goto err_unuse_clocks;
1441 }
1442
1443 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1444 major, minor, omap->speed);
1445
1446 pm_runtime_mark_last_busy(omap->dev);
1447 pm_runtime_put_autosuspend(omap->dev);
1448
1449 return 0;
1450
1451 err_unuse_clocks:
1452 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1453 pm_runtime_put(omap->dev);
1454 pm_runtime_disable(&pdev->dev);
1455 err_free_mem:
1456
1457 return r;
1458 }
1459
1460 static int omap_i2c_remove(struct platform_device *pdev)
1461 {
1462 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1463 int ret;
1464
1465 i2c_del_adapter(&omap->adapter);
1466 ret = pm_runtime_get_sync(&pdev->dev);
1467 if (ret < 0)
1468 return ret;
1469
1470 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1471 pm_runtime_put_sync(&pdev->dev);
1472 pm_runtime_disable(&pdev->dev);
1473 return 0;
1474 }
1475
1476 #ifdef CONFIG_PM
1477 static int omap_i2c_runtime_suspend(struct device *dev)
1478 {
1479 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1480
1481 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1482
1483 if (omap->scheme == OMAP_I2C_SCHEME_0)
1484 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1485 else
1486 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1487 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1488
1489 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1490 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1491 } else {
1492 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1493
1494 /* Flush posted write */
1495 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1496 }
1497
1498 pinctrl_pm_select_sleep_state(dev);
1499
1500 return 0;
1501 }
1502
1503 static int omap_i2c_runtime_resume(struct device *dev)
1504 {
1505 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1506
1507 pinctrl_pm_select_default_state(dev);
1508
1509 if (!omap->regs)
1510 return 0;
1511
1512 __omap_i2c_init(omap);
1513
1514 return 0;
1515 }
1516
1517 static struct dev_pm_ops omap_i2c_pm_ops = {
1518 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1519 omap_i2c_runtime_resume, NULL)
1520 };
1521 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1522 #else
1523 #define OMAP_I2C_PM_OPS NULL
1524 #endif /* CONFIG_PM */
1525
1526 static struct platform_driver omap_i2c_driver = {
1527 .probe = omap_i2c_probe,
1528 .remove = omap_i2c_remove,
1529 .driver = {
1530 .name = "omap_i2c",
1531 .pm = OMAP_I2C_PM_OPS,
1532 .of_match_table = of_match_ptr(omap_i2c_of_match),
1533 },
1534 };
1535
1536 /* I2C may be needed to bring up other drivers */
1537 static int __init
1538 omap_i2c_init_driver(void)
1539 {
1540 return platform_driver_register(&omap_i2c_driver);
1541 }
1542 subsys_initcall(omap_i2c_init_driver);
1543
1544 static void __exit omap_i2c_exit_driver(void)
1545 {
1546 platform_driver_unregister(&omap_i2c_driver);
1547 }
1548 module_exit(omap_i2c_exit_driver);
1549
1550 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1551 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1552 MODULE_LICENSE("GPL");
1553 MODULE_ALIAS("platform:omap_i2c");
Linux with added FPC-III support