drivers/i2c/busses/i2c-rcar.c

   1 /*
   2  * Driver for the Renesas RCar I2C unit
   3  *
   4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   5  *
   6  * Copyright (C) 2012-14 Renesas Solutions Corp.
   7  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8  *
   9  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
  10  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
  11  *
  12  * This file used out-of-tree driver i2c-rcar.c
  13  * Copyright (C) 2011-2012 Renesas Electronics Corporation
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; version 2 of the License.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  */
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/of_device.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/slab.h>
  36
  37 /* register offsets */
  38 #define ICSCR   0x00    /* slave ctrl */
  39 #define ICMCR   0x04    /* master ctrl */
  40 #define ICSSR   0x08    /* slave status */
  41 #define ICMSR   0x0C    /* master status */
  42 #define ICSIER  0x10    /* slave irq enable */
  43 #define ICMIER  0x14    /* master irq enable */
  44 #define ICCCR   0x18    /* clock dividers */
  45 #define ICSAR   0x1C    /* slave address */
  46 #define ICMAR   0x20    /* master address */
  47 #define ICRXTX  0x24    /* data port */
  48
  49 /* ICSCR */
  50 #define SDBS    (1 << 3)        /* slave data buffer select */
  51 #define SIE     (1 << 2)        /* slave interface enable */
  52 #define GCAE    (1 << 1)        /* general call address enable */
  53 #define FNA     (1 << 0)        /* forced non acknowledgment */
  54
  55 /* ICMCR */
  56 #define MDBS    (1 << 7)        /* non-fifo mode switch */
  57 #define FSCL    (1 << 6)        /* override SCL pin */
  58 #define FSDA    (1 << 5)        /* override SDA pin */
  59 #define OBPC    (1 << 4)        /* override pins */
  60 #define MIE     (1 << 3)        /* master if enable */
  61 #define TSBE    (1 << 2)
  62 #define FSB     (1 << 1)        /* force stop bit */
  63 #define ESG     (1 << 0)        /* en startbit gen */
  64
  65 /* ICSSR (also for ICSIER) */
  66 #define GCAR    (1 << 6)        /* general call received */
  67 #define STM     (1 << 5)        /* slave transmit mode */
  68 #define SSR     (1 << 4)        /* stop received */
  69 #define SDE     (1 << 3)        /* slave data empty */
  70 #define SDT     (1 << 2)        /* slave data transmitted */
  71 #define SDR     (1 << 1)        /* slave data received */
  72 #define SAR     (1 << 0)        /* slave addr received */
  73
  74 /* ICMSR (also for ICMIE) */
  75 #define MNR     (1 << 6)        /* nack received */
  76 #define MAL     (1 << 5)        /* arbitration lost */
  77 #define MST     (1 << 4)        /* sent a stop */
  78 #define MDE     (1 << 3)
  79 #define MDT     (1 << 2)
  80 #define MDR     (1 << 1)
  81 #define MAT     (1 << 0)        /* slave addr xfer done */
  82
  83
  84 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
  85 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
  86 #define RCAR_BUS_MASK_DATA      (~(ESG | FSB) & 0xFF)
  87 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
  88
  89 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
  90 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
  91 #define RCAR_IRQ_STOP   (MST)
  92
  93 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0xFF)
  94 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0xFF)
  95
  96 #define ID_LAST_MSG     (1 << 0)
  97 #define ID_DONE         (1 << 2)
  98 #define ID_ARBLOST      (1 << 3)
  99 #define ID_NACK         (1 << 4)
 100
 101 enum rcar_i2c_type {
 102         I2C_RCAR_GEN1,
 103         I2C_RCAR_GEN2,
 104         I2C_RCAR_GEN3,
 105 };
 106
 107 struct rcar_i2c_priv {
 108         void __iomem *io;
 109         struct i2c_adapter adap;
 110         struct i2c_msg *msg;
 111         int msgs_left;
 112         struct clk *clk;
 113
 114         wait_queue_head_t wait;
 115
 116         int pos;
 117         u32 icccr;
 118         u32 flags;
 119         enum rcar_i2c_type devtype;
 120         struct i2c_client *slave;
 121 };
 122
 123 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
 124 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
 125
 126 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
 127 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
 128
 129 #define LOOP_TIMEOUT    1024
 130
 131
 132 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
 133 {
 134         writel(val, priv->io + reg);
 135 }
 136
 137 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
 138 {
 139         return readl(priv->io + reg);
 140 }
 141
 142 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
 143 {
 144         /* reset master mode */
 145         rcar_i2c_write(priv, ICMIER, 0);
 146         rcar_i2c_write(priv, ICMCR, MDBS);
 147         rcar_i2c_write(priv, ICMSR, 0);
 148         /* start clock */
 149         rcar_i2c_write(priv, ICCCR, priv->icccr);
 150 }
 151
 152 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
 153 {
 154         int i;
 155
 156         for (i = 0; i < LOOP_TIMEOUT; i++) {
 157                 /* make sure that bus is not busy */
 158                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
 159                         return 0;
 160                 udelay(1);
 161         }
 162
 163         return -EBUSY;
 164 }
 165
 166 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
 167                                     u32 bus_speed,
 168                                     struct device *dev)
 169 {
 170         u32 scgd, cdf;
 171         u32 round, ick;
 172         u32 scl;
 173         u32 cdf_width;
 174         unsigned long rate;
 175
 176         switch (priv->devtype) {
 177         case I2C_RCAR_GEN1:
 178                 cdf_width = 2;
 179                 break;
 180         case I2C_RCAR_GEN2:
 181         case I2C_RCAR_GEN3:
 182                 cdf_width = 3;
 183                 break;
 184         default:
 185                 dev_err(dev, "device type error\n");
 186                 return -EIO;
 187         }
 188
 189         /*
 190          * calculate SCL clock
 191          * see
 192          *      ICCCR
 193          *
 194          * ick  = clkp / (1 + CDF)
 195          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 196          *
 197          * ick  : I2C internal clock < 20 MHz
 198          * ticf : I2C SCL falling time  =  35 ns here
 199          * tr   : I2C SCL rising  time  = 200 ns here
 200          * intd : LSI internal delay    =  50 ns here
 201          * clkp : peripheral_clk
 202          * F[]  : integer up-valuation
 203          */
 204         rate = clk_get_rate(priv->clk);
 205         cdf = rate / 20000000;
 206         if (cdf >= 1U << cdf_width) {
 207                 dev_err(dev, "Input clock %lu too high\n", rate);
 208                 return -EIO;
 209         }
 210         ick = rate / (cdf + 1);
 211
 212         /*
 213          * it is impossible to calculate large scale
 214          * number on u32. separate it
 215          *
 216          * F[(ticf + tr + intd) * ick]
 217          *  = F[(35 + 200 + 50)ns * ick]
 218          *  = F[285 * ick / 1000000000]
 219          *  = F[(ick / 1000000) * 285 / 1000]
 220          */
 221         round = (ick + 500000) / 1000000 * 285;
 222         round = (round + 500) / 1000;
 223
 224         /*
 225          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 226          *
 227          * Calculation result (= SCL) should be less than
 228          * bus_speed for hardware safety
 229          *
 230          * We could use something along the lines of
 231          *      div = ick / (bus_speed + 1) + 1;
 232          *      scgd = (div - 20 - round + 7) / 8;
 233          *      scl = ick / (20 + (scgd * 8) + round);
 234          * (not fully verified) but that would get pretty involved
 235          */
 236         for (scgd = 0; scgd < 0x40; scgd++) {
 237                 scl = ick / (20 + (scgd * 8) + round);
 238                 if (scl <= bus_speed)
 239                         goto scgd_find;
 240         }
 241         dev_err(dev, "it is impossible to calculate best SCL\n");
 242         return -EIO;
 243
 244 scgd_find:
 245         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 246                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
 247
 248         /*
 249          * keep icccr value
 250          */
 251         priv->icccr = scgd << cdf_width | cdf;
 252
 253         return 0;
 254 }
 255
 256 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 257 {
 258         int read = !!rcar_i2c_is_recv(priv);
 259
 260         priv->pos = 0;
 261         priv->flags = 0;
 262         if (priv->msgs_left == 1)
 263                 rcar_i2c_flags_set(priv, ID_LAST_MSG);
 264
 265         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
 266         rcar_i2c_write(priv, ICMSR, 0);
 267         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 268         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
 269 }
 270
 271 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
 272 {
 273         priv->msg++;
 274         priv->msgs_left--;
 275         rcar_i2c_prepare_msg(priv);
 276 }
 277
 278 /*
 279  *              interrupt functions
 280  */
 281 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
 282 {
 283         struct i2c_msg *msg = priv->msg;
 284
 285         /*
 286          * FIXME
 287          * sometimes, unknown interrupt happened.
 288          * Do nothing
 289          */
 290         if (!(msr & MDE))
 291                 return;
 292
 293         if (priv->pos < msg->len) {
 294                 /*
 295                  * Prepare next data to ICRXTX register.
 296                  * This data will go to _SHIFT_ register.
 297                  *
 298                  *    *
 299                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 300                  */
 301                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
 302                 priv->pos++;
 303
 304         } else {
 305                 /*
 306                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
 307                  * It is on _SHIFT_ register, and will sent to I2C bus.
 308                  *
 309                  *                *
 310                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 311                  */
 312
 313                 if (priv->flags & ID_LAST_MSG) {
 314                         /*
 315                          * If current msg is the _LAST_ msg,
 316                          * prepare stop condition here.
 317                          * ID_DONE will be set on STOP irq.
 318                          */
 319                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 320                 } else {
 321                         rcar_i2c_next_msg(priv);
 322                         return;
 323                 }
 324         }
 325
 326         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
 327 }
 328
 329 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
 330 {
 331         struct i2c_msg *msg = priv->msg;
 332
 333         /*
 334          * FIXME
 335          * sometimes, unknown interrupt happened.
 336          * Do nothing
 337          */
 338         if (!(msr & MDR))
 339                 return;
 340
 341         if (msr & MAT) {
 342                 /* Address transfer phase finished, but no data at this point. */
 343         } else if (priv->pos < msg->len) {
 344                 /*
 345                  * get received data
 346                  */
 347                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
 348                 priv->pos++;
 349         }
 350
 351         /*
 352          * If next received data is the _LAST_,
 353          * go to STOP phase,
 354          * otherwise, go to DATA phase.
 355          */
 356         if (priv->pos + 1 >= msg->len)
 357                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 358
 359         if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
 360                 rcar_i2c_next_msg(priv);
 361         else
 362                 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
 363 }
 364
 365 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
 366 {
 367         u32 ssr_raw, ssr_filtered;
 368         u8 value;
 369
 370         ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
 371         ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
 372
 373         if (!ssr_filtered)
 374                 return false;
 375
 376         /* address detected */
 377         if (ssr_filtered & SAR) {
 378                 /* read or write request */
 379                 if (ssr_raw & STM) {
 380                         i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
 381                         rcar_i2c_write(priv, ICRXTX, value);
 382                         rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
 383                 } else {
 384                         i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
 385                         rcar_i2c_read(priv, ICRXTX);    /* dummy read */
 386                         rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
 387                 }
 388
 389                 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
 390         }
 391
 392         /* master sent stop */
 393         if (ssr_filtered & SSR) {
 394                 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
 395                 rcar_i2c_write(priv, ICSIER, SAR | SSR);
 396                 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
 397         }
 398
 399         /* master wants to write to us */
 400         if (ssr_filtered & SDR) {
 401                 int ret;
 402
 403                 value = rcar_i2c_read(priv, ICRXTX);
 404                 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
 405                 /* Send NACK in case of error */
 406                 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
 407                 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
 408         }
 409
 410         /* master wants to read from us */
 411         if (ssr_filtered & SDE) {
 412                 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
 413                 rcar_i2c_write(priv, ICRXTX, value);
 414                 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
 415         }
 416
 417         return true;
 418 }
 419
 420 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
 421 {
 422         struct rcar_i2c_priv *priv = ptr;
 423         u32 msr, val;
 424
 425         /* Clear START or STOP as soon as we can */
 426         val = rcar_i2c_read(priv, ICMCR);
 427         rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
 428
 429         msr = rcar_i2c_read(priv, ICMSR);
 430
 431         /* Only handle interrupts that are currently enabled */
 432         msr &= rcar_i2c_read(priv, ICMIER);
 433         if (!msr) {
 434                 if (rcar_i2c_slave_irq(priv))
 435                         return IRQ_HANDLED;
 436
 437                 return IRQ_NONE;
 438         }
 439
 440         /* Arbitration lost */
 441         if (msr & MAL) {
 442                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
 443                 goto out;
 444         }
 445
 446         /* Nack */
 447         if (msr & MNR) {
 448                 /* HW automatically sends STOP after received NACK */
 449                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
 450                 rcar_i2c_flags_set(priv, ID_NACK);
 451                 goto out;
 452         }
 453
 454         /* Stop */
 455         if (msr & MST) {
 456                 priv->msgs_left--; /* The last message also made it */
 457                 rcar_i2c_flags_set(priv, ID_DONE);
 458                 goto out;
 459         }
 460
 461         if (rcar_i2c_is_recv(priv))
 462                 rcar_i2c_irq_recv(priv, msr);
 463         else
 464                 rcar_i2c_irq_send(priv, msr);
 465
 466 out:
 467         if (rcar_i2c_flags_has(priv, ID_DONE)) {
 468                 rcar_i2c_write(priv, ICMIER, 0);
 469                 rcar_i2c_write(priv, ICMSR, 0);
 470                 wake_up(&priv->wait);
 471         }
 472
 473         return IRQ_HANDLED;
 474 }
 475
 476 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
 477                                 struct i2c_msg *msgs,
 478                                 int num)
 479 {
 480         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 481         struct device *dev = rcar_i2c_priv_to_dev(priv);
 482         int i, ret;
 483         long time_left;
 484
 485         pm_runtime_get_sync(dev);
 486
 487         rcar_i2c_init(priv);
 488
 489         ret = rcar_i2c_bus_barrier(priv);
 490         if (ret < 0)
 491                 goto out;
 492
 493         for (i = 0; i < num; i++) {
 494                 /* This HW can't send STOP after address phase */
 495                 if (msgs[i].len == 0) {
 496                         ret = -EOPNOTSUPP;
 497                         goto out;
 498                 }
 499         }
 500
 501         /* init data */
 502         priv->msg = msgs;
 503         priv->msgs_left = num;
 504
 505         rcar_i2c_prepare_msg(priv);
 506
 507         time_left = wait_event_timeout(priv->wait,
 508                                      rcar_i2c_flags_has(priv, ID_DONE),
 509                                      num * adap->timeout);
 510         if (!time_left) {
 511                 rcar_i2c_init(priv);
 512                 ret = -ETIMEDOUT;
 513         } else if (rcar_i2c_flags_has(priv, ID_NACK)) {
 514                 ret = -ENXIO;
 515         } else if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
 516                 ret = -EAGAIN;
 517         } else {
 518                 ret = num - priv->msgs_left; /* The number of transfer */
 519         }
 520 out:
 521         pm_runtime_put(dev);
 522
 523         if (ret < 0 && ret != -ENXIO)
 524                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
 525
 526         return ret;
 527 }
 528
 529 static int rcar_reg_slave(struct i2c_client *slave)
 530 {
 531         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 532
 533         if (priv->slave)
 534                 return -EBUSY;
 535
 536         if (slave->flags & I2C_CLIENT_TEN)
 537                 return -EAFNOSUPPORT;
 538
 539         pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
 540
 541         priv->slave = slave;
 542         rcar_i2c_write(priv, ICSAR, slave->addr);
 543         rcar_i2c_write(priv, ICSSR, 0);
 544         rcar_i2c_write(priv, ICSIER, SAR | SSR);
 545         rcar_i2c_write(priv, ICSCR, SIE | SDBS);
 546
 547         return 0;
 548 }
 549
 550 static int rcar_unreg_slave(struct i2c_client *slave)
 551 {
 552         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 553
 554         WARN_ON(!priv->slave);
 555
 556         rcar_i2c_write(priv, ICSIER, 0);
 557         rcar_i2c_write(priv, ICSCR, 0);
 558
 559         priv->slave = NULL;
 560
 561         pm_runtime_put(rcar_i2c_priv_to_dev(priv));
 562
 563         return 0;
 564 }
 565
 566 static u32 rcar_i2c_func(struct i2c_adapter *adap)
 567 {
 568         /* This HW can't do SMBUS_QUICK and NOSTART */
 569         return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
 570                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 571 }
 572
 573 static const struct i2c_algorithm rcar_i2c_algo = {
 574         .master_xfer    = rcar_i2c_master_xfer,
 575         .functionality  = rcar_i2c_func,
 576         .reg_slave      = rcar_reg_slave,
 577         .unreg_slave    = rcar_unreg_slave,
 578 };
 579
 580 static const struct of_device_id rcar_i2c_dt_ids[] = {
 581         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
 582         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
 583         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
 584         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
 585         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
 586         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
 587         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
 588         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
 589         { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
 590         {},
 591 };
 592 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
 593
 594 static int rcar_i2c_probe(struct platform_device *pdev)
 595 {
 596         struct rcar_i2c_priv *priv;
 597         struct i2c_adapter *adap;
 598         struct resource *res;
 599         struct device *dev = &pdev->dev;
 600         u32 bus_speed;
 601         int irq, ret;
 602
 603         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
 604         if (!priv)
 605                 return -ENOMEM;
 606
 607         priv->clk = devm_clk_get(dev, NULL);
 608         if (IS_ERR(priv->clk)) {
 609                 dev_err(dev, "cannot get clock\n");
 610                 return PTR_ERR(priv->clk);
 611         }
 612
 613         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 614         priv->io = devm_ioremap_resource(dev, res);
 615         if (IS_ERR(priv->io))
 616                 return PTR_ERR(priv->io);
 617
 618         bus_speed = 100000; /* default 100 kHz */
 619         of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
 620
 621         priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data;
 622
 623         pm_runtime_enable(dev);
 624         pm_runtime_get_sync(dev);
 625         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
 626         if (ret < 0)
 627                 goto out_pm_put;
 628
 629         pm_runtime_put(dev);
 630
 631         irq = platform_get_irq(pdev, 0);
 632         init_waitqueue_head(&priv->wait);
 633
 634         adap = &priv->adap;
 635         adap->nr = pdev->id;
 636         adap->algo = &rcar_i2c_algo;
 637         adap->class = I2C_CLASS_DEPRECATED;
 638         adap->retries = 3;
 639         adap->dev.parent = dev;
 640         adap->dev.of_node = dev->of_node;
 641         i2c_set_adapdata(adap, priv);
 642         strlcpy(adap->name, pdev->name, sizeof(adap->name));
 643
 644         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
 645                                dev_name(dev), priv);
 646         if (ret < 0) {
 647                 dev_err(dev, "cannot get irq %d\n", irq);
 648                 goto out_pm_disable;
 649         }
 650
 651         platform_set_drvdata(pdev, priv);
 652
 653         ret = i2c_add_numbered_adapter(adap);
 654         if (ret < 0) {
 655                 dev_err(dev, "reg adap failed: %d\n", ret);
 656                 goto out_pm_disable;
 657         }
 658
 659         dev_info(dev, "probed\n");
 660
 661         return 0;
 662
 663  out_pm_put:
 664         pm_runtime_put(dev);
 665  out_pm_disable:
 666         pm_runtime_disable(dev);
 667         return ret;
 668 }
 669
 670 static int rcar_i2c_remove(struct platform_device *pdev)
 671 {
 672         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
 673         struct device *dev = &pdev->dev;
 674
 675         i2c_del_adapter(&priv->adap);
 676         pm_runtime_disable(dev);
 677
 678         return 0;
 679 }
 680
 681 static struct platform_driver rcar_i2c_driver = {
 682         .driver = {
 683                 .name   = "i2c-rcar",
 684                 .of_match_table = rcar_i2c_dt_ids,
 685         },
 686         .probe          = rcar_i2c_probe,
 687         .remove         = rcar_i2c_remove,
 688 };
 689
 690 module_platform_driver(rcar_i2c_driver);
 691
 692 MODULE_LICENSE("GPL v2");
 693 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
 694 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");