2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #define UNIPHIER_FI2C_CR 0x00 /* control register */
23 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
24 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
25 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
26 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
27 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
28 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
29 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
30 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
31 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
32 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
33 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
34 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
35 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
36 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
37 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
38 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
39 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
40 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
41 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
42 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
43 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
44 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
45 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
46 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
47 #define UNIPHIER_FI2C_SR 0x2c /* status register */
48 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
49 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
50 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
51 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
52 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
53 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
54 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
55 #define UNIPHIER_FI2C_RST 0x34 /* reset control */
56 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
57 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
58 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
59 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
60 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
61 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
62 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
63 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
64 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
65 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
66 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
67 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
68 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
69 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
70 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
71 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
73 #define UNIPHIER_FI2C_INT_FAULTS \
74 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
75 #define UNIPHIER_FI2C_INT_STOP \
76 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
78 #define UNIPHIER_FI2C_RD BIT(0)
79 #define UNIPHIER_FI2C_STOP BIT(1)
80 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
81 #define UNIPHIER_FI2C_BYTE_WISE BIT(3)
82 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
84 #define UNIPHIER_FI2C_DEFAULT_SPEED 100000
85 #define UNIPHIER_FI2C_MAX_SPEED 400000
86 #define UNIPHIER_FI2C_FIFO_SIZE 8
88 struct uniphier_fi2c_priv
{
89 struct completion comp
;
90 struct i2c_adapter adap
;
91 void __iomem
*membase
;
98 unsigned int busy_cnt
;
101 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv
*priv
,
104 int fifo_space
= UNIPHIER_FI2C_FIFO_SIZE
;
107 * TX-FIFO stores slave address in it for the first access.
108 * Decrement the counter.
114 if (fifo_space
-- <= 0)
117 dev_dbg(&priv
->adap
.dev
, "write data: %02x\n", *priv
->buf
);
118 writel(*priv
->buf
++, priv
->membase
+ UNIPHIER_FI2C_DTTX
);
123 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv
*priv
)
125 int fifo_left
= priv
->flags
& UNIPHIER_FI2C_BYTE_WISE
?
126 1 : UNIPHIER_FI2C_FIFO_SIZE
;
129 if (fifo_left
-- <= 0)
132 *priv
->buf
++ = readl(priv
->membase
+ UNIPHIER_FI2C_DTRX
);
133 dev_dbg(&priv
->adap
.dev
, "read data: %02x\n", priv
->buf
[-1]);
138 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv
*priv
)
140 writel(priv
->enabled_irqs
, priv
->membase
+ UNIPHIER_FI2C_IE
);
143 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv
*priv
)
145 writel(-1, priv
->membase
+ UNIPHIER_FI2C_IC
);
148 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv
*priv
)
150 dev_dbg(&priv
->adap
.dev
, "stop condition\n");
152 priv
->enabled_irqs
|= UNIPHIER_FI2C_INT_STOP
;
153 uniphier_fi2c_set_irqs(priv
);
154 writel(UNIPHIER_FI2C_CR_MST
| UNIPHIER_FI2C_CR_STO
,
155 priv
->membase
+ UNIPHIER_FI2C_CR
);
158 static irqreturn_t
uniphier_fi2c_interrupt(int irq
, void *dev_id
)
160 struct uniphier_fi2c_priv
*priv
= dev_id
;
163 irq_status
= readl(priv
->membase
+ UNIPHIER_FI2C_INT
);
165 dev_dbg(&priv
->adap
.dev
,
166 "interrupt: enabled_irqs=%04x, irq_status=%04x\n",
167 priv
->enabled_irqs
, irq_status
);
169 if (irq_status
& UNIPHIER_FI2C_INT_STOP
)
172 if (unlikely(irq_status
& UNIPHIER_FI2C_INT_AL
)) {
173 dev_dbg(&priv
->adap
.dev
, "arbitration lost\n");
174 priv
->error
= -EAGAIN
;
178 if (unlikely(irq_status
& UNIPHIER_FI2C_INT_NA
)) {
179 dev_dbg(&priv
->adap
.dev
, "could not get ACK\n");
180 priv
->error
= -ENXIO
;
181 if (priv
->flags
& UNIPHIER_FI2C_RD
) {
183 * work around a hardware bug:
184 * The receive-completed interrupt is never set even if
185 * STOP condition is detected after the address phase
186 * of read transaction fails to get ACK.
187 * To avoid time-out error, we issue STOP here,
188 * but do not wait for its completion.
189 * It should be checked after exiting this handler.
191 uniphier_fi2c_stop(priv
);
192 priv
->flags
|= UNIPHIER_FI2C_DEFER_STOP_COMP
;
198 if (irq_status
& UNIPHIER_FI2C_INT_TE
) {
202 uniphier_fi2c_fill_txfifo(priv
, false);
206 if (irq_status
& (UNIPHIER_FI2C_INT_RF
| UNIPHIER_FI2C_INT_RB
)) {
207 uniphier_fi2c_drain_rxfifo(priv
);
211 if (unlikely(priv
->flags
& UNIPHIER_FI2C_MANUAL_NACK
)) {
212 if (priv
->len
<= UNIPHIER_FI2C_FIFO_SIZE
&&
213 !(priv
->flags
& UNIPHIER_FI2C_BYTE_WISE
)) {
214 dev_dbg(&priv
->adap
.dev
,
215 "enable read byte count IRQ\n");
216 priv
->enabled_irqs
|= UNIPHIER_FI2C_INT_RB
;
217 uniphier_fi2c_set_irqs(priv
);
218 priv
->flags
|= UNIPHIER_FI2C_BYTE_WISE
;
220 if (priv
->len
<= 1) {
221 dev_dbg(&priv
->adap
.dev
, "set NACK\n");
222 writel(UNIPHIER_FI2C_CR_MST
|
223 UNIPHIER_FI2C_CR_NACK
,
224 priv
->membase
+ UNIPHIER_FI2C_CR
);
234 if (priv
->flags
& UNIPHIER_FI2C_STOP
) {
236 uniphier_fi2c_stop(priv
);
239 priv
->enabled_irqs
= 0;
240 uniphier_fi2c_set_irqs(priv
);
241 complete(&priv
->comp
);
245 uniphier_fi2c_clear_irqs(priv
);
250 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv
*priv
, u16 addr
)
252 priv
->enabled_irqs
|= UNIPHIER_FI2C_INT_TE
;
253 /* do not use TX byte counter */
254 writel(0, priv
->membase
+ UNIPHIER_FI2C_TBC
);
255 /* set slave address */
256 writel(UNIPHIER_FI2C_DTTX_CMD
| addr
<< 1,
257 priv
->membase
+ UNIPHIER_FI2C_DTTX
);
258 /* first chunk of data */
259 uniphier_fi2c_fill_txfifo(priv
, true);
262 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv
*priv
, u16 addr
)
264 priv
->flags
|= UNIPHIER_FI2C_RD
;
266 if (likely(priv
->len
< 256)) {
268 * If possible, use RX byte counter.
269 * It can automatically handle NACK for the last byte.
271 writel(priv
->len
, priv
->membase
+ UNIPHIER_FI2C_RBC
);
272 priv
->enabled_irqs
|= UNIPHIER_FI2C_INT_RF
|
273 UNIPHIER_FI2C_INT_RB
;
276 * The byte counter can not count over 256. In this case,
277 * do not use it at all. Drain data when FIFO gets full,
278 * but treat the last portion as a special case.
280 writel(0, priv
->membase
+ UNIPHIER_FI2C_RBC
);
281 priv
->flags
|= UNIPHIER_FI2C_MANUAL_NACK
;
282 priv
->enabled_irqs
|= UNIPHIER_FI2C_INT_RF
;
285 /* set slave address with RD bit */
286 writel(UNIPHIER_FI2C_DTTX_CMD
| UNIPHIER_FI2C_DTTX_RD
| addr
<< 1,
287 priv
->membase
+ UNIPHIER_FI2C_DTTX
);
290 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv
*priv
)
292 writel(UNIPHIER_FI2C_RST_RST
, priv
->membase
+ UNIPHIER_FI2C_RST
);
295 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv
*priv
)
297 writel(UNIPHIER_FI2C_BRST_FOEN
| UNIPHIER_FI2C_BRST_RSCL
,
298 priv
->membase
+ UNIPHIER_FI2C_BRST
);
301 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv
*priv
)
303 uniphier_fi2c_reset(priv
);
304 i2c_recover_bus(&priv
->adap
);
307 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter
*adap
,
308 struct i2c_msg
*msg
, bool stop
)
310 struct uniphier_fi2c_priv
*priv
= i2c_get_adapdata(adap
);
311 bool is_read
= msg
->flags
& I2C_M_RD
;
312 unsigned long time_left
;
314 dev_dbg(&adap
->dev
, "%s: addr=0x%02x, len=%d, stop=%d\n",
315 is_read
? "receive" : "transmit", msg
->addr
, msg
->len
, stop
);
317 priv
->len
= msg
->len
;
318 priv
->buf
= msg
->buf
;
319 priv
->enabled_irqs
= UNIPHIER_FI2C_INT_FAULTS
;
324 priv
->flags
|= UNIPHIER_FI2C_STOP
;
326 reinit_completion(&priv
->comp
);
327 uniphier_fi2c_clear_irqs(priv
);
328 writel(UNIPHIER_FI2C_RST_TBRST
| UNIPHIER_FI2C_RST_RBRST
,
329 priv
->membase
+ UNIPHIER_FI2C_RST
); /* reset TX/RX FIFO */
332 uniphier_fi2c_rx_init(priv
, msg
->addr
);
334 uniphier_fi2c_tx_init(priv
, msg
->addr
);
336 uniphier_fi2c_set_irqs(priv
);
338 dev_dbg(&adap
->dev
, "start condition\n");
339 writel(UNIPHIER_FI2C_CR_MST
| UNIPHIER_FI2C_CR_STA
,
340 priv
->membase
+ UNIPHIER_FI2C_CR
);
342 time_left
= wait_for_completion_timeout(&priv
->comp
, adap
->timeout
);
344 dev_err(&adap
->dev
, "transaction timeout.\n");
345 uniphier_fi2c_recover(priv
);
348 dev_dbg(&adap
->dev
, "complete\n");
350 if (unlikely(priv
->flags
& UNIPHIER_FI2C_DEFER_STOP_COMP
)) {
351 u32 status
= readl(priv
->membase
+ UNIPHIER_FI2C_SR
);
353 if (!(status
& UNIPHIER_FI2C_SR_STS
) ||
354 status
& UNIPHIER_FI2C_SR_BB
) {
356 "stop condition was not completed.\n");
357 uniphier_fi2c_recover(priv
);
365 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter
*adap
)
367 struct uniphier_fi2c_priv
*priv
= i2c_get_adapdata(adap
);
369 if (readl(priv
->membase
+ UNIPHIER_FI2C_SR
) & UNIPHIER_FI2C_SR_DB
) {
370 if (priv
->busy_cnt
++ > 3) {
372 * If bus busy continues too long, it is probably
373 * in a wrong state. Try bus recovery.
375 uniphier_fi2c_recover(priv
);
386 static int uniphier_fi2c_master_xfer(struct i2c_adapter
*adap
,
387 struct i2c_msg
*msgs
, int num
)
389 struct i2c_msg
*msg
, *emsg
= msgs
+ num
;
392 ret
= uniphier_fi2c_check_bus_busy(adap
);
396 for (msg
= msgs
; msg
< emsg
; msg
++) {
397 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
398 bool stop
= (msg
+ 1 == emsg
) || (msg
->flags
& I2C_M_STOP
);
400 ret
= uniphier_fi2c_master_xfer_one(adap
, msg
, stop
);
408 static u32
uniphier_fi2c_functionality(struct i2c_adapter
*adap
)
410 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
413 static const struct i2c_algorithm uniphier_fi2c_algo
= {
414 .master_xfer
= uniphier_fi2c_master_xfer
,
415 .functionality
= uniphier_fi2c_functionality
,
418 static int uniphier_fi2c_get_scl(struct i2c_adapter
*adap
)
420 struct uniphier_fi2c_priv
*priv
= i2c_get_adapdata(adap
);
422 return !!(readl(priv
->membase
+ UNIPHIER_FI2C_BM
) &
423 UNIPHIER_FI2C_BM_SCLS
);
426 static void uniphier_fi2c_set_scl(struct i2c_adapter
*adap
, int val
)
428 struct uniphier_fi2c_priv
*priv
= i2c_get_adapdata(adap
);
430 writel(val
? UNIPHIER_FI2C_BRST_RSCL
: 0,
431 priv
->membase
+ UNIPHIER_FI2C_BRST
);
434 static int uniphier_fi2c_get_sda(struct i2c_adapter
*adap
)
436 struct uniphier_fi2c_priv
*priv
= i2c_get_adapdata(adap
);
438 return !!(readl(priv
->membase
+ UNIPHIER_FI2C_BM
) &
439 UNIPHIER_FI2C_BM_SDAS
);
442 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter
*adap
)
444 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap
));
447 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info
= {
448 .recover_bus
= i2c_generic_scl_recovery
,
449 .get_scl
= uniphier_fi2c_get_scl
,
450 .set_scl
= uniphier_fi2c_set_scl
,
451 .get_sda
= uniphier_fi2c_get_sda
,
452 .unprepare_recovery
= uniphier_fi2c_unprepare_recovery
,
455 static int uniphier_fi2c_clk_init(struct device
*dev
,
456 struct uniphier_fi2c_priv
*priv
)
458 struct device_node
*np
= dev
->of_node
;
459 unsigned long clk_rate
;
460 u32 bus_speed
, clk_count
;
463 if (of_property_read_u32(np
, "clock-frequency", &bus_speed
))
464 bus_speed
= UNIPHIER_FI2C_DEFAULT_SPEED
;
466 if (bus_speed
> UNIPHIER_FI2C_MAX_SPEED
)
467 bus_speed
= UNIPHIER_FI2C_MAX_SPEED
;
469 /* Get input clk rate through clk driver */
470 priv
->clk
= devm_clk_get(dev
, NULL
);
471 if (IS_ERR(priv
->clk
)) {
472 dev_err(dev
, "failed to get clock\n");
473 return PTR_ERR(priv
->clk
);
476 ret
= clk_prepare_enable(priv
->clk
);
480 clk_rate
= clk_get_rate(priv
->clk
);
482 uniphier_fi2c_reset(priv
);
484 clk_count
= clk_rate
/ bus_speed
;
486 writel(clk_count
, priv
->membase
+ UNIPHIER_FI2C_CYC
);
487 writel(clk_count
/ 2, priv
->membase
+ UNIPHIER_FI2C_LCTL
);
488 writel(clk_count
/ 2, priv
->membase
+ UNIPHIER_FI2C_SSUT
);
489 writel(clk_count
/ 16, priv
->membase
+ UNIPHIER_FI2C_DSUT
);
491 uniphier_fi2c_prepare_operation(priv
);
496 static int uniphier_fi2c_probe(struct platform_device
*pdev
)
498 struct device
*dev
= &pdev
->dev
;
499 struct uniphier_fi2c_priv
*priv
;
500 struct resource
*regs
;
504 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
508 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
509 priv
->membase
= devm_ioremap_resource(dev
, regs
);
510 if (IS_ERR(priv
->membase
))
511 return PTR_ERR(priv
->membase
);
513 irq
= platform_get_irq(pdev
, 0);
515 dev_err(dev
, "failed to get IRQ number");
519 init_completion(&priv
->comp
);
520 priv
->adap
.owner
= THIS_MODULE
;
521 priv
->adap
.algo
= &uniphier_fi2c_algo
;
522 priv
->adap
.dev
.parent
= dev
;
523 priv
->adap
.dev
.of_node
= dev
->of_node
;
524 strlcpy(priv
->adap
.name
, "UniPhier FI2C", sizeof(priv
->adap
.name
));
525 priv
->adap
.bus_recovery_info
= &uniphier_fi2c_bus_recovery_info
;
526 i2c_set_adapdata(&priv
->adap
, priv
);
527 platform_set_drvdata(pdev
, priv
);
529 ret
= uniphier_fi2c_clk_init(dev
, priv
);
533 ret
= devm_request_irq(dev
, irq
, uniphier_fi2c_interrupt
, 0,
536 dev_err(dev
, "failed to request irq %d\n", irq
);
540 ret
= i2c_add_adapter(&priv
->adap
);
542 dev_err(dev
, "failed to add I2C adapter\n");
548 clk_disable_unprepare(priv
->clk
);
553 static int uniphier_fi2c_remove(struct platform_device
*pdev
)
555 struct uniphier_fi2c_priv
*priv
= platform_get_drvdata(pdev
);
557 i2c_del_adapter(&priv
->adap
);
558 clk_disable_unprepare(priv
->clk
);
563 static const struct of_device_id uniphier_fi2c_match
[] = {
564 { .compatible
= "socionext,uniphier-fi2c" },
567 MODULE_DEVICE_TABLE(of
, uniphier_fi2c_match
);
569 static struct platform_driver uniphier_fi2c_drv
= {
570 .probe
= uniphier_fi2c_probe
,
571 .remove
= uniphier_fi2c_remove
,
573 .name
= "uniphier-fi2c",
574 .of_match_table
= uniphier_fi2c_match
,
577 module_platform_driver(uniphier_fi2c_drv
);
579 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
580 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
581 MODULE_LICENSE("GPL");