dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-uniphier.c
blobad5eb8bacc6d1649f53d5ca1aa5fbb87263d22f8
1 /*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #define UNIPHIER_I2C_DTRM 0x00 /* TX register */
23 #define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
24 #define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
25 #define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
26 #define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
27 #define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
28 #define UNIPHIER_I2C_DREC 0x04 /* RX register */
29 #define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
30 #define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
31 #define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
32 #define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
33 #define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
34 #define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
35 #define UNIPHIER_I2C_MYAD 0x08 /* slave address */
36 #define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
37 #define UNIPHIER_I2C_BRST 0x10 /* bus reset */
38 #define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
39 #define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
40 #define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
41 #define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
42 #define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
43 #define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
44 #define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
45 #define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
47 #define UNIPHIER_I2C_DEFAULT_SPEED 100000
48 #define UNIPHIER_I2C_MAX_SPEED 400000
50 struct uniphier_i2c_priv {
51 struct completion comp;
52 struct i2c_adapter adap;
53 void __iomem *membase;
54 struct clk *clk;
55 unsigned int busy_cnt;
58 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
60 struct uniphier_i2c_priv *priv = dev_id;
63 * This hardware uses edge triggered interrupt. Do not touch the
64 * hardware registers in this handler to make sure to catch the next
65 * interrupt edge. Just send a complete signal and return.
67 complete(&priv->comp);
69 return IRQ_HANDLED;
72 static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
73 u32 *rxdatap)
75 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
76 unsigned long time_left;
77 u32 rxdata;
79 reinit_completion(&priv->comp);
81 txdata |= UNIPHIER_I2C_DTRM_IRQEN;
82 dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
83 writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
85 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
86 if (unlikely(!time_left)) {
87 dev_err(&adap->dev, "transaction timeout\n");
88 return -ETIMEDOUT;
91 rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
92 dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);
94 if (rxdatap)
95 *rxdatap = rxdata;
97 return 0;
100 static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
102 u32 rxdata;
103 int ret;
105 ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
106 if (ret)
107 return ret;
109 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
110 dev_dbg(&adap->dev, "arbitration lost\n");
111 return -EAGAIN;
113 if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
114 dev_dbg(&adap->dev, "could not get ACK\n");
115 return -ENXIO;
118 return 0;
121 static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
122 const u8 *buf)
124 int ret;
126 dev_dbg(&adap->dev, "start condition\n");
127 ret = uniphier_i2c_send_byte(adap, addr << 1 |
128 UNIPHIER_I2C_DTRM_STA |
129 UNIPHIER_I2C_DTRM_NACK);
130 if (ret)
131 return ret;
133 while (len--) {
134 ret = uniphier_i2c_send_byte(adap,
135 UNIPHIER_I2C_DTRM_NACK | *buf++);
136 if (ret)
137 return ret;
140 return 0;
143 static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
144 u8 *buf)
146 int ret;
148 dev_dbg(&adap->dev, "start condition\n");
149 ret = uniphier_i2c_send_byte(adap, addr << 1 |
150 UNIPHIER_I2C_DTRM_STA |
151 UNIPHIER_I2C_DTRM_NACK |
152 UNIPHIER_I2C_DTRM_RD);
153 if (ret)
154 return ret;
156 while (len--) {
157 u32 rxdata;
159 ret = uniphier_i2c_xfer_byte(adap,
160 len ? 0 : UNIPHIER_I2C_DTRM_NACK,
161 &rxdata);
162 if (ret)
163 return ret;
164 *buf++ = rxdata;
167 return 0;
170 static int uniphier_i2c_stop(struct i2c_adapter *adap)
172 dev_dbg(&adap->dev, "stop condition\n");
173 return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
174 UNIPHIER_I2C_DTRM_NACK);
177 static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
178 struct i2c_msg *msg, bool stop)
180 bool is_read = msg->flags & I2C_M_RD;
181 bool recovery = false;
182 int ret;
184 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
185 is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
187 if (is_read)
188 ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
189 else
190 ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
192 if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
193 return ret;
195 if (ret == -ETIMEDOUT) {
196 /* This error is fatal. Needs recovery. */
197 stop = false;
198 recovery = true;
201 if (stop) {
202 int ret2 = uniphier_i2c_stop(adap);
204 if (ret2) {
205 /* Failed to issue STOP. The bus needs recovery. */
206 recovery = true;
207 ret = ret ?: ret2;
211 if (recovery)
212 i2c_recover_bus(adap);
214 return ret;
217 static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
219 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
221 if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
222 UNIPHIER_I2C_DREC_BBN)) {
223 if (priv->busy_cnt++ > 3) {
225 * If bus busy continues too long, it is probably
226 * in a wrong state. Try bus recovery.
228 i2c_recover_bus(adap);
229 priv->busy_cnt = 0;
232 return -EAGAIN;
235 priv->busy_cnt = 0;
236 return 0;
239 static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
240 struct i2c_msg *msgs, int num)
242 struct i2c_msg *msg, *emsg = msgs + num;
243 int ret;
245 ret = uniphier_i2c_check_bus_busy(adap);
246 if (ret)
247 return ret;
249 for (msg = msgs; msg < emsg; msg++) {
250 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
251 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
253 ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
254 if (ret)
255 return ret;
258 return num;
261 static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
263 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
266 static const struct i2c_algorithm uniphier_i2c_algo = {
267 .master_xfer = uniphier_i2c_master_xfer,
268 .functionality = uniphier_i2c_functionality,
271 static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
273 u32 val = UNIPHIER_I2C_BRST_RSCL;
275 val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
276 writel(val, priv->membase + UNIPHIER_I2C_BRST);
279 static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
281 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
283 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
284 UNIPHIER_I2C_BSTS_SCL);
287 static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
289 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
291 writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
292 priv->membase + UNIPHIER_I2C_BRST);
295 static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
297 struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
299 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
300 UNIPHIER_I2C_BSTS_SDA);
303 static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
305 uniphier_i2c_reset(i2c_get_adapdata(adap), false);
308 static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
309 .recover_bus = i2c_generic_scl_recovery,
310 .get_scl = uniphier_i2c_get_scl,
311 .set_scl = uniphier_i2c_set_scl,
312 .get_sda = uniphier_i2c_get_sda,
313 .unprepare_recovery = uniphier_i2c_unprepare_recovery,
316 static int uniphier_i2c_clk_init(struct device *dev,
317 struct uniphier_i2c_priv *priv)
319 struct device_node *np = dev->of_node;
320 unsigned long clk_rate;
321 u32 bus_speed;
322 int ret;
324 if (of_property_read_u32(np, "clock-frequency", &bus_speed))
325 bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;
327 if (bus_speed > UNIPHIER_I2C_MAX_SPEED)
328 bus_speed = UNIPHIER_I2C_MAX_SPEED;
330 /* Get input clk rate through clk driver */
331 priv->clk = devm_clk_get(dev, NULL);
332 if (IS_ERR(priv->clk)) {
333 dev_err(dev, "failed to get clock\n");
334 return PTR_ERR(priv->clk);
337 ret = clk_prepare_enable(priv->clk);
338 if (ret)
339 return ret;
341 clk_rate = clk_get_rate(priv->clk);
343 uniphier_i2c_reset(priv, true);
345 writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed),
346 priv->membase + UNIPHIER_I2C_CLK);
348 uniphier_i2c_reset(priv, false);
350 return 0;
353 static int uniphier_i2c_probe(struct platform_device *pdev)
355 struct device *dev = &pdev->dev;
356 struct uniphier_i2c_priv *priv;
357 struct resource *regs;
358 int irq;
359 int ret;
361 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
362 if (!priv)
363 return -ENOMEM;
365 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366 priv->membase = devm_ioremap_resource(dev, regs);
367 if (IS_ERR(priv->membase))
368 return PTR_ERR(priv->membase);
370 irq = platform_get_irq(pdev, 0);
371 if (irq < 0) {
372 dev_err(dev, "failed to get IRQ number");
373 return irq;
376 init_completion(&priv->comp);
377 priv->adap.owner = THIS_MODULE;
378 priv->adap.algo = &uniphier_i2c_algo;
379 priv->adap.dev.parent = dev;
380 priv->adap.dev.of_node = dev->of_node;
381 strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
382 priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
383 i2c_set_adapdata(&priv->adap, priv);
384 platform_set_drvdata(pdev, priv);
386 ret = uniphier_i2c_clk_init(dev, priv);
387 if (ret)
388 return ret;
390 ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
391 priv);
392 if (ret) {
393 dev_err(dev, "failed to request irq %d\n", irq);
394 goto err;
397 ret = i2c_add_adapter(&priv->adap);
398 if (ret) {
399 dev_err(dev, "failed to add I2C adapter\n");
400 goto err;
403 err:
404 if (ret)
405 clk_disable_unprepare(priv->clk);
407 return ret;
410 static int uniphier_i2c_remove(struct platform_device *pdev)
412 struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
414 i2c_del_adapter(&priv->adap);
415 clk_disable_unprepare(priv->clk);
417 return 0;
420 static const struct of_device_id uniphier_i2c_match[] = {
421 { .compatible = "socionext,uniphier-i2c" },
422 { /* sentinel */ }
424 MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
426 static struct platform_driver uniphier_i2c_drv = {
427 .probe = uniphier_i2c_probe,
428 .remove = uniphier_i2c_remove,
429 .driver = {
430 .name = "uniphier-i2c",
431 .of_match_table = uniphier_i2c_match,
434 module_platform_driver(uniphier_i2c_drv);
436 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
437 MODULE_DESCRIPTION("UniPhier I2C bus driver");
438 MODULE_LICENSE("GPL");