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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / iio / accel / bmc150-accel-core.c
blobc7122919a8c0eb3f6ddcdabe1d11c893045404ad
1 /*
2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
3 * - BMC150
4 * - BMI055
5 * - BMA255
6 * - BMA250E
7 * - BMA222E
8 * - BMA280
9 *
10 * Copyright (c) 2014, Intel Corporation.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/pm.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/events.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/regmap.h>
39
40 #include "bmc150-accel.h"
41
42 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
43 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
44
45 #define BMC150_ACCEL_REG_CHIP_ID 0x00
46
47 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
48 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
49 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
52 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
53
54 #define BMC150_ACCEL_REG_PMU_LPW 0x11
55 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
56 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
58 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
59
60 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
61
62 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
63 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
64 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
65 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
66
67 /* Default BW: 125Hz */
68 #define BMC150_ACCEL_REG_PMU_BW 0x10
69 #define BMC150_ACCEL_DEF_BW 125
70
71 #define BMC150_ACCEL_REG_RESET 0x14
72 #define BMC150_ACCEL_RESET_VAL 0xB6
73
74 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
75 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
76
77 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
78 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
79 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
80 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
81
82 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
83 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
84 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
85 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
86
87 #define BMC150_ACCEL_REG_INT_EN_0 0x16
88 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
90 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
91
92 #define BMC150_ACCEL_REG_INT_EN_1 0x17
93 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
94 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
95 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
96
97 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
98 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
99
100 #define BMC150_ACCEL_REG_INT_5 0x27
101 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
102
103 #define BMC150_ACCEL_REG_INT_6 0x28
104 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
105
106 /* Slope duration in terms of number of samples */
107 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
108 /* in terms of multiples of g's/LSB, based on range */
109 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
110
111 #define BMC150_ACCEL_REG_XOUT_L 0x02
112
113 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
114
115 /* Sleep Duration values */
116 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
117 #define BMC150_ACCEL_SLEEP_1_MS 0x06
118 #define BMC150_ACCEL_SLEEP_2_MS 0x07
119 #define BMC150_ACCEL_SLEEP_4_MS 0x08
120 #define BMC150_ACCEL_SLEEP_6_MS 0x09
121 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
122 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
123 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
124 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
125 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
126 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
127
128 #define BMC150_ACCEL_REG_TEMP 0x08
129 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
130
131 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
132 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
133
134 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
135 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
136 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
137 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
138 #define BMC150_ACCEL_FIFO_LENGTH 32
139
140 enum bmc150_accel_axis {
141 AXIS_X,
142 AXIS_Y,
143 AXIS_Z,
144 };
145
146 enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
151 };
152
153 struct bmc150_scale_info {
154 int scale;
155 u8 reg_range;
156 };
157
158 struct bmc150_accel_chip_info {
159 const char *name;
160 u8 chip_id;
161 const struct iio_chan_spec *channels;
162 int num_channels;
163 const struct bmc150_scale_info scale_table[4];
164 };
165
166 struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
168 atomic_t users;
169 };
170
171 struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
175 int intr;
176 bool enabled;
177 };
178
179 enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
184 };
185
186 enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
190 };
191
192 struct bmc150_accel_data {
193 struct regmap *regmap;
194 struct device *dev;
195 int irq;
196 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
197 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
198 struct mutex mutex;
199 u8 fifo_mode, watermark;
200 s16 buffer[8];
201 u8 bw_bits;
202 u32 slope_dur;
203 u32 slope_thres;
204 u32 range;
205 int ev_enable_state;
206 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
207 const struct bmc150_accel_chip_info *chip_info;
208 };
209
210 static const struct {
211 int val;
212 int val2;
213 u8 bw_bits;
214 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
215 {31, 260000, 0x09},
216 {62, 500000, 0x0A},
217 {125, 0, 0x0B},
218 {250, 0, 0x0C},
219 {500, 0, 0x0D},
220 {1000, 0, 0x0E},
221 {2000, 0, 0x0F} };
222
223 static const struct {
224 int bw_bits;
225 int msec;
226 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
227 {0x09, 32},
228 {0x0A, 16},
229 {0x0B, 8},
230 {0x0C, 4},
231 {0x0D, 2},
232 {0x0E, 1},
233 {0x0F, 1} };
234
235 static const struct {
236 int sleep_dur;
237 u8 reg_value;
238 } bmc150_accel_sleep_value_table[] = { {0, 0},
239 {500, BMC150_ACCEL_SLEEP_500_MICRO},
240 {1000, BMC150_ACCEL_SLEEP_1_MS},
241 {2000, BMC150_ACCEL_SLEEP_2_MS},
242 {4000, BMC150_ACCEL_SLEEP_4_MS},
243 {6000, BMC150_ACCEL_SLEEP_6_MS},
244 {10000, BMC150_ACCEL_SLEEP_10_MS},
245 {25000, BMC150_ACCEL_SLEEP_25_MS},
246 {50000, BMC150_ACCEL_SLEEP_50_MS},
247 {100000, BMC150_ACCEL_SLEEP_100_MS},
248 {500000, BMC150_ACCEL_SLEEP_500_MS},
249 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
250
251 static const struct regmap_config bmc150_i2c_regmap_conf = {
252 .reg_bits = 8,
253 .val_bits = 8,
254 .max_register = 0x3f,
255 };
256
257 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
258 enum bmc150_power_modes mode,
259 int dur_us)
260 {
261 int i;
262 int ret;
263 u8 lpw_bits;
264 int dur_val = -1;
265
266 if (dur_us > 0) {
267 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
268 ++i) {
269 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
270 dur_us)
271 dur_val =
272 bmc150_accel_sleep_value_table[i].reg_value;
273 }
274 } else {
275 dur_val = 0;
276 }
277
278 if (dur_val < 0)
279 return -EINVAL;
280
281 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
282 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
283
284 dev_dbg(data->dev, "Set Mode bits %x\n", lpw_bits);
285
286 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
287 if (ret < 0) {
288 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
289 return ret;
290 }
291
292 return 0;
293 }
294
295 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
296 int val2)
297 {
298 int i;
299 int ret;
300
301 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
302 if (bmc150_accel_samp_freq_table[i].val == val &&
303 bmc150_accel_samp_freq_table[i].val2 == val2) {
304 ret = regmap_write(data->regmap,
305 BMC150_ACCEL_REG_PMU_BW,
306 bmc150_accel_samp_freq_table[i].bw_bits);
307 if (ret < 0)
308 return ret;
309
310 data->bw_bits =
311 bmc150_accel_samp_freq_table[i].bw_bits;
312 return 0;
313 }
314 }
315
316 return -EINVAL;
317 }
318
319 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
320 {
321 int ret;
322
323 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
324 data->slope_thres);
325 if (ret < 0) {
326 dev_err(data->dev, "Error writing reg_int_6\n");
327 return ret;
328 }
329
330 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
331 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
332 if (ret < 0) {
333 dev_err(data->dev, "Error updating reg_int_5\n");
334 return ret;
335 }
336
337 dev_dbg(data->dev, "%s: %x %x\n", __func__, data->slope_thres,
338 data->slope_dur);
339
340 return ret;
341 }
342
343 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
344 bool state)
345 {
346 if (state)
347 return bmc150_accel_update_slope(t->data);
348
349 return 0;
350 }
351
352 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
353 int *val2)
354 {
355 int i;
356
357 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
358 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
359 *val = bmc150_accel_samp_freq_table[i].val;
360 *val2 = bmc150_accel_samp_freq_table[i].val2;
361 return IIO_VAL_INT_PLUS_MICRO;
362 }
363 }
364
365 return -EINVAL;
366 }
367
368 #ifdef CONFIG_PM
369 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
370 {
371 int i;
372
373 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
374 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
375 return bmc150_accel_sample_upd_time[i].msec;
376 }
377
378 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
379 }
380
381 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
382 {
383 int ret;
384
385 if (on) {
386 ret = pm_runtime_get_sync(data->dev);
387 } else {
388 pm_runtime_mark_last_busy(data->dev);
389 ret = pm_runtime_put_autosuspend(data->dev);
390 }
391
392 if (ret < 0) {
393 dev_err(data->dev,
394 "Failed: bmc150_accel_set_power_state for %d\n", on);
395 if (on)
396 pm_runtime_put_noidle(data->dev);
397
398 return ret;
399 }
400
401 return 0;
402 }
403 #else
404 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
405 {
406 return 0;
407 }
408 #endif
409
410 static const struct bmc150_accel_interrupt_info {
411 u8 map_reg;
412 u8 map_bitmask;
413 u8 en_reg;
414 u8 en_bitmask;
415 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
416 { /* data ready interrupt */
417 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
418 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
419 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
420 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
421 },
422 { /* motion interrupt */
423 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
424 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
425 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
426 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
427 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
428 BMC150_ACCEL_INT_EN_BIT_SLP_Z
429 },
430 { /* fifo watermark interrupt */
431 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
432 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
433 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
434 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
435 },
436 };
437
438 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
439 struct bmc150_accel_data *data)
440 {
441 int i;
442
443 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
444 data->interrupts[i].info = &bmc150_accel_interrupts[i];
445 }
446
447 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
448 bool state)
449 {
450 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
451 const struct bmc150_accel_interrupt_info *info = intr->info;
452 int ret;
453
454 if (state) {
455 if (atomic_inc_return(&intr->users) > 1)
456 return 0;
457 } else {
458 if (atomic_dec_return(&intr->users) > 0)
459 return 0;
460 }
461
462 /*
463 * We will expect the enable and disable to do operation in reverse
464 * order. This will happen here anyway, as our resume operation uses
465 * sync mode runtime pm calls. The suspend operation will be delayed
466 * by autosuspend delay.
467 * So the disable operation will still happen in reverse order of
468 * enable operation. When runtime pm is disabled the mode is always on,
469 * so sequence doesn't matter.
470 */
471 ret = bmc150_accel_set_power_state(data, state);
472 if (ret < 0)
473 return ret;
474
475 /* map the interrupt to the appropriate pins */
476 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
477 (state ? info->map_bitmask : 0));
478 if (ret < 0) {
479 dev_err(data->dev, "Error updating reg_int_map\n");
480 goto out_fix_power_state;
481 }
482
483 /* enable/disable the interrupt */
484 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
485 (state ? info->en_bitmask : 0));
486 if (ret < 0) {
487 dev_err(data->dev, "Error updating reg_int_en\n");
488 goto out_fix_power_state;
489 }
490
491 return 0;
492
493 out_fix_power_state:
494 bmc150_accel_set_power_state(data, false);
495 return ret;
496 }
497
498 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
499 {
500 int ret, i;
501
502 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
503 if (data->chip_info->scale_table[i].scale == val) {
504 ret = regmap_write(data->regmap,
505 BMC150_ACCEL_REG_PMU_RANGE,
506 data->chip_info->scale_table[i].reg_range);
507 if (ret < 0) {
508 dev_err(data->dev,
509 "Error writing pmu_range\n");
510 return ret;
511 }
512
513 data->range = data->chip_info->scale_table[i].reg_range;
514 return 0;
515 }
516 }
517
518 return -EINVAL;
519 }
520
521 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
522 {
523 int ret;
524 unsigned int value;
525
526 mutex_lock(&data->mutex);
527
528 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
529 if (ret < 0) {
530 dev_err(data->dev, "Error reading reg_temp\n");
531 mutex_unlock(&data->mutex);
532 return ret;
533 }
534 *val = sign_extend32(value, 7);
535
536 mutex_unlock(&data->mutex);
537
538 return IIO_VAL_INT;
539 }
540
541 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
542 struct iio_chan_spec const *chan,
543 int *val)
544 {
545 int ret;
546 int axis = chan->scan_index;
547 __le16 raw_val;
548
549 mutex_lock(&data->mutex);
550 ret = bmc150_accel_set_power_state(data, true);
551 if (ret < 0) {
552 mutex_unlock(&data->mutex);
553 return ret;
554 }
555
556 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
557 &raw_val, sizeof(raw_val));
558 if (ret < 0) {
559 dev_err(data->dev, "Error reading axis %d\n", axis);
560 bmc150_accel_set_power_state(data, false);
561 mutex_unlock(&data->mutex);
562 return ret;
563 }
564 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
565 chan->scan_type.realbits - 1);
566 ret = bmc150_accel_set_power_state(data, false);
567 mutex_unlock(&data->mutex);
568 if (ret < 0)
569 return ret;
570
571 return IIO_VAL_INT;
572 }
573
574 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
575 struct iio_chan_spec const *chan,
576 int *val, int *val2, long mask)
577 {
578 struct bmc150_accel_data *data = iio_priv(indio_dev);
579 int ret;
580
581 switch (mask) {
582 case IIO_CHAN_INFO_RAW:
583 switch (chan->type) {
584 case IIO_TEMP:
585 return bmc150_accel_get_temp(data, val);
586 case IIO_ACCEL:
587 if (iio_buffer_enabled(indio_dev))
588 return -EBUSY;
589 else
590 return bmc150_accel_get_axis(data, chan, val);
591 default:
592 return -EINVAL;
593 }
594 case IIO_CHAN_INFO_OFFSET:
595 if (chan->type == IIO_TEMP) {
596 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
597 return IIO_VAL_INT;
598 } else {
599 return -EINVAL;
600 }
601 case IIO_CHAN_INFO_SCALE:
602 *val = 0;
603 switch (chan->type) {
604 case IIO_TEMP:
605 *val2 = 500000;
606 return IIO_VAL_INT_PLUS_MICRO;
607 case IIO_ACCEL:
608 {
609 int i;
610 const struct bmc150_scale_info *si;
611 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
612
613 for (i = 0; i < st_size; ++i) {
614 si = &data->chip_info->scale_table[i];
615 if (si->reg_range == data->range) {
616 *val2 = si->scale;
617 return IIO_VAL_INT_PLUS_MICRO;
618 }
619 }
620 return -EINVAL;
621 }
622 default:
623 return -EINVAL;
624 }
625 case IIO_CHAN_INFO_SAMP_FREQ:
626 mutex_lock(&data->mutex);
627 ret = bmc150_accel_get_bw(data, val, val2);
628 mutex_unlock(&data->mutex);
629 return ret;
630 default:
631 return -EINVAL;
632 }
633 }
634
635 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
636 struct iio_chan_spec const *chan,
637 int val, int val2, long mask)
638 {
639 struct bmc150_accel_data *data = iio_priv(indio_dev);
640 int ret;
641
642 switch (mask) {
643 case IIO_CHAN_INFO_SAMP_FREQ:
644 mutex_lock(&data->mutex);
645 ret = bmc150_accel_set_bw(data, val, val2);
646 mutex_unlock(&data->mutex);
647 break;
648 case IIO_CHAN_INFO_SCALE:
649 if (val)
650 return -EINVAL;
651
652 mutex_lock(&data->mutex);
653 ret = bmc150_accel_set_scale(data, val2);
654 mutex_unlock(&data->mutex);
655 return ret;
656 default:
657 ret = -EINVAL;
658 }
659
660 return ret;
661 }
662
663 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
664 const struct iio_chan_spec *chan,
665 enum iio_event_type type,
666 enum iio_event_direction dir,
667 enum iio_event_info info,
668 int *val, int *val2)
669 {
670 struct bmc150_accel_data *data = iio_priv(indio_dev);
671
672 *val2 = 0;
673 switch (info) {
674 case IIO_EV_INFO_VALUE:
675 *val = data->slope_thres;
676 break;
677 case IIO_EV_INFO_PERIOD:
678 *val = data->slope_dur;
679 break;
680 default:
681 return -EINVAL;
682 }
683
684 return IIO_VAL_INT;
685 }
686
687 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
688 const struct iio_chan_spec *chan,
689 enum iio_event_type type,
690 enum iio_event_direction dir,
691 enum iio_event_info info,
692 int val, int val2)
693 {
694 struct bmc150_accel_data *data = iio_priv(indio_dev);
695
696 if (data->ev_enable_state)
697 return -EBUSY;
698
699 switch (info) {
700 case IIO_EV_INFO_VALUE:
701 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
702 break;
703 case IIO_EV_INFO_PERIOD:
704 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 return 0;
711 }
712
713 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
714 const struct iio_chan_spec *chan,
715 enum iio_event_type type,
716 enum iio_event_direction dir)
717 {
718 struct bmc150_accel_data *data = iio_priv(indio_dev);
719
720 return data->ev_enable_state;
721 }
722
723 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
724 const struct iio_chan_spec *chan,
725 enum iio_event_type type,
726 enum iio_event_direction dir,
727 int state)
728 {
729 struct bmc150_accel_data *data = iio_priv(indio_dev);
730 int ret;
731
732 if (state == data->ev_enable_state)
733 return 0;
734
735 mutex_lock(&data->mutex);
736
737 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
738 state);
739 if (ret < 0) {
740 mutex_unlock(&data->mutex);
741 return ret;
742 }
743
744 data->ev_enable_state = state;
745 mutex_unlock(&data->mutex);
746
747 return 0;
748 }
749
750 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
751 struct iio_trigger *trig)
752 {
753 struct bmc150_accel_data *data = iio_priv(indio_dev);
754 int i;
755
756 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
757 if (data->triggers[i].indio_trig == trig)
758 return 0;
759 }
760
761 return -EINVAL;
762 }
763
764 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
765 struct device_attribute *attr,
766 char *buf)
767 {
768 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
769 struct bmc150_accel_data *data = iio_priv(indio_dev);
770 int wm;
771
772 mutex_lock(&data->mutex);
773 wm = data->watermark;
774 mutex_unlock(&data->mutex);
775
776 return sprintf(buf, "%d\n", wm);
777 }
778
779 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
780 struct device_attribute *attr,
781 char *buf)
782 {
783 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
784 struct bmc150_accel_data *data = iio_priv(indio_dev);
785 bool state;
786
787 mutex_lock(&data->mutex);
788 state = data->fifo_mode;
789 mutex_unlock(&data->mutex);
790
791 return sprintf(buf, "%d\n", state);
792 }
793
794 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
795 static IIO_CONST_ATTR(hwfifo_watermark_max,
796 __stringify(BMC150_ACCEL_FIFO_LENGTH));
797 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
798 bmc150_accel_get_fifo_state, NULL, 0);
799 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
800 bmc150_accel_get_fifo_watermark, NULL, 0);
801
802 static const struct attribute *bmc150_accel_fifo_attributes[] = {
803 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
804 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
805 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
806 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
807 NULL,
808 };
809
810 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
811 {
812 struct bmc150_accel_data *data = iio_priv(indio_dev);
813
814 if (val > BMC150_ACCEL_FIFO_LENGTH)
815 val = BMC150_ACCEL_FIFO_LENGTH;
816
817 mutex_lock(&data->mutex);
818 data->watermark = val;
819 mutex_unlock(&data->mutex);
820
821 return 0;
822 }
823
824 /*
825 * We must read at least one full frame in one burst, otherwise the rest of the
826 * frame data is discarded.
827 */
828 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
829 char *buffer, int samples)
830 {
831 int sample_length = 3 * 2;
832 int ret;
833 int total_length = samples * sample_length;
834 int i;
835 size_t step = regmap_get_raw_read_max(data->regmap);
836
837 if (!step || step > total_length)
838 step = total_length;
839 else if (step < total_length)
840 step = sample_length;
841
842 /*
843 * Seems we have a bus with size limitation so we have to execute
844 * multiple reads
845 */
846 for (i = 0; i < total_length; i += step) {
847 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
848 &buffer[i], step);
849 if (ret)
850 break;
851 }
852
853 if (ret)
854 dev_err(data->dev, "Error transferring data from fifo in single steps of %zu\n",
855 step);
856
857 return ret;
858 }
859
860 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
861 unsigned samples, bool irq)
862 {
863 struct bmc150_accel_data *data = iio_priv(indio_dev);
864 int ret, i;
865 u8 count;
866 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
867 int64_t tstamp;
868 uint64_t sample_period;
869 unsigned int val;
870
871 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
872 if (ret < 0) {
873 dev_err(data->dev, "Error reading reg_fifo_status\n");
874 return ret;
875 }
876
877 count = val & 0x7F;
878
879 if (!count)
880 return 0;
881
882 /*
883 * If we getting called from IRQ handler we know the stored timestamp is
884 * fairly accurate for the last stored sample. Otherwise, if we are
885 * called as a result of a read operation from userspace and hence
886 * before the watermark interrupt was triggered, take a timestamp
887 * now. We can fall anywhere in between two samples so the error in this
888 * case is at most one sample period.
889 */
890 if (!irq) {
891 data->old_timestamp = data->timestamp;
892 data->timestamp = iio_get_time_ns();
893 }
894
895 /*
896 * Approximate timestamps for each of the sample based on the sampling
897 * frequency, timestamp for last sample and number of samples.
898 *
899 * Note that we can't use the current bandwidth settings to compute the
900 * sample period because the sample rate varies with the device
901 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
902 * small variation adds when we store a large number of samples and
903 * creates significant jitter between the last and first samples in
904 * different batches (e.g. 32ms vs 21ms).
905 *
906 * To avoid this issue we compute the actual sample period ourselves
907 * based on the timestamp delta between the last two flush operations.
908 */
909 sample_period = (data->timestamp - data->old_timestamp);
910 do_div(sample_period, count);
911 tstamp = data->timestamp - (count - 1) * sample_period;
912
913 if (samples && count > samples)
914 count = samples;
915
916 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
917 if (ret)
918 return ret;
919
920 /*
921 * Ideally we want the IIO core to handle the demux when running in fifo
922 * mode but not when running in triggered buffer mode. Unfortunately
923 * this does not seem to be possible, so stick with driver demux for
924 * now.
925 */
926 for (i = 0; i < count; i++) {
927 u16 sample[8];
928 int j, bit;
929
930 j = 0;
931 for_each_set_bit(bit, indio_dev->active_scan_mask,
932 indio_dev->masklength)
933 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
934
935 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
936
937 tstamp += sample_period;
938 }
939
940 return count;
941 }
942
943 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
944 {
945 struct bmc150_accel_data *data = iio_priv(indio_dev);
946 int ret;
947
948 mutex_lock(&data->mutex);
949 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
950 mutex_unlock(&data->mutex);
951
952 return ret;
953 }
954
955 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
956 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
957
958 static struct attribute *bmc150_accel_attributes[] = {
959 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
960 NULL,
961 };
962
963 static const struct attribute_group bmc150_accel_attrs_group = {
964 .attrs = bmc150_accel_attributes,
965 };
966
967 static const struct iio_event_spec bmc150_accel_event = {
968 .type = IIO_EV_TYPE_ROC,
969 .dir = IIO_EV_DIR_EITHER,
970 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
971 BIT(IIO_EV_INFO_ENABLE) |
972 BIT(IIO_EV_INFO_PERIOD)
973 };
974
975 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
976 .type = IIO_ACCEL, \
977 .modified = 1, \
978 .channel2 = IIO_MOD_##_axis, \
979 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
980 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
981 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
982 .scan_index = AXIS_##_axis, \
983 .scan_type = { \
984 .sign = 's', \
985 .realbits = (bits), \
986 .storagebits = 16, \
987 .shift = 16 - (bits), \
988 .endianness = IIO_LE, \
989 }, \
990 .event_spec = &bmc150_accel_event, \
991 .num_event_specs = 1 \
992 }
993
994 #define BMC150_ACCEL_CHANNELS(bits) { \
995 { \
996 .type = IIO_TEMP, \
997 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
998 BIT(IIO_CHAN_INFO_SCALE) | \
999 BIT(IIO_CHAN_INFO_OFFSET), \
1000 .scan_index = -1, \
1001 }, \
1002 BMC150_ACCEL_CHANNEL(X, bits), \
1003 BMC150_ACCEL_CHANNEL(Y, bits), \
1004 BMC150_ACCEL_CHANNEL(Z, bits), \
1005 IIO_CHAN_SOFT_TIMESTAMP(3), \
1006 }
1007
1008 static const struct iio_chan_spec bma222e_accel_channels[] =
1009 BMC150_ACCEL_CHANNELS(8);
1010 static const struct iio_chan_spec bma250e_accel_channels[] =
1011 BMC150_ACCEL_CHANNELS(10);
1012 static const struct iio_chan_spec bmc150_accel_channels[] =
1013 BMC150_ACCEL_CHANNELS(12);
1014 static const struct iio_chan_spec bma280_accel_channels[] =
1015 BMC150_ACCEL_CHANNELS(14);
1016
1017 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1018 [bmc150] = {
1019 .name = "BMC150A",
1020 .chip_id = 0xFA,
1021 .channels = bmc150_accel_channels,
1022 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1023 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1024 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1025 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1026 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1027 },
1028 [bmi055] = {
1029 .name = "BMI055A",
1030 .chip_id = 0xFA,
1031 .channels = bmc150_accel_channels,
1032 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1033 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1034 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1035 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1036 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1037 },
1038 [bma255] = {
1039 .name = "BMA0255",
1040 .chip_id = 0xFA,
1041 .channels = bmc150_accel_channels,
1042 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1043 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1044 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1045 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1046 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1047 },
1048 [bma250e] = {
1049 .name = "BMA250E",
1050 .chip_id = 0xF9,
1051 .channels = bma250e_accel_channels,
1052 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1053 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1054 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1055 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1056 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1057 },
1058 [bma222e] = {
1059 .name = "BMA222E",
1060 .chip_id = 0xF8,
1061 .channels = bma222e_accel_channels,
1062 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1063 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1064 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1065 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1066 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1067 },
1068 [bma280] = {
1069 .name = "BMA0280",
1070 .chip_id = 0xFB,
1071 .channels = bma280_accel_channels,
1072 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1073 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1074 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1075 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1076 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1077 },
1078 };
1079
1080 static const struct iio_info bmc150_accel_info = {
1081 .attrs = &bmc150_accel_attrs_group,
1082 .read_raw = bmc150_accel_read_raw,
1083 .write_raw = bmc150_accel_write_raw,
1084 .read_event_value = bmc150_accel_read_event,
1085 .write_event_value = bmc150_accel_write_event,
1086 .write_event_config = bmc150_accel_write_event_config,
1087 .read_event_config = bmc150_accel_read_event_config,
1088 .driver_module = THIS_MODULE,
1089 };
1090
1091 static const struct iio_info bmc150_accel_info_fifo = {
1092 .attrs = &bmc150_accel_attrs_group,
1093 .read_raw = bmc150_accel_read_raw,
1094 .write_raw = bmc150_accel_write_raw,
1095 .read_event_value = bmc150_accel_read_event,
1096 .write_event_value = bmc150_accel_write_event,
1097 .write_event_config = bmc150_accel_write_event_config,
1098 .read_event_config = bmc150_accel_read_event_config,
1099 .validate_trigger = bmc150_accel_validate_trigger,
1100 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1101 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1102 .driver_module = THIS_MODULE,
1103 };
1104
1105 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1106 {
1107 struct iio_poll_func *pf = p;
1108 struct iio_dev *indio_dev = pf->indio_dev;
1109 struct bmc150_accel_data *data = iio_priv(indio_dev);
1110 int bit, ret, i = 0;
1111 unsigned int raw_val;
1112
1113 mutex_lock(&data->mutex);
1114 for_each_set_bit(bit, indio_dev->active_scan_mask,
1115 indio_dev->masklength) {
1116 ret = regmap_bulk_read(data->regmap,
1117 BMC150_ACCEL_AXIS_TO_REG(bit), &raw_val,
1118 2);
1119 if (ret < 0) {
1120 mutex_unlock(&data->mutex);
1121 goto err_read;
1122 }
1123 data->buffer[i++] = raw_val;
1124 }
1125 mutex_unlock(&data->mutex);
1126
1127 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1128 pf->timestamp);
1129 err_read:
1130 iio_trigger_notify_done(indio_dev->trig);
1131
1132 return IRQ_HANDLED;
1133 }
1134
1135 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1136 {
1137 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1138 struct bmc150_accel_data *data = t->data;
1139 int ret;
1140
1141 /* new data interrupts don't need ack */
1142 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1143 return 0;
1144
1145 mutex_lock(&data->mutex);
1146 /* clear any latched interrupt */
1147 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1148 BMC150_ACCEL_INT_MODE_LATCH_INT |
1149 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1150 mutex_unlock(&data->mutex);
1151 if (ret < 0) {
1152 dev_err(data->dev,
1153 "Error writing reg_int_rst_latch\n");
1154 return ret;
1155 }
1156
1157 return 0;
1158 }
1159
1160 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1161 bool state)
1162 {
1163 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1164 struct bmc150_accel_data *data = t->data;
1165 int ret;
1166
1167 mutex_lock(&data->mutex);
1168
1169 if (t->enabled == state) {
1170 mutex_unlock(&data->mutex);
1171 return 0;
1172 }
1173
1174 if (t->setup) {
1175 ret = t->setup(t, state);
1176 if (ret < 0) {
1177 mutex_unlock(&data->mutex);
1178 return ret;
1179 }
1180 }
1181
1182 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1183 if (ret < 0) {
1184 mutex_unlock(&data->mutex);
1185 return ret;
1186 }
1187
1188 t->enabled = state;
1189
1190 mutex_unlock(&data->mutex);
1191
1192 return ret;
1193 }
1194
1195 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1196 .set_trigger_state = bmc150_accel_trigger_set_state,
1197 .try_reenable = bmc150_accel_trig_try_reen,
1198 .owner = THIS_MODULE,
1199 };
1200
1201 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1202 {
1203 struct bmc150_accel_data *data = iio_priv(indio_dev);
1204 int dir;
1205 int ret;
1206 unsigned int val;
1207
1208 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1209 if (ret < 0) {
1210 dev_err(data->dev, "Error reading reg_int_status_2\n");
1211 return ret;
1212 }
1213
1214 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1215 dir = IIO_EV_DIR_FALLING;
1216 else
1217 dir = IIO_EV_DIR_RISING;
1218
1219 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1220 iio_push_event(indio_dev,
1221 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1222 0,
1223 IIO_MOD_X,
1224 IIO_EV_TYPE_ROC,
1225 dir),
1226 data->timestamp);
1227
1228 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1229 iio_push_event(indio_dev,
1230 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1231 0,
1232 IIO_MOD_Y,
1233 IIO_EV_TYPE_ROC,
1234 dir),
1235 data->timestamp);
1236
1237 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1238 iio_push_event(indio_dev,
1239 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1240 0,
1241 IIO_MOD_Z,
1242 IIO_EV_TYPE_ROC,
1243 dir),
1244 data->timestamp);
1245
1246 return ret;
1247 }
1248
1249 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1250 {
1251 struct iio_dev *indio_dev = private;
1252 struct bmc150_accel_data *data = iio_priv(indio_dev);
1253 bool ack = false;
1254 int ret;
1255
1256 mutex_lock(&data->mutex);
1257
1258 if (data->fifo_mode) {
1259 ret = __bmc150_accel_fifo_flush(indio_dev,
1260 BMC150_ACCEL_FIFO_LENGTH, true);
1261 if (ret > 0)
1262 ack = true;
1263 }
1264
1265 if (data->ev_enable_state) {
1266 ret = bmc150_accel_handle_roc_event(indio_dev);
1267 if (ret > 0)
1268 ack = true;
1269 }
1270
1271 if (ack) {
1272 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1273 BMC150_ACCEL_INT_MODE_LATCH_INT |
1274 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1275 if (ret)
1276 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1277
1278 ret = IRQ_HANDLED;
1279 } else {
1280 ret = IRQ_NONE;
1281 }
1282
1283 mutex_unlock(&data->mutex);
1284
1285 return ret;
1286 }
1287
1288 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1289 {
1290 struct iio_dev *indio_dev = private;
1291 struct bmc150_accel_data *data = iio_priv(indio_dev);
1292 bool ack = false;
1293 int i;
1294
1295 data->old_timestamp = data->timestamp;
1296 data->timestamp = iio_get_time_ns();
1297
1298 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1299 if (data->triggers[i].enabled) {
1300 iio_trigger_poll(data->triggers[i].indio_trig);
1301 ack = true;
1302 break;
1303 }
1304 }
1305
1306 if (data->ev_enable_state || data->fifo_mode)
1307 return IRQ_WAKE_THREAD;
1308
1309 if (ack)
1310 return IRQ_HANDLED;
1311
1312 return IRQ_NONE;
1313 }
1314
1315 static const struct {
1316 int intr;
1317 const char *name;
1318 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1319 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1320 {
1321 .intr = 0,
1322 .name = "%s-dev%d",
1323 },
1324 {
1325 .intr = 1,
1326 .name = "%s-any-motion-dev%d",
1327 .setup = bmc150_accel_any_motion_setup,
1328 },
1329 };
1330
1331 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1332 int from)
1333 {
1334 int i;
1335
1336 for (i = from; i >= 0; i--) {
1337 if (data->triggers[i].indio_trig) {
1338 iio_trigger_unregister(data->triggers[i].indio_trig);
1339 data->triggers[i].indio_trig = NULL;
1340 }
1341 }
1342 }
1343
1344 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1345 struct bmc150_accel_data *data)
1346 {
1347 int i, ret;
1348
1349 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1350 struct bmc150_accel_trigger *t = &data->triggers[i];
1351
1352 t->indio_trig = devm_iio_trigger_alloc(data->dev,
1353 bmc150_accel_triggers[i].name,
1354 indio_dev->name,
1355 indio_dev->id);
1356 if (!t->indio_trig) {
1357 ret = -ENOMEM;
1358 break;
1359 }
1360
1361 t->indio_trig->dev.parent = data->dev;
1362 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1363 t->intr = bmc150_accel_triggers[i].intr;
1364 t->data = data;
1365 t->setup = bmc150_accel_triggers[i].setup;
1366 iio_trigger_set_drvdata(t->indio_trig, t);
1367
1368 ret = iio_trigger_register(t->indio_trig);
1369 if (ret)
1370 break;
1371 }
1372
1373 if (ret)
1374 bmc150_accel_unregister_triggers(data, i - 1);
1375
1376 return ret;
1377 }
1378
1379 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1380 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1381 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1382
1383 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1384 {
1385 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1386 int ret;
1387
1388 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1389 if (ret < 0) {
1390 dev_err(data->dev, "Error writing reg_fifo_config1\n");
1391 return ret;
1392 }
1393
1394 if (!data->fifo_mode)
1395 return 0;
1396
1397 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1398 data->watermark);
1399 if (ret < 0)
1400 dev_err(data->dev, "Error writing reg_fifo_config0\n");
1401
1402 return ret;
1403 }
1404
1405 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1406 {
1407 struct bmc150_accel_data *data = iio_priv(indio_dev);
1408
1409 return bmc150_accel_set_power_state(data, true);
1410 }
1411
1412 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1413 {
1414 struct bmc150_accel_data *data = iio_priv(indio_dev);
1415 int ret = 0;
1416
1417 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1418 return iio_triggered_buffer_postenable(indio_dev);
1419
1420 mutex_lock(&data->mutex);
1421
1422 if (!data->watermark)
1423 goto out;
1424
1425 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1426 true);
1427 if (ret)
1428 goto out;
1429
1430 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1431
1432 ret = bmc150_accel_fifo_set_mode(data);
1433 if (ret) {
1434 data->fifo_mode = 0;
1435 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1436 false);
1437 }
1438
1439 out:
1440 mutex_unlock(&data->mutex);
1441
1442 return ret;
1443 }
1444
1445 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1446 {
1447 struct bmc150_accel_data *data = iio_priv(indio_dev);
1448
1449 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1450 return iio_triggered_buffer_predisable(indio_dev);
1451
1452 mutex_lock(&data->mutex);
1453
1454 if (!data->fifo_mode)
1455 goto out;
1456
1457 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1458 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1459 data->fifo_mode = 0;
1460 bmc150_accel_fifo_set_mode(data);
1461
1462 out:
1463 mutex_unlock(&data->mutex);
1464
1465 return 0;
1466 }
1467
1468 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1469 {
1470 struct bmc150_accel_data *data = iio_priv(indio_dev);
1471
1472 return bmc150_accel_set_power_state(data, false);
1473 }
1474
1475 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1476 .preenable = bmc150_accel_buffer_preenable,
1477 .postenable = bmc150_accel_buffer_postenable,
1478 .predisable = bmc150_accel_buffer_predisable,
1479 .postdisable = bmc150_accel_buffer_postdisable,
1480 };
1481
1482 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1483 {
1484 int ret, i;
1485 unsigned int val;
1486
1487 /*
1488 * Reset chip to get it in a known good state. A delay of 1.8ms after
1489 * reset is required according to the data sheets of supported chips.
1490 */
1491 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1492 BMC150_ACCEL_RESET_VAL);
1493 usleep_range(1800, 2500);
1494
1495 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1496 if (ret < 0) {
1497 dev_err(data->dev,
1498 "Error: Reading chip id\n");
1499 return ret;
1500 }
1501
1502 dev_dbg(data->dev, "Chip Id %x\n", val);
1503 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1504 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1505 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1506 break;
1507 }
1508 }
1509
1510 if (!data->chip_info) {
1511 dev_err(data->dev, "Invalid chip %x\n", val);
1512 return -ENODEV;
1513 }
1514
1515 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1516 if (ret < 0)
1517 return ret;
1518
1519 /* Set Bandwidth */
1520 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1521 if (ret < 0)
1522 return ret;
1523
1524 /* Set Default Range */
1525 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1526 BMC150_ACCEL_DEF_RANGE_4G);
1527 if (ret < 0) {
1528 dev_err(data->dev,
1529 "Error writing reg_pmu_range\n");
1530 return ret;
1531 }
1532
1533 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1534
1535 /* Set default slope duration and thresholds */
1536 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1537 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1538 ret = bmc150_accel_update_slope(data);
1539 if (ret < 0)
1540 return ret;
1541
1542 /* Set default as latched interrupts */
1543 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1544 BMC150_ACCEL_INT_MODE_LATCH_INT |
1545 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1546 if (ret < 0) {
1547 dev_err(data->dev,
1548 "Error writing reg_int_rst_latch\n");
1549 return ret;
1550 }
1551
1552 return 0;
1553 }
1554
1555 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1556 const char *name, bool block_supported)
1557 {
1558 struct bmc150_accel_data *data;
1559 struct iio_dev *indio_dev;
1560 int ret;
1561
1562 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1563 if (!indio_dev)
1564 return -ENOMEM;
1565
1566 data = iio_priv(indio_dev);
1567 dev_set_drvdata(dev, indio_dev);
1568 data->dev = dev;
1569 data->irq = irq;
1570
1571 data->regmap = regmap;
1572
1573 ret = bmc150_accel_chip_init(data);
1574 if (ret < 0)
1575 return ret;
1576
1577 mutex_init(&data->mutex);
1578
1579 indio_dev->dev.parent = dev;
1580 indio_dev->channels = data->chip_info->channels;
1581 indio_dev->num_channels = data->chip_info->num_channels;
1582 indio_dev->name = name ? name : data->chip_info->name;
1583 indio_dev->modes = INDIO_DIRECT_MODE;
1584 indio_dev->info = &bmc150_accel_info;
1585
1586 ret = iio_triggered_buffer_setup(indio_dev,
1587 &iio_pollfunc_store_time,
1588 bmc150_accel_trigger_handler,
1589 &bmc150_accel_buffer_ops);
1590 if (ret < 0) {
1591 dev_err(data->dev, "Failed: iio triggered buffer setup\n");
1592 return ret;
1593 }
1594
1595 if (data->irq > 0) {
1596 ret = devm_request_threaded_irq(
1597 data->dev, data->irq,
1598 bmc150_accel_irq_handler,
1599 bmc150_accel_irq_thread_handler,
1600 IRQF_TRIGGER_RISING,
1601 BMC150_ACCEL_IRQ_NAME,
1602 indio_dev);
1603 if (ret)
1604 goto err_buffer_cleanup;
1605
1606 /*
1607 * Set latched mode interrupt. While certain interrupts are
1608 * non-latched regardless of this settings (e.g. new data) we
1609 * want to use latch mode when we can to prevent interrupt
1610 * flooding.
1611 */
1612 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1613 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1614 if (ret < 0) {
1615 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1616 goto err_buffer_cleanup;
1617 }
1618
1619 bmc150_accel_interrupts_setup(indio_dev, data);
1620
1621 ret = bmc150_accel_triggers_setup(indio_dev, data);
1622 if (ret)
1623 goto err_buffer_cleanup;
1624
1625 if (block_supported) {
1626 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1627 indio_dev->info = &bmc150_accel_info_fifo;
1628 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1629 }
1630 }
1631
1632 ret = iio_device_register(indio_dev);
1633 if (ret < 0) {
1634 dev_err(dev, "Unable to register iio device\n");
1635 goto err_trigger_unregister;
1636 }
1637
1638 ret = pm_runtime_set_active(dev);
1639 if (ret)
1640 goto err_iio_unregister;
1641
1642 pm_runtime_enable(dev);
1643 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1644 pm_runtime_use_autosuspend(dev);
1645
1646 return 0;
1647
1648 err_iio_unregister:
1649 iio_device_unregister(indio_dev);
1650 err_trigger_unregister:
1651 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1652 err_buffer_cleanup:
1653 iio_triggered_buffer_cleanup(indio_dev);
1654
1655 return ret;
1656 }
1657 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1658
1659 int bmc150_accel_core_remove(struct device *dev)
1660 {
1661 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1662 struct bmc150_accel_data *data = iio_priv(indio_dev);
1663
1664 pm_runtime_disable(data->dev);
1665 pm_runtime_set_suspended(data->dev);
1666 pm_runtime_put_noidle(data->dev);
1667
1668 iio_device_unregister(indio_dev);
1669
1670 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1671
1672 iio_triggered_buffer_cleanup(indio_dev);
1673
1674 mutex_lock(&data->mutex);
1675 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1676 mutex_unlock(&data->mutex);
1677
1678 return 0;
1679 }
1680 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1681
1682 #ifdef CONFIG_PM_SLEEP
1683 static int bmc150_accel_suspend(struct device *dev)
1684 {
1685 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1686 struct bmc150_accel_data *data = iio_priv(indio_dev);
1687
1688 mutex_lock(&data->mutex);
1689 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1690 mutex_unlock(&data->mutex);
1691
1692 return 0;
1693 }
1694
1695 static int bmc150_accel_resume(struct device *dev)
1696 {
1697 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1698 struct bmc150_accel_data *data = iio_priv(indio_dev);
1699
1700 mutex_lock(&data->mutex);
1701 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1702 bmc150_accel_fifo_set_mode(data);
1703 mutex_unlock(&data->mutex);
1704
1705 return 0;
1706 }
1707 #endif
1708
1709 #ifdef CONFIG_PM
1710 static int bmc150_accel_runtime_suspend(struct device *dev)
1711 {
1712 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1713 struct bmc150_accel_data *data = iio_priv(indio_dev);
1714 int ret;
1715
1716 dev_dbg(data->dev, __func__);
1717 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1718 if (ret < 0)
1719 return -EAGAIN;
1720
1721 return 0;
1722 }
1723
1724 static int bmc150_accel_runtime_resume(struct device *dev)
1725 {
1726 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1727 struct bmc150_accel_data *data = iio_priv(indio_dev);
1728 int ret;
1729 int sleep_val;
1730
1731 dev_dbg(data->dev, __func__);
1732
1733 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1734 if (ret < 0)
1735 return ret;
1736 ret = bmc150_accel_fifo_set_mode(data);
1737 if (ret < 0)
1738 return ret;
1739
1740 sleep_val = bmc150_accel_get_startup_times(data);
1741 if (sleep_val < 20)
1742 usleep_range(sleep_val * 1000, 20000);
1743 else
1744 msleep_interruptible(sleep_val);
1745
1746 return 0;
1747 }
1748 #endif
1749
1750 const struct dev_pm_ops bmc150_accel_pm_ops = {
1751 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1752 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1753 bmc150_accel_runtime_resume, NULL)
1754 };
1755 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1756
1757 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1758 MODULE_LICENSE("GPL v2");
1759 MODULE_DESCRIPTION("BMC150 accelerometer driver");
Linux with added FPC-III support