drivers/iio/adc/rockchip_saradc.c

   1 /*
   2  * Rockchip Successive Approximation Register (SAR) A/D Converter
   3  * Copyright (C) 2014 ROCKCHIP, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/delay.h>
  25 #include <linux/reset.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/iio/iio.h>
  28
  29 #define SARADC_DATA                     0x00
  30
  31 #define SARADC_STAS                     0x04
  32 #define SARADC_STAS_BUSY                BIT(0)
  33
  34 #define SARADC_CTRL                     0x08
  35 #define SARADC_CTRL_IRQ_STATUS          BIT(6)
  36 #define SARADC_CTRL_IRQ_ENABLE          BIT(5)
  37 #define SARADC_CTRL_POWER_CTRL          BIT(3)
  38 #define SARADC_CTRL_CHN_MASK            0x7
  39
  40 #define SARADC_DLY_PU_SOC               0x0c
  41 #define SARADC_DLY_PU_SOC_MASK          0x3f
  42
  43 #define SARADC_TIMEOUT                  msecs_to_jiffies(100)
  44
  45 struct rockchip_saradc_data {
  46         int                             num_bits;
  47         const struct iio_chan_spec      *channels;
  48         int                             num_channels;
  49         unsigned long                   clk_rate;
  50 };
  51
  52 struct rockchip_saradc {
  53         void __iomem            *regs;
  54         struct clk              *pclk;
  55         struct clk              *clk;
  56         struct completion       completion;
  57         struct regulator        *vref;
  58         struct reset_control    *reset;
  59         const struct rockchip_saradc_data *data;
  60         u16                     last_val;
  61 };
  62
  63 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
  64                                     struct iio_chan_spec const *chan,
  65                                     int *val, int *val2, long mask)
  66 {
  67         struct rockchip_saradc *info = iio_priv(indio_dev);
  68         int ret;
  69
  70         switch (mask) {
  71         case IIO_CHAN_INFO_RAW:
  72                 mutex_lock(&indio_dev->mlock);
  73
  74                 reinit_completion(&info->completion);
  75
  76                 /* 8 clock periods as delay between power up and start cmd */
  77                 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
  78
  79                 /* Select the channel to be used and trigger conversion */
  80                 writel(SARADC_CTRL_POWER_CTRL
  81                                 | (chan->channel & SARADC_CTRL_CHN_MASK)
  82                                 | SARADC_CTRL_IRQ_ENABLE,
  83                        info->regs + SARADC_CTRL);
  84
  85                 if (!wait_for_completion_timeout(&info->completion,
  86                                                  SARADC_TIMEOUT)) {
  87                         writel_relaxed(0, info->regs + SARADC_CTRL);
  88                         mutex_unlock(&indio_dev->mlock);
  89                         return -ETIMEDOUT;
  90                 }
  91
  92                 *val = info->last_val;
  93                 mutex_unlock(&indio_dev->mlock);
  94                 return IIO_VAL_INT;
  95         case IIO_CHAN_INFO_SCALE:
  96                 ret = regulator_get_voltage(info->vref);
  97                 if (ret < 0) {
  98                         dev_err(&indio_dev->dev, "failed to get voltage\n");
  99                         return ret;
 100                 }
 101
 102                 *val = ret / 1000;
 103                 *val2 = info->data->num_bits;
 104                 return IIO_VAL_FRACTIONAL_LOG2;
 105         default:
 106                 return -EINVAL;
 107         }
 108 }
 109
 110 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
 111 {
 112         struct rockchip_saradc *info = (struct rockchip_saradc *)dev_id;
 113
 114         /* Read value */
 115         info->last_val = readl_relaxed(info->regs + SARADC_DATA);
 116         info->last_val &= GENMASK(info->data->num_bits - 1, 0);
 117
 118         /* Clear irq & power down adc */
 119         writel_relaxed(0, info->regs + SARADC_CTRL);
 120
 121         complete(&info->completion);
 122
 123         return IRQ_HANDLED;
 124 }
 125
 126 static const struct iio_info rockchip_saradc_iio_info = {
 127         .read_raw = rockchip_saradc_read_raw,
 128         .driver_module = THIS_MODULE,
 129 };
 130
 131 #define ADC_CHANNEL(_index, _id) {                              \
 132         .type = IIO_VOLTAGE,                                    \
 133         .indexed = 1,                                           \
 134         .channel = _index,                                      \
 135         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 136         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 137         .datasheet_name = _id,                                  \
 138 }
 139
 140 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
 141         ADC_CHANNEL(0, "adc0"),
 142         ADC_CHANNEL(1, "adc1"),
 143         ADC_CHANNEL(2, "adc2"),
 144 };
 145
 146 static const struct rockchip_saradc_data saradc_data = {
 147         .num_bits = 10,
 148         .channels = rockchip_saradc_iio_channels,
 149         .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
 150         .clk_rate = 1000000,
 151 };
 152
 153 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
 154         ADC_CHANNEL(0, "adc0"),
 155         ADC_CHANNEL(1, "adc1"),
 156 };
 157
 158 static const struct rockchip_saradc_data rk3066_tsadc_data = {
 159         .num_bits = 12,
 160         .channels = rockchip_rk3066_tsadc_iio_channels,
 161         .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
 162         .clk_rate = 50000,
 163 };
 164
 165 static const struct of_device_id rockchip_saradc_match[] = {
 166         {
 167                 .compatible = "rockchip,saradc",
 168                 .data = &saradc_data,
 169         }, {
 170                 .compatible = "rockchip,rk3066-tsadc",
 171                 .data = &rk3066_tsadc_data,
 172         },
 173         {},
 174 };
 175 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 176
 177 /**
 178  * Reset SARADC Controller.
 179  */
 180 static void rockchip_saradc_reset_controller(struct reset_control *reset)
 181 {
 182         reset_control_assert(reset);
 183         usleep_range(10, 20);
 184         reset_control_deassert(reset);
 185 }
 186
 187 static int rockchip_saradc_probe(struct platform_device *pdev)
 188 {
 189         struct rockchip_saradc *info = NULL;
 190         struct device_node *np = pdev->dev.of_node;
 191         struct iio_dev *indio_dev = NULL;
 192         struct resource *mem;
 193         const struct of_device_id *match;
 194         int ret;
 195         int irq;
 196
 197         if (!np)
 198                 return -ENODEV;
 199
 200         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
 201         if (!indio_dev) {
 202                 dev_err(&pdev->dev, "failed allocating iio device\n");
 203                 return -ENOMEM;
 204         }
 205         info = iio_priv(indio_dev);
 206
 207         match = of_match_device(rockchip_saradc_match, &pdev->dev);
 208         info->data = match->data;
 209
 210         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 211         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 212         if (IS_ERR(info->regs))
 213                 return PTR_ERR(info->regs);
 214
 215         /*
 216          * The reset should be an optional property, as it should work
 217          * with old devicetrees as well
 218          */
 219         info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
 220         if (IS_ERR(info->reset)) {
 221                 ret = PTR_ERR(info->reset);
 222                 if (ret != -ENOENT)
 223                         return ret;
 224
 225                 dev_dbg(&pdev->dev, "no reset control found\n");
 226                 info->reset = NULL;
 227         }
 228
 229         init_completion(&info->completion);
 230
 231         irq = platform_get_irq(pdev, 0);
 232         if (irq < 0) {
 233                 dev_err(&pdev->dev, "no irq resource?\n");
 234                 return irq;
 235         }
 236
 237         ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
 238                                0, dev_name(&pdev->dev), info);
 239         if (ret < 0) {
 240                 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
 241                 return ret;
 242         }
 243
 244         info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 245         if (IS_ERR(info->pclk)) {
 246                 dev_err(&pdev->dev, "failed to get pclk\n");
 247                 return PTR_ERR(info->pclk);
 248         }
 249
 250         info->clk = devm_clk_get(&pdev->dev, "saradc");
 251         if (IS_ERR(info->clk)) {
 252                 dev_err(&pdev->dev, "failed to get adc clock\n");
 253                 return PTR_ERR(info->clk);
 254         }
 255
 256         info->vref = devm_regulator_get(&pdev->dev, "vref");
 257         if (IS_ERR(info->vref)) {
 258                 dev_err(&pdev->dev, "failed to get regulator, %ld\n",
 259                         PTR_ERR(info->vref));
 260                 return PTR_ERR(info->vref);
 261         }
 262
 263         if (info->reset)
 264                 rockchip_saradc_reset_controller(info->reset);
 265
 266         /*
 267          * Use a default value for the converter clock.
 268          * This may become user-configurable in the future.
 269          */
 270         ret = clk_set_rate(info->clk, info->data->clk_rate);
 271         if (ret < 0) {
 272                 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
 273                 return ret;
 274         }
 275
 276         ret = regulator_enable(info->vref);
 277         if (ret < 0) {
 278                 dev_err(&pdev->dev, "failed to enable vref regulator\n");
 279                 return ret;
 280         }
 281
 282         ret = clk_prepare_enable(info->pclk);
 283         if (ret < 0) {
 284                 dev_err(&pdev->dev, "failed to enable pclk\n");
 285                 goto err_reg_voltage;
 286         }
 287
 288         ret = clk_prepare_enable(info->clk);
 289         if (ret < 0) {
 290                 dev_err(&pdev->dev, "failed to enable converter clock\n");
 291                 goto err_pclk;
 292         }
 293
 294         platform_set_drvdata(pdev, indio_dev);
 295
 296         indio_dev->name = dev_name(&pdev->dev);
 297         indio_dev->dev.parent = &pdev->dev;
 298         indio_dev->dev.of_node = pdev->dev.of_node;
 299         indio_dev->info = &rockchip_saradc_iio_info;
 300         indio_dev->modes = INDIO_DIRECT_MODE;
 301
 302         indio_dev->channels = info->data->channels;
 303         indio_dev->num_channels = info->data->num_channels;
 304
 305         ret = iio_device_register(indio_dev);
 306         if (ret)
 307                 goto err_clk;
 308
 309         return 0;
 310
 311 err_clk:
 312         clk_disable_unprepare(info->clk);
 313 err_pclk:
 314         clk_disable_unprepare(info->pclk);
 315 err_reg_voltage:
 316         regulator_disable(info->vref);
 317         return ret;
 318 }
 319
 320 static int rockchip_saradc_remove(struct platform_device *pdev)
 321 {
 322         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 323         struct rockchip_saradc *info = iio_priv(indio_dev);
 324
 325         iio_device_unregister(indio_dev);
 326         clk_disable_unprepare(info->clk);
 327         clk_disable_unprepare(info->pclk);
 328         regulator_disable(info->vref);
 329
 330         return 0;
 331 }
 332
 333 #ifdef CONFIG_PM_SLEEP
 334 static int rockchip_saradc_suspend(struct device *dev)
 335 {
 336         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 337         struct rockchip_saradc *info = iio_priv(indio_dev);
 338
 339         clk_disable_unprepare(info->clk);
 340         clk_disable_unprepare(info->pclk);
 341         regulator_disable(info->vref);
 342
 343         return 0;
 344 }
 345
 346 static int rockchip_saradc_resume(struct device *dev)
 347 {
 348         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 349         struct rockchip_saradc *info = iio_priv(indio_dev);
 350         int ret;
 351
 352         ret = regulator_enable(info->vref);
 353         if (ret)
 354                 return ret;
 355
 356         ret = clk_prepare_enable(info->pclk);
 357         if (ret)
 358                 return ret;
 359
 360         ret = clk_prepare_enable(info->clk);
 361         if (ret)
 362                 return ret;
 363
 364         return ret;
 365 }
 366 #endif
 367
 368 static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
 369                          rockchip_saradc_suspend, rockchip_saradc_resume);
 370
 371 static struct platform_driver rockchip_saradc_driver = {
 372         .probe          = rockchip_saradc_probe,
 373         .remove         = rockchip_saradc_remove,
 374         .driver         = {
 375                 .name   = "rockchip-saradc",
 376                 .of_match_table = rockchip_saradc_match,
 377                 .pm     = &rockchip_saradc_pm_ops,
 378         },
 379 };
 380
 381 module_platform_driver(rockchip_saradc_driver);
 382
 383 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
 384 MODULE_DESCRIPTION("Rockchip SARADC driver");
 385 MODULE_LICENSE("GPL v2");