dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / media / i2c / adv7183.c
blobe2dd1617662fb0042f4820cdf95022b371bff786
1 /*
2 * adv7183.c Analog Devices ADV7183 video decoder driver
4 * Copyright (c) 2011 Analog Devices Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/gpio.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28 #include <linux/videodev2.h>
30 #include <media/adv7183.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
34 #include "adv7183_regs.h"
36 struct adv7183 {
37 struct v4l2_subdev sd;
38 struct v4l2_ctrl_handler hdl;
40 v4l2_std_id std; /* Current set standard */
41 u32 input;
42 u32 output;
43 unsigned reset_pin;
44 unsigned oe_pin;
45 struct v4l2_mbus_framefmt fmt;
48 /* EXAMPLES USING 27 MHz CLOCK
49 * Mode 1 CVBS Input (Composite Video on AIN5)
50 * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
52 static const unsigned char adv7183_init_regs[] = {
53 ADV7183_IN_CTRL, 0x04, /* CVBS input on AIN5 */
54 ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
55 ADV7183_SHAP_FILT_CTRL, 0x41, /* Set CSFM to SH1 */
56 ADV7183_ADC_CTRL, 0x16, /* Power down ADC 1 and ADC 2 */
57 ADV7183_CTI_DNR_CTRL_4, 0x04, /* Set DNR threshold to 4 for flat response */
58 /* ADI recommended programming sequence */
59 ADV7183_ADI_CTRL, 0x80,
60 ADV7183_CTI_DNR_CTRL_4, 0x20,
61 0x52, 0x18,
62 0x58, 0xED,
63 0x77, 0xC5,
64 0x7C, 0x93,
65 0x7D, 0x00,
66 0xD0, 0x48,
67 0xD5, 0xA0,
68 0xD7, 0xEA,
69 ADV7183_SD_SATURATION_CR, 0x3E,
70 ADV7183_PAL_V_END, 0x3E,
71 ADV7183_PAL_F_TOGGLE, 0x0F,
72 ADV7183_ADI_CTRL, 0x00,
75 static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
77 return container_of(sd, struct adv7183, sd);
79 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
81 return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
84 static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
86 struct i2c_client *client = v4l2_get_subdevdata(sd);
88 return i2c_smbus_read_byte_data(client, reg);
91 static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
92 unsigned char value)
94 struct i2c_client *client = v4l2_get_subdevdata(sd);
96 return i2c_smbus_write_byte_data(client, reg, value);
99 static int adv7183_writeregs(struct v4l2_subdev *sd,
100 const unsigned char *regs, unsigned int num)
102 unsigned char reg, data;
103 unsigned int cnt = 0;
105 if (num & 0x1) {
106 v4l2_err(sd, "invalid regs array\n");
107 return -1;
110 while (cnt < num) {
111 reg = *regs++;
112 data = *regs++;
113 cnt += 2;
115 adv7183_write(sd, reg, data);
117 return 0;
120 static int adv7183_log_status(struct v4l2_subdev *sd)
122 struct adv7183 *decoder = to_adv7183(sd);
124 v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
125 adv7183_read(sd, ADV7183_IN_CTRL));
126 v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
127 adv7183_read(sd, ADV7183_VD_SEL));
128 v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
129 adv7183_read(sd, ADV7183_OUT_CTRL));
130 v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
131 adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
132 v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
133 adv7183_read(sd, ADV7183_AUTO_DET_EN));
134 v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
135 adv7183_read(sd, ADV7183_CONTRAST));
136 v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
137 adv7183_read(sd, ADV7183_BRIGHTNESS));
138 v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
139 adv7183_read(sd, ADV7183_HUE));
140 v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
141 adv7183_read(sd, ADV7183_DEF_Y));
142 v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
143 adv7183_read(sd, ADV7183_DEF_C));
144 v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
145 adv7183_read(sd, ADV7183_ADI_CTRL));
146 v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
147 adv7183_read(sd, ADV7183_POW_MANAGE));
148 v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
149 adv7183_read(sd, ADV7183_STATUS_1),
150 adv7183_read(sd, ADV7183_STATUS_2),
151 adv7183_read(sd, ADV7183_STATUS_3));
152 v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
153 adv7183_read(sd, ADV7183_IDENT));
154 v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
155 adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
156 v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
157 adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
158 v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
159 adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
160 adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
161 v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
162 adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
163 v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
164 adv7183_read(sd, ADV7183_ADI_CTRL_2));
165 v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
166 adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
167 v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
168 adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
169 v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
170 adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
171 v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
172 adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
173 adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
174 v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
175 adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
176 adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
177 v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
178 adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
179 adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
180 adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
181 v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
182 adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
183 adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
184 adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
185 v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
186 adv7183_read(sd, ADV7183_POLARITY));
187 v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
188 adv7183_read(sd, ADV7183_ADC_CTRL));
189 v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
190 adv7183_read(sd, ADV7183_SD_OFFSET_CB),
191 adv7183_read(sd, ADV7183_SD_OFFSET_CR));
192 v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
193 adv7183_read(sd, ADV7183_SD_SATURATION_CB),
194 adv7183_read(sd, ADV7183_SD_SATURATION_CR));
195 v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
196 adv7183_read(sd, ADV7183_DRIVE_STR));
197 v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
198 return 0;
201 static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
203 struct adv7183 *decoder = to_adv7183(sd);
205 *std = decoder->std;
206 return 0;
209 static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
211 struct adv7183 *decoder = to_adv7183(sd);
212 int reg;
214 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
215 if (std == V4L2_STD_PAL_60)
216 reg |= 0x60;
217 else if (std == V4L2_STD_NTSC_443)
218 reg |= 0x70;
219 else if (std == V4L2_STD_PAL_N)
220 reg |= 0x90;
221 else if (std == V4L2_STD_PAL_M)
222 reg |= 0xA0;
223 else if (std == V4L2_STD_PAL_Nc)
224 reg |= 0xC0;
225 else if (std & V4L2_STD_PAL)
226 reg |= 0x80;
227 else if (std & V4L2_STD_NTSC)
228 reg |= 0x50;
229 else if (std & V4L2_STD_SECAM)
230 reg |= 0xE0;
231 else
232 return -EINVAL;
233 adv7183_write(sd, ADV7183_IN_CTRL, reg);
235 decoder->std = std;
237 return 0;
240 static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
242 int reg;
244 reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
245 adv7183_write(sd, ADV7183_POW_MANAGE, reg);
246 /* wait 5ms before any further i2c writes are performed */
247 usleep_range(5000, 10000);
248 return 0;
251 static int adv7183_s_routing(struct v4l2_subdev *sd,
252 u32 input, u32 output, u32 config)
254 struct adv7183 *decoder = to_adv7183(sd);
255 int reg;
257 if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
258 return -EINVAL;
260 if (input != decoder->input) {
261 decoder->input = input;
262 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
263 switch (input) {
264 case ADV7183_COMPOSITE1:
265 reg |= 0x1;
266 break;
267 case ADV7183_COMPOSITE2:
268 reg |= 0x2;
269 break;
270 case ADV7183_COMPOSITE3:
271 reg |= 0x3;
272 break;
273 case ADV7183_COMPOSITE4:
274 reg |= 0x4;
275 break;
276 case ADV7183_COMPOSITE5:
277 reg |= 0x5;
278 break;
279 case ADV7183_COMPOSITE6:
280 reg |= 0xB;
281 break;
282 case ADV7183_COMPOSITE7:
283 reg |= 0xC;
284 break;
285 case ADV7183_COMPOSITE8:
286 reg |= 0xD;
287 break;
288 case ADV7183_COMPOSITE9:
289 reg |= 0xE;
290 break;
291 case ADV7183_COMPOSITE10:
292 reg |= 0xF;
293 break;
294 case ADV7183_SVIDEO0:
295 reg |= 0x6;
296 break;
297 case ADV7183_SVIDEO1:
298 reg |= 0x7;
299 break;
300 case ADV7183_SVIDEO2:
301 reg |= 0x8;
302 break;
303 case ADV7183_COMPONENT0:
304 reg |= 0x9;
305 break;
306 case ADV7183_COMPONENT1:
307 reg |= 0xA;
308 break;
309 default:
310 break;
312 adv7183_write(sd, ADV7183_IN_CTRL, reg);
315 if (output != decoder->output) {
316 decoder->output = output;
317 reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
318 switch (output) {
319 case ADV7183_16BIT_OUT:
320 reg |= 0x9;
321 break;
322 default:
323 reg |= 0xC;
324 break;
326 adv7183_write(sd, ADV7183_OUT_CTRL, reg);
329 return 0;
332 static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
334 struct v4l2_subdev *sd = to_sd(ctrl);
335 int val = ctrl->val;
337 switch (ctrl->id) {
338 case V4L2_CID_BRIGHTNESS:
339 if (val < 0)
340 val = 127 - val;
341 adv7183_write(sd, ADV7183_BRIGHTNESS, val);
342 break;
343 case V4L2_CID_CONTRAST:
344 adv7183_write(sd, ADV7183_CONTRAST, val);
345 break;
346 case V4L2_CID_SATURATION:
347 adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
348 adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
349 break;
350 case V4L2_CID_HUE:
351 adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
352 adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
353 break;
354 default:
355 return -EINVAL;
358 return 0;
361 static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
363 struct adv7183 *decoder = to_adv7183(sd);
364 int reg;
366 /* enable autodetection block */
367 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
368 adv7183_write(sd, ADV7183_IN_CTRL, reg);
370 /* wait autodetection switch */
371 mdelay(10);
373 /* get autodetection result */
374 reg = adv7183_read(sd, ADV7183_STATUS_1);
375 switch ((reg >> 0x4) & 0x7) {
376 case 0:
377 *std &= V4L2_STD_NTSC;
378 break;
379 case 1:
380 *std &= V4L2_STD_NTSC_443;
381 break;
382 case 2:
383 *std &= V4L2_STD_PAL_M;
384 break;
385 case 3:
386 *std &= V4L2_STD_PAL_60;
387 break;
388 case 4:
389 *std &= V4L2_STD_PAL;
390 break;
391 case 5:
392 *std &= V4L2_STD_SECAM;
393 break;
394 case 6:
395 *std &= V4L2_STD_PAL_Nc;
396 break;
397 case 7:
398 *std &= V4L2_STD_SECAM;
399 break;
400 default:
401 *std = V4L2_STD_UNKNOWN;
402 break;
405 /* after std detection, write back user set std */
406 adv7183_s_std(sd, decoder->std);
407 return 0;
410 static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
412 int reg;
414 *status = V4L2_IN_ST_NO_SIGNAL;
415 reg = adv7183_read(sd, ADV7183_STATUS_1);
416 if (reg < 0)
417 return reg;
418 if (reg & 0x1)
419 *status = 0;
420 return 0;
423 static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
424 struct v4l2_subdev_pad_config *cfg,
425 struct v4l2_subdev_mbus_code_enum *code)
427 if (code->pad || code->index > 0)
428 return -EINVAL;
430 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
431 return 0;
434 static int adv7183_set_fmt(struct v4l2_subdev *sd,
435 struct v4l2_subdev_pad_config *cfg,
436 struct v4l2_subdev_format *format)
438 struct adv7183 *decoder = to_adv7183(sd);
439 struct v4l2_mbus_framefmt *fmt = &format->format;
441 if (format->pad)
442 return -EINVAL;
444 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
445 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
446 if (decoder->std & V4L2_STD_525_60) {
447 fmt->field = V4L2_FIELD_SEQ_TB;
448 fmt->width = 720;
449 fmt->height = 480;
450 } else {
451 fmt->field = V4L2_FIELD_SEQ_BT;
452 fmt->width = 720;
453 fmt->height = 576;
455 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
456 decoder->fmt = *fmt;
457 else
458 cfg->try_fmt = *fmt;
459 return 0;
462 static int adv7183_get_fmt(struct v4l2_subdev *sd,
463 struct v4l2_subdev_pad_config *cfg,
464 struct v4l2_subdev_format *format)
466 struct adv7183 *decoder = to_adv7183(sd);
468 if (format->pad)
469 return -EINVAL;
471 format->format = decoder->fmt;
472 return 0;
475 static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
477 struct adv7183 *decoder = to_adv7183(sd);
479 if (enable)
480 gpio_set_value(decoder->oe_pin, 0);
481 else
482 gpio_set_value(decoder->oe_pin, 1);
483 udelay(1);
484 return 0;
487 #ifdef CONFIG_VIDEO_ADV_DEBUG
488 static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
490 reg->val = adv7183_read(sd, reg->reg & 0xff);
491 reg->size = 1;
492 return 0;
495 static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
497 adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
498 return 0;
500 #endif
502 static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
503 .s_ctrl = adv7183_s_ctrl,
506 static const struct v4l2_subdev_core_ops adv7183_core_ops = {
507 .log_status = adv7183_log_status,
508 .reset = adv7183_reset,
509 #ifdef CONFIG_VIDEO_ADV_DEBUG
510 .g_register = adv7183_g_register,
511 .s_register = adv7183_s_register,
512 #endif
515 static const struct v4l2_subdev_video_ops adv7183_video_ops = {
516 .g_std = adv7183_g_std,
517 .s_std = adv7183_s_std,
518 .s_routing = adv7183_s_routing,
519 .querystd = adv7183_querystd,
520 .g_input_status = adv7183_g_input_status,
521 .s_stream = adv7183_s_stream,
524 static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
525 .enum_mbus_code = adv7183_enum_mbus_code,
526 .get_fmt = adv7183_get_fmt,
527 .set_fmt = adv7183_set_fmt,
530 static const struct v4l2_subdev_ops adv7183_ops = {
531 .core = &adv7183_core_ops,
532 .video = &adv7183_video_ops,
533 .pad = &adv7183_pad_ops,
536 static int adv7183_probe(struct i2c_client *client,
537 const struct i2c_device_id *id)
539 struct adv7183 *decoder;
540 struct v4l2_subdev *sd;
541 struct v4l2_ctrl_handler *hdl;
542 int ret;
543 struct v4l2_subdev_format fmt = {
544 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
546 const unsigned *pin_array;
548 /* Check if the adapter supports the needed features */
549 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
550 return -EIO;
552 v4l_info(client, "chip found @ 0x%02x (%s)\n",
553 client->addr << 1, client->adapter->name);
555 pin_array = client->dev.platform_data;
556 if (pin_array == NULL)
557 return -EINVAL;
559 decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
560 if (decoder == NULL)
561 return -ENOMEM;
563 decoder->reset_pin = pin_array[0];
564 decoder->oe_pin = pin_array[1];
566 if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
567 GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
568 v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
569 return -EBUSY;
572 if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
573 GPIOF_OUT_INIT_HIGH,
574 "ADV7183 Output Enable")) {
575 v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
576 return -EBUSY;
579 sd = &decoder->sd;
580 v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
582 hdl = &decoder->hdl;
583 v4l2_ctrl_handler_init(hdl, 4);
584 v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
585 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
586 v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
587 V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
588 v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
589 V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
590 v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
591 V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
592 /* hook the control handler into the driver */
593 sd->ctrl_handler = hdl;
594 if (hdl->error) {
595 ret = hdl->error;
597 v4l2_ctrl_handler_free(hdl);
598 return ret;
601 /* v4l2 doesn't support an autodetect standard, pick PAL as default */
602 decoder->std = V4L2_STD_PAL;
603 decoder->input = ADV7183_COMPOSITE4;
604 decoder->output = ADV7183_8BIT_OUT;
606 /* reset chip */
607 /* reset pulse width at least 5ms */
608 mdelay(10);
609 gpio_set_value(decoder->reset_pin, 1);
610 /* wait 5ms before any further i2c writes are performed */
611 mdelay(5);
613 adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
614 adv7183_s_std(sd, decoder->std);
615 fmt.format.width = 720;
616 fmt.format.height = 576;
617 adv7183_set_fmt(sd, NULL, &fmt);
619 /* initialize the hardware to the default control values */
620 ret = v4l2_ctrl_handler_setup(hdl);
621 if (ret) {
622 v4l2_ctrl_handler_free(hdl);
623 return ret;
626 return 0;
629 static int adv7183_remove(struct i2c_client *client)
631 struct v4l2_subdev *sd = i2c_get_clientdata(client);
633 v4l2_device_unregister_subdev(sd);
634 v4l2_ctrl_handler_free(sd->ctrl_handler);
635 return 0;
638 static const struct i2c_device_id adv7183_id[] = {
639 {"adv7183", 0},
643 MODULE_DEVICE_TABLE(i2c, adv7183_id);
645 static struct i2c_driver adv7183_driver = {
646 .driver = {
647 .owner = THIS_MODULE,
648 .name = "adv7183",
650 .probe = adv7183_probe,
651 .remove = adv7183_remove,
652 .id_table = adv7183_id,
655 module_i2c_driver(adv7183_driver);
657 MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
658 MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
659 MODULE_LICENSE("GPL v2");