2 * Driver for MT9T001 CMOS Image Sensor from Aptina (Micron)
4 * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Based on the MT9M001 driver,
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/clk.h>
16 #include <linux/i2c.h>
17 #include <linux/log2.h>
18 #include <linux/module.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <linux/v4l2-mediabus.h>
24 #include <media/mt9t001.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-subdev.h>
29 #define MT9T001_PIXEL_ARRAY_HEIGHT 1568
30 #define MT9T001_PIXEL_ARRAY_WIDTH 2112
32 #define MT9T001_CHIP_VERSION 0x00
33 #define MT9T001_CHIP_ID 0x1621
34 #define MT9T001_ROW_START 0x01
35 #define MT9T001_ROW_START_MIN 0
36 #define MT9T001_ROW_START_DEF 20
37 #define MT9T001_ROW_START_MAX 1534
38 #define MT9T001_COLUMN_START 0x02
39 #define MT9T001_COLUMN_START_MIN 0
40 #define MT9T001_COLUMN_START_DEF 32
41 #define MT9T001_COLUMN_START_MAX 2046
42 #define MT9T001_WINDOW_HEIGHT 0x03
43 #define MT9T001_WINDOW_HEIGHT_MIN 1
44 #define MT9T001_WINDOW_HEIGHT_DEF 1535
45 #define MT9T001_WINDOW_HEIGHT_MAX 1567
46 #define MT9T001_WINDOW_WIDTH 0x04
47 #define MT9T001_WINDOW_WIDTH_MIN 1
48 #define MT9T001_WINDOW_WIDTH_DEF 2047
49 #define MT9T001_WINDOW_WIDTH_MAX 2111
50 #define MT9T001_HORIZONTAL_BLANKING 0x05
51 #define MT9T001_HORIZONTAL_BLANKING_MIN 21
52 #define MT9T001_HORIZONTAL_BLANKING_MAX 1023
53 #define MT9T001_VERTICAL_BLANKING 0x06
54 #define MT9T001_VERTICAL_BLANKING_MIN 3
55 #define MT9T001_VERTICAL_BLANKING_MAX 1023
56 #define MT9T001_OUTPUT_CONTROL 0x07
57 #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0)
58 #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1)
59 #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6)
60 #define MT9T001_OUTPUT_CONTROL_DEF 0x0002
61 #define MT9T001_SHUTTER_WIDTH_HIGH 0x08
62 #define MT9T001_SHUTTER_WIDTH_LOW 0x09
63 #define MT9T001_SHUTTER_WIDTH_MIN 1
64 #define MT9T001_SHUTTER_WIDTH_DEF 1561
65 #define MT9T001_SHUTTER_WIDTH_MAX (1024 * 1024)
66 #define MT9T001_PIXEL_CLOCK 0x0a
67 #define MT9T001_PIXEL_CLOCK_INVERT (1 << 15)
68 #define MT9T001_PIXEL_CLOCK_SHIFT_MASK (7 << 8)
69 #define MT9T001_PIXEL_CLOCK_SHIFT_SHIFT 8
70 #define MT9T001_PIXEL_CLOCK_DIVIDE_MASK (0x7f << 0)
71 #define MT9T001_FRAME_RESTART 0x0b
72 #define MT9T001_SHUTTER_DELAY 0x0c
73 #define MT9T001_SHUTTER_DELAY_MAX 2047
74 #define MT9T001_RESET 0x0d
75 #define MT9T001_READ_MODE1 0x1e
76 #define MT9T001_READ_MODE_SNAPSHOT (1 << 8)
77 #define MT9T001_READ_MODE_STROBE_ENABLE (1 << 9)
78 #define MT9T001_READ_MODE_STROBE_WIDTH (1 << 10)
79 #define MT9T001_READ_MODE_STROBE_OVERRIDE (1 << 11)
80 #define MT9T001_READ_MODE2 0x20
81 #define MT9T001_READ_MODE_BAD_FRAMES (1 << 0)
82 #define MT9T001_READ_MODE_LINE_VALID_CONTINUOUS (1 << 9)
83 #define MT9T001_READ_MODE_LINE_VALID_FRAME (1 << 10)
84 #define MT9T001_READ_MODE3 0x21
85 #define MT9T001_READ_MODE_GLOBAL_RESET (1 << 0)
86 #define MT9T001_READ_MODE_GHST_CTL (1 << 1)
87 #define MT9T001_ROW_ADDRESS_MODE 0x22
88 #define MT9T001_ROW_SKIP_MASK (7 << 0)
89 #define MT9T001_ROW_BIN_MASK (3 << 3)
90 #define MT9T001_ROW_BIN_SHIFT 3
91 #define MT9T001_COLUMN_ADDRESS_MODE 0x23
92 #define MT9T001_COLUMN_SKIP_MASK (7 << 0)
93 #define MT9T001_COLUMN_BIN_MASK (3 << 3)
94 #define MT9T001_COLUMN_BIN_SHIFT 3
95 #define MT9T001_GREEN1_GAIN 0x2b
96 #define MT9T001_BLUE_GAIN 0x2c
97 #define MT9T001_RED_GAIN 0x2d
98 #define MT9T001_GREEN2_GAIN 0x2e
99 #define MT9T001_TEST_DATA 0x32
100 #define MT9T001_GLOBAL_GAIN 0x35
101 #define MT9T001_GLOBAL_GAIN_MIN 8
102 #define MT9T001_GLOBAL_GAIN_MAX 1024
103 #define MT9T001_BLACK_LEVEL 0x49
104 #define MT9T001_ROW_BLACK_DEFAULT_OFFSET 0x4b
105 #define MT9T001_BLC_DELTA_THRESHOLDS 0x5d
106 #define MT9T001_CAL_THRESHOLDS 0x5f
107 #define MT9T001_GREEN1_OFFSET 0x60
108 #define MT9T001_GREEN2_OFFSET 0x61
109 #define MT9T001_BLACK_LEVEL_CALIBRATION 0x62
110 #define MT9T001_BLACK_LEVEL_OVERRIDE (1 << 0)
111 #define MT9T001_BLACK_LEVEL_DISABLE_OFFSET (1 << 1)
112 #define MT9T001_BLACK_LEVEL_RECALCULATE (1 << 12)
113 #define MT9T001_BLACK_LEVEL_LOCK_RED_BLUE (1 << 13)
114 #define MT9T001_BLACK_LEVEL_LOCK_GREEN (1 << 14)
115 #define MT9T001_RED_OFFSET 0x63
116 #define MT9T001_BLUE_OFFSET 0x64
119 struct v4l2_subdev subdev
;
120 struct media_pad pad
;
123 struct regulator_bulk_data regulators
[2];
125 struct mutex power_lock
; /* lock to protect power_count */
128 struct v4l2_mbus_framefmt format
;
129 struct v4l2_rect crop
;
131 struct v4l2_ctrl_handler ctrls
;
132 struct v4l2_ctrl
*gains
[4];
138 static inline struct mt9t001
*to_mt9t001(struct v4l2_subdev
*sd
)
140 return container_of(sd
, struct mt9t001
, subdev
);
143 static int mt9t001_read(struct i2c_client
*client
, u8 reg
)
145 return i2c_smbus_read_word_swapped(client
, reg
);
148 static int mt9t001_write(struct i2c_client
*client
, u8 reg
, u16 data
)
150 return i2c_smbus_write_word_swapped(client
, reg
, data
);
153 static int mt9t001_set_output_control(struct mt9t001
*mt9t001
, u16 clear
,
156 struct i2c_client
*client
= v4l2_get_subdevdata(&mt9t001
->subdev
);
157 u16 value
= (mt9t001
->output_control
& ~clear
) | set
;
160 if (value
== mt9t001
->output_control
)
163 ret
= mt9t001_write(client
, MT9T001_OUTPUT_CONTROL
, value
);
167 mt9t001
->output_control
= value
;
171 static int mt9t001_reset(struct mt9t001
*mt9t001
)
173 struct i2c_client
*client
= v4l2_get_subdevdata(&mt9t001
->subdev
);
176 /* Reset the chip and stop data read out */
177 ret
= mt9t001_write(client
, MT9T001_RESET
, 1);
181 ret
= mt9t001_write(client
, MT9T001_RESET
, 0);
185 mt9t001
->output_control
= MT9T001_OUTPUT_CONTROL_DEF
;
187 return mt9t001_set_output_control(mt9t001
,
188 MT9T001_OUTPUT_CONTROL_CHIP_ENABLE
,
192 static int mt9t001_power_on(struct mt9t001
*mt9t001
)
196 /* Bring up the supplies */
197 ret
= regulator_bulk_enable(ARRAY_SIZE(mt9t001
->regulators
),
198 mt9t001
->regulators
);
203 ret
= clk_prepare_enable(mt9t001
->clk
);
205 regulator_bulk_disable(ARRAY_SIZE(mt9t001
->regulators
),
206 mt9t001
->regulators
);
211 static void mt9t001_power_off(struct mt9t001
*mt9t001
)
213 regulator_bulk_disable(ARRAY_SIZE(mt9t001
->regulators
),
214 mt9t001
->regulators
);
216 clk_disable_unprepare(mt9t001
->clk
);
219 static int __mt9t001_set_power(struct mt9t001
*mt9t001
, bool on
)
221 struct i2c_client
*client
= v4l2_get_subdevdata(&mt9t001
->subdev
);
225 mt9t001_power_off(mt9t001
);
229 ret
= mt9t001_power_on(mt9t001
);
233 ret
= mt9t001_reset(mt9t001
);
235 dev_err(&client
->dev
, "Failed to reset the camera\n");
239 return v4l2_ctrl_handler_setup(&mt9t001
->ctrls
);
242 /* -----------------------------------------------------------------------------
243 * V4L2 subdev video operations
246 static struct v4l2_mbus_framefmt
*
247 __mt9t001_get_pad_format(struct mt9t001
*mt9t001
, struct v4l2_subdev_pad_config
*cfg
,
248 unsigned int pad
, enum v4l2_subdev_format_whence which
)
251 case V4L2_SUBDEV_FORMAT_TRY
:
252 return v4l2_subdev_get_try_format(&mt9t001
->subdev
, cfg
, pad
);
253 case V4L2_SUBDEV_FORMAT_ACTIVE
:
254 return &mt9t001
->format
;
260 static struct v4l2_rect
*
261 __mt9t001_get_pad_crop(struct mt9t001
*mt9t001
, struct v4l2_subdev_pad_config
*cfg
,
262 unsigned int pad
, enum v4l2_subdev_format_whence which
)
265 case V4L2_SUBDEV_FORMAT_TRY
:
266 return v4l2_subdev_get_try_crop(&mt9t001
->subdev
, cfg
, pad
);
267 case V4L2_SUBDEV_FORMAT_ACTIVE
:
268 return &mt9t001
->crop
;
274 static int mt9t001_s_stream(struct v4l2_subdev
*subdev
, int enable
)
276 const u16 mode
= MT9T001_OUTPUT_CONTROL_CHIP_ENABLE
;
277 struct i2c_client
*client
= v4l2_get_subdevdata(subdev
);
278 struct mt9t001_platform_data
*pdata
= client
->dev
.platform_data
;
279 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
280 struct v4l2_mbus_framefmt
*format
= &mt9t001
->format
;
281 struct v4l2_rect
*crop
= &mt9t001
->crop
;
287 return mt9t001_set_output_control(mt9t001
, mode
, 0);
289 /* Configure the pixel clock polarity */
290 if (pdata
->clk_pol
) {
291 ret
= mt9t001_write(client
, MT9T001_PIXEL_CLOCK
,
292 MT9T001_PIXEL_CLOCK_INVERT
);
297 /* Configure the window size and row/column bin */
298 hratio
= DIV_ROUND_CLOSEST(crop
->width
, format
->width
);
299 vratio
= DIV_ROUND_CLOSEST(crop
->height
, format
->height
);
301 ret
= mt9t001_write(client
, MT9T001_ROW_ADDRESS_MODE
, hratio
- 1);
305 ret
= mt9t001_write(client
, MT9T001_COLUMN_ADDRESS_MODE
, vratio
- 1);
309 ret
= mt9t001_write(client
, MT9T001_COLUMN_START
, crop
->left
);
313 ret
= mt9t001_write(client
, MT9T001_ROW_START
, crop
->top
);
317 ret
= mt9t001_write(client
, MT9T001_WINDOW_WIDTH
, crop
->width
- 1);
321 ret
= mt9t001_write(client
, MT9T001_WINDOW_HEIGHT
, crop
->height
- 1);
325 /* Switch to master "normal" mode */
326 return mt9t001_set_output_control(mt9t001
, 0, mode
);
329 static int mt9t001_enum_mbus_code(struct v4l2_subdev
*subdev
,
330 struct v4l2_subdev_pad_config
*cfg
,
331 struct v4l2_subdev_mbus_code_enum
*code
)
336 code
->code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
340 static int mt9t001_enum_frame_size(struct v4l2_subdev
*subdev
,
341 struct v4l2_subdev_pad_config
*cfg
,
342 struct v4l2_subdev_frame_size_enum
*fse
)
344 if (fse
->index
>= 8 || fse
->code
!= MEDIA_BUS_FMT_SGRBG10_1X10
)
347 fse
->min_width
= (MT9T001_WINDOW_WIDTH_DEF
+ 1) / fse
->index
;
348 fse
->max_width
= fse
->min_width
;
349 fse
->min_height
= (MT9T001_WINDOW_HEIGHT_DEF
+ 1) / fse
->index
;
350 fse
->max_height
= fse
->min_height
;
355 static int mt9t001_get_format(struct v4l2_subdev
*subdev
,
356 struct v4l2_subdev_pad_config
*cfg
,
357 struct v4l2_subdev_format
*format
)
359 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
361 format
->format
= *__mt9t001_get_pad_format(mt9t001
, cfg
, format
->pad
,
366 static int mt9t001_set_format(struct v4l2_subdev
*subdev
,
367 struct v4l2_subdev_pad_config
*cfg
,
368 struct v4l2_subdev_format
*format
)
370 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
371 struct v4l2_mbus_framefmt
*__format
;
372 struct v4l2_rect
*__crop
;
378 __crop
= __mt9t001_get_pad_crop(mt9t001
, cfg
, format
->pad
,
381 /* Clamp the width and height to avoid dividing by zero. */
382 width
= clamp_t(unsigned int, ALIGN(format
->format
.width
, 2),
383 max_t(unsigned int, __crop
->width
/ 8,
384 MT9T001_WINDOW_HEIGHT_MIN
+ 1),
386 height
= clamp_t(unsigned int, ALIGN(format
->format
.height
, 2),
387 max_t(unsigned int, __crop
->height
/ 8,
388 MT9T001_WINDOW_HEIGHT_MIN
+ 1),
391 hratio
= DIV_ROUND_CLOSEST(__crop
->width
, width
);
392 vratio
= DIV_ROUND_CLOSEST(__crop
->height
, height
);
394 __format
= __mt9t001_get_pad_format(mt9t001
, cfg
, format
->pad
,
396 __format
->width
= __crop
->width
/ hratio
;
397 __format
->height
= __crop
->height
/ vratio
;
399 format
->format
= *__format
;
404 static int mt9t001_get_selection(struct v4l2_subdev
*subdev
,
405 struct v4l2_subdev_pad_config
*cfg
,
406 struct v4l2_subdev_selection
*sel
)
408 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
410 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
413 sel
->r
= *__mt9t001_get_pad_crop(mt9t001
, cfg
, sel
->pad
, sel
->which
);
417 static int mt9t001_set_selection(struct v4l2_subdev
*subdev
,
418 struct v4l2_subdev_pad_config
*cfg
,
419 struct v4l2_subdev_selection
*sel
)
421 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
422 struct v4l2_mbus_framefmt
*__format
;
423 struct v4l2_rect
*__crop
;
424 struct v4l2_rect rect
;
426 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
429 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
432 rect
.left
= clamp(ALIGN(sel
->r
.left
, 2),
433 MT9T001_COLUMN_START_MIN
,
434 MT9T001_COLUMN_START_MAX
);
435 rect
.top
= clamp(ALIGN(sel
->r
.top
, 2),
436 MT9T001_ROW_START_MIN
,
437 MT9T001_ROW_START_MAX
);
438 rect
.width
= clamp_t(unsigned int, ALIGN(sel
->r
.width
, 2),
439 MT9T001_WINDOW_WIDTH_MIN
+ 1,
440 MT9T001_WINDOW_WIDTH_MAX
+ 1);
441 rect
.height
= clamp_t(unsigned int, ALIGN(sel
->r
.height
, 2),
442 MT9T001_WINDOW_HEIGHT_MIN
+ 1,
443 MT9T001_WINDOW_HEIGHT_MAX
+ 1);
445 rect
.width
= min_t(unsigned int, rect
.width
,
446 MT9T001_PIXEL_ARRAY_WIDTH
- rect
.left
);
447 rect
.height
= min_t(unsigned int, rect
.height
,
448 MT9T001_PIXEL_ARRAY_HEIGHT
- rect
.top
);
450 __crop
= __mt9t001_get_pad_crop(mt9t001
, cfg
, sel
->pad
, sel
->which
);
452 if (rect
.width
!= __crop
->width
|| rect
.height
!= __crop
->height
) {
453 /* Reset the output image size if the crop rectangle size has
456 __format
= __mt9t001_get_pad_format(mt9t001
, cfg
, sel
->pad
,
458 __format
->width
= rect
.width
;
459 __format
->height
= rect
.height
;
468 /* -----------------------------------------------------------------------------
469 * V4L2 subdev control operations
472 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
473 #define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
474 #define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
475 #define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
477 #define V4L2_CID_GAIN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1001)
478 #define V4L2_CID_GAIN_GREEN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1002)
479 #define V4L2_CID_GAIN_GREEN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1003)
480 #define V4L2_CID_GAIN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1004)
482 static u16
mt9t001_gain_value(s32
*gain
)
484 /* Gain is controlled by 2 analog stages and a digital stage. Valid
485 * values for the 3 stages are
488 * ------------------------------------------
489 * First analog stage x1 x2 1
490 * Second analog stage x1 x4 0.125
491 * Digital stage x1 x16 0.125
493 * To minimize noise, the gain stages should be used in the second
494 * analog stage, first analog stage, digital stage order. Gain from a
495 * previous stage should be pushed to its maximum value before the next
503 return (1 << 6) | (*gain
>> 1);
507 return ((*gain
- 64) << 5) | (1 << 6) | 32;
510 static int mt9t001_ctrl_freeze(struct mt9t001
*mt9t001
, bool freeze
)
512 return mt9t001_set_output_control(mt9t001
,
513 freeze
? 0 : MT9T001_OUTPUT_CONTROL_SYNC
,
514 freeze
? MT9T001_OUTPUT_CONTROL_SYNC
: 0);
517 static int mt9t001_s_ctrl(struct v4l2_ctrl
*ctrl
)
519 static const u8 gains
[4] = {
520 MT9T001_RED_GAIN
, MT9T001_GREEN1_GAIN
,
521 MT9T001_GREEN2_GAIN
, MT9T001_BLUE_GAIN
524 struct mt9t001
*mt9t001
=
525 container_of(ctrl
->handler
, struct mt9t001
, ctrls
);
526 struct i2c_client
*client
= v4l2_get_subdevdata(&mt9t001
->subdev
);
533 case V4L2_CID_GAIN_RED
:
534 case V4L2_CID_GAIN_GREEN_RED
:
535 case V4L2_CID_GAIN_GREEN_BLUE
:
536 case V4L2_CID_GAIN_BLUE
:
538 /* Disable control updates if more than one control has changed
541 for (i
= 0, count
= 0; i
< 4; ++i
) {
542 struct v4l2_ctrl
*gain
= mt9t001
->gains
[i
];
544 if (gain
->val
!= gain
->cur
.val
)
549 ret
= mt9t001_ctrl_freeze(mt9t001
, true);
554 /* Update the gain controls. */
555 for (i
= 0; i
< 4; ++i
) {
556 struct v4l2_ctrl
*gain
= mt9t001
->gains
[i
];
558 if (gain
->val
== gain
->cur
.val
)
561 value
= mt9t001_gain_value(&gain
->val
);
562 ret
= mt9t001_write(client
, gains
[i
], value
);
564 mt9t001_ctrl_freeze(mt9t001
, false);
569 /* Enable control updates. */
571 ret
= mt9t001_ctrl_freeze(mt9t001
, false);
578 case V4L2_CID_EXPOSURE
:
579 ret
= mt9t001_write(client
, MT9T001_SHUTTER_WIDTH_LOW
,
584 return mt9t001_write(client
, MT9T001_SHUTTER_WIDTH_HIGH
,
587 case V4L2_CID_TEST_PATTERN
:
588 return mt9t001_set_output_control(mt9t001
,
589 ctrl
->val
? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA
,
590 ctrl
->val
? MT9T001_OUTPUT_CONTROL_TEST_DATA
: 0);
592 case V4L2_CID_TEST_PATTERN_COLOR
:
593 return mt9t001_write(client
, MT9T001_TEST_DATA
, ctrl
->val
<< 2);
595 case V4L2_CID_BLACK_LEVEL_AUTO
:
596 value
= ctrl
->val
? 0 : MT9T001_BLACK_LEVEL_OVERRIDE
;
597 ret
= mt9t001_write(client
, MT9T001_BLACK_LEVEL_CALIBRATION
,
602 mt9t001
->black_level
= value
;
605 case V4L2_CID_BLACK_LEVEL_OFFSET
:
606 ret
= mt9t001_write(client
, MT9T001_GREEN1_OFFSET
, ctrl
->val
);
610 ret
= mt9t001_write(client
, MT9T001_GREEN2_OFFSET
, ctrl
->val
);
614 ret
= mt9t001_write(client
, MT9T001_RED_OFFSET
, ctrl
->val
);
618 return mt9t001_write(client
, MT9T001_BLUE_OFFSET
, ctrl
->val
);
620 case V4L2_CID_BLACK_LEVEL_CALIBRATE
:
621 return mt9t001_write(client
, MT9T001_BLACK_LEVEL_CALIBRATION
,
622 MT9T001_BLACK_LEVEL_RECALCULATE
|
623 mt9t001
->black_level
);
629 static struct v4l2_ctrl_ops mt9t001_ctrl_ops
= {
630 .s_ctrl
= mt9t001_s_ctrl
,
633 static const char * const mt9t001_test_pattern_menu
[] = {
638 static const struct v4l2_ctrl_config mt9t001_ctrls
[] = {
640 .ops
= &mt9t001_ctrl_ops
,
641 .id
= V4L2_CID_TEST_PATTERN_COLOR
,
642 .type
= V4L2_CTRL_TYPE_INTEGER
,
643 .name
= "Test Pattern Color",
650 .ops
= &mt9t001_ctrl_ops
,
651 .id
= V4L2_CID_BLACK_LEVEL_AUTO
,
652 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
653 .name
= "Black Level, Auto",
660 .ops
= &mt9t001_ctrl_ops
,
661 .id
= V4L2_CID_BLACK_LEVEL_OFFSET
,
662 .type
= V4L2_CTRL_TYPE_INTEGER
,
663 .name
= "Black Level, Offset",
670 .ops
= &mt9t001_ctrl_ops
,
671 .id
= V4L2_CID_BLACK_LEVEL_CALIBRATE
,
672 .type
= V4L2_CTRL_TYPE_BUTTON
,
673 .name
= "Black Level, Calibrate",
678 .flags
= V4L2_CTRL_FLAG_WRITE_ONLY
,
682 static const struct v4l2_ctrl_config mt9t001_gains
[] = {
684 .ops
= &mt9t001_ctrl_ops
,
685 .id
= V4L2_CID_GAIN_RED
,
686 .type
= V4L2_CTRL_TYPE_INTEGER
,
688 .min
= MT9T001_GLOBAL_GAIN_MIN
,
689 .max
= MT9T001_GLOBAL_GAIN_MAX
,
691 .def
= MT9T001_GLOBAL_GAIN_MIN
,
694 .ops
= &mt9t001_ctrl_ops
,
695 .id
= V4L2_CID_GAIN_GREEN_RED
,
696 .type
= V4L2_CTRL_TYPE_INTEGER
,
697 .name
= "Gain, Green (R)",
698 .min
= MT9T001_GLOBAL_GAIN_MIN
,
699 .max
= MT9T001_GLOBAL_GAIN_MAX
,
701 .def
= MT9T001_GLOBAL_GAIN_MIN
,
704 .ops
= &mt9t001_ctrl_ops
,
705 .id
= V4L2_CID_GAIN_GREEN_BLUE
,
706 .type
= V4L2_CTRL_TYPE_INTEGER
,
707 .name
= "Gain, Green (B)",
708 .min
= MT9T001_GLOBAL_GAIN_MIN
,
709 .max
= MT9T001_GLOBAL_GAIN_MAX
,
711 .def
= MT9T001_GLOBAL_GAIN_MIN
,
714 .ops
= &mt9t001_ctrl_ops
,
715 .id
= V4L2_CID_GAIN_BLUE
,
716 .type
= V4L2_CTRL_TYPE_INTEGER
,
717 .name
= "Gain, Blue",
718 .min
= MT9T001_GLOBAL_GAIN_MIN
,
719 .max
= MT9T001_GLOBAL_GAIN_MAX
,
721 .def
= MT9T001_GLOBAL_GAIN_MIN
,
726 /* -----------------------------------------------------------------------------
727 * V4L2 subdev core operations
730 static int mt9t001_set_power(struct v4l2_subdev
*subdev
, int on
)
732 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
735 mutex_lock(&mt9t001
->power_lock
);
737 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
738 * update the power state.
740 if (mt9t001
->power_count
== !on
) {
741 ret
= __mt9t001_set_power(mt9t001
, !!on
);
746 /* Update the power count. */
747 mt9t001
->power_count
+= on
? 1 : -1;
748 WARN_ON(mt9t001
->power_count
< 0);
751 mutex_unlock(&mt9t001
->power_lock
);
755 /* -----------------------------------------------------------------------------
756 * V4L2 subdev internal operations
759 static int mt9t001_registered(struct v4l2_subdev
*subdev
)
761 struct i2c_client
*client
= v4l2_get_subdevdata(subdev
);
762 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
766 ret
= mt9t001_power_on(mt9t001
);
768 dev_err(&client
->dev
, "MT9T001 power up failed\n");
772 /* Read out the chip version register */
773 data
= mt9t001_read(client
, MT9T001_CHIP_VERSION
);
774 mt9t001_power_off(mt9t001
);
776 if (data
!= MT9T001_CHIP_ID
) {
777 dev_err(&client
->dev
,
778 "MT9T001 not detected, wrong version 0x%04x\n", data
);
782 dev_info(&client
->dev
, "MT9T001 detected at address 0x%02x\n",
788 static int mt9t001_open(struct v4l2_subdev
*subdev
, struct v4l2_subdev_fh
*fh
)
790 struct v4l2_mbus_framefmt
*format
;
791 struct v4l2_rect
*crop
;
793 crop
= v4l2_subdev_get_try_crop(subdev
, fh
->pad
, 0);
794 crop
->left
= MT9T001_COLUMN_START_DEF
;
795 crop
->top
= MT9T001_ROW_START_DEF
;
796 crop
->width
= MT9T001_WINDOW_WIDTH_DEF
+ 1;
797 crop
->height
= MT9T001_WINDOW_HEIGHT_DEF
+ 1;
799 format
= v4l2_subdev_get_try_format(subdev
, fh
->pad
, 0);
800 format
->code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
801 format
->width
= MT9T001_WINDOW_WIDTH_DEF
+ 1;
802 format
->height
= MT9T001_WINDOW_HEIGHT_DEF
+ 1;
803 format
->field
= V4L2_FIELD_NONE
;
804 format
->colorspace
= V4L2_COLORSPACE_SRGB
;
806 return mt9t001_set_power(subdev
, 1);
809 static int mt9t001_close(struct v4l2_subdev
*subdev
, struct v4l2_subdev_fh
*fh
)
811 return mt9t001_set_power(subdev
, 0);
814 static struct v4l2_subdev_core_ops mt9t001_subdev_core_ops
= {
815 .s_power
= mt9t001_set_power
,
818 static struct v4l2_subdev_video_ops mt9t001_subdev_video_ops
= {
819 .s_stream
= mt9t001_s_stream
,
822 static struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops
= {
823 .enum_mbus_code
= mt9t001_enum_mbus_code
,
824 .enum_frame_size
= mt9t001_enum_frame_size
,
825 .get_fmt
= mt9t001_get_format
,
826 .set_fmt
= mt9t001_set_format
,
827 .get_selection
= mt9t001_get_selection
,
828 .set_selection
= mt9t001_set_selection
,
831 static struct v4l2_subdev_ops mt9t001_subdev_ops
= {
832 .core
= &mt9t001_subdev_core_ops
,
833 .video
= &mt9t001_subdev_video_ops
,
834 .pad
= &mt9t001_subdev_pad_ops
,
837 static struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops
= {
838 .registered
= mt9t001_registered
,
839 .open
= mt9t001_open
,
840 .close
= mt9t001_close
,
843 static int mt9t001_probe(struct i2c_client
*client
,
844 const struct i2c_device_id
*did
)
846 struct mt9t001_platform_data
*pdata
= client
->dev
.platform_data
;
847 struct mt9t001
*mt9t001
;
852 dev_err(&client
->dev
, "No platform data\n");
856 if (!i2c_check_functionality(client
->adapter
,
857 I2C_FUNC_SMBUS_WORD_DATA
)) {
858 dev_warn(&client
->adapter
->dev
,
859 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
863 mt9t001
= devm_kzalloc(&client
->dev
, sizeof(*mt9t001
), GFP_KERNEL
);
867 mutex_init(&mt9t001
->power_lock
);
868 mt9t001
->output_control
= MT9T001_OUTPUT_CONTROL_DEF
;
870 mt9t001
->regulators
[0].supply
= "vdd";
871 mt9t001
->regulators
[1].supply
= "vaa";
873 ret
= devm_regulator_bulk_get(&client
->dev
, 2, mt9t001
->regulators
);
875 dev_err(&client
->dev
, "Unable to get regulators\n");
879 mt9t001
->clk
= devm_clk_get(&client
->dev
, NULL
);
880 if (IS_ERR(mt9t001
->clk
)) {
881 dev_err(&client
->dev
, "Unable to get clock\n");
882 return PTR_ERR(mt9t001
->clk
);
885 v4l2_ctrl_handler_init(&mt9t001
->ctrls
, ARRAY_SIZE(mt9t001_ctrls
) +
886 ARRAY_SIZE(mt9t001_gains
) + 4);
888 v4l2_ctrl_new_std(&mt9t001
->ctrls
, &mt9t001_ctrl_ops
,
889 V4L2_CID_EXPOSURE
, MT9T001_SHUTTER_WIDTH_MIN
,
890 MT9T001_SHUTTER_WIDTH_MAX
, 1,
891 MT9T001_SHUTTER_WIDTH_DEF
);
892 v4l2_ctrl_new_std(&mt9t001
->ctrls
, &mt9t001_ctrl_ops
,
893 V4L2_CID_BLACK_LEVEL
, 1, 1, 1, 1);
894 v4l2_ctrl_new_std(&mt9t001
->ctrls
, &mt9t001_ctrl_ops
,
895 V4L2_CID_PIXEL_RATE
, pdata
->ext_clk
, pdata
->ext_clk
,
897 v4l2_ctrl_new_std_menu_items(&mt9t001
->ctrls
, &mt9t001_ctrl_ops
,
898 V4L2_CID_TEST_PATTERN
,
899 ARRAY_SIZE(mt9t001_test_pattern_menu
) - 1, 0,
900 0, mt9t001_test_pattern_menu
);
902 for (i
= 0; i
< ARRAY_SIZE(mt9t001_ctrls
); ++i
)
903 v4l2_ctrl_new_custom(&mt9t001
->ctrls
, &mt9t001_ctrls
[i
], NULL
);
905 for (i
= 0; i
< ARRAY_SIZE(mt9t001_gains
); ++i
)
906 mt9t001
->gains
[i
] = v4l2_ctrl_new_custom(&mt9t001
->ctrls
,
907 &mt9t001_gains
[i
], NULL
);
909 v4l2_ctrl_cluster(ARRAY_SIZE(mt9t001_gains
), mt9t001
->gains
);
911 mt9t001
->subdev
.ctrl_handler
= &mt9t001
->ctrls
;
913 if (mt9t001
->ctrls
.error
) {
914 printk(KERN_INFO
"%s: control initialization error %d\n",
915 __func__
, mt9t001
->ctrls
.error
);
920 mt9t001
->crop
.left
= MT9T001_COLUMN_START_DEF
;
921 mt9t001
->crop
.top
= MT9T001_ROW_START_DEF
;
922 mt9t001
->crop
.width
= MT9T001_WINDOW_WIDTH_DEF
+ 1;
923 mt9t001
->crop
.height
= MT9T001_WINDOW_HEIGHT_DEF
+ 1;
925 mt9t001
->format
.code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
926 mt9t001
->format
.width
= MT9T001_WINDOW_WIDTH_DEF
+ 1;
927 mt9t001
->format
.height
= MT9T001_WINDOW_HEIGHT_DEF
+ 1;
928 mt9t001
->format
.field
= V4L2_FIELD_NONE
;
929 mt9t001
->format
.colorspace
= V4L2_COLORSPACE_SRGB
;
931 v4l2_i2c_subdev_init(&mt9t001
->subdev
, client
, &mt9t001_subdev_ops
);
932 mt9t001
->subdev
.internal_ops
= &mt9t001_subdev_internal_ops
;
933 mt9t001
->subdev
.flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
935 mt9t001
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
936 ret
= media_entity_init(&mt9t001
->subdev
.entity
, 1, &mt9t001
->pad
, 0);
940 v4l2_ctrl_handler_free(&mt9t001
->ctrls
);
941 media_entity_cleanup(&mt9t001
->subdev
.entity
);
947 static int mt9t001_remove(struct i2c_client
*client
)
949 struct v4l2_subdev
*subdev
= i2c_get_clientdata(client
);
950 struct mt9t001
*mt9t001
= to_mt9t001(subdev
);
952 v4l2_ctrl_handler_free(&mt9t001
->ctrls
);
953 v4l2_device_unregister_subdev(subdev
);
954 media_entity_cleanup(&subdev
->entity
);
958 static const struct i2c_device_id mt9t001_id
[] = {
962 MODULE_DEVICE_TABLE(i2c
, mt9t001_id
);
964 static struct i2c_driver mt9t001_driver
= {
968 .probe
= mt9t001_probe
,
969 .remove
= mt9t001_remove
,
970 .id_table
= mt9t001_id
,
973 module_i2c_driver(mt9t001_driver
);
975 MODULE_DESCRIPTION("Aptina (Micron) MT9T001 Camera driver");
976 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
977 MODULE_LICENSE("GPL");