dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / media / i2c / s5c73m3 / s5c73m3.h
blob13aed59f0f5dac48f2c5788a7df1366f222c5fc6
1 /*
2 * Samsung LSI S5C73M3 8M pixel camera driver
4 * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 * Andrzej Hajda <a.hajda@samsung.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #ifndef S5C73M3_H_
18 #define S5C73M3_H_
20 #include <linux/clk.h>
21 #include <linux/kernel.h>
22 #include <linux/regulator/consumer.h>
23 #include <media/v4l2-common.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/s5c73m3.h>
28 #define DRIVER_NAME "S5C73M3"
30 #define S5C73M3_ISP_FMT MEDIA_BUS_FMT_VYUY8_2X8
31 #define S5C73M3_JPEG_FMT MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8
33 /* Subdevs pad index definitions */
34 enum s5c73m3_pads {
35 S5C73M3_ISP_PAD,
36 S5C73M3_JPEG_PAD,
37 S5C73M3_NUM_PADS
40 enum s5c73m3_oif_pads {
41 OIF_ISP_PAD,
42 OIF_JPEG_PAD,
43 OIF_SOURCE_PAD,
44 OIF_NUM_PADS
47 #define S5C73M3_SENSOR_FW_LEN 6
48 #define S5C73M3_SENSOR_TYPE_LEN 12
50 #define S5C73M3_REG(_addrh, _addrl) (((_addrh) << 16) | _addrl)
52 #define AHB_MSB_ADDR_PTR 0xfcfc
53 #define REG_CMDWR_ADDRH 0x0050
54 #define REG_CMDWR_ADDRL 0x0054
55 #define REG_CMDRD_ADDRH 0x0058
56 #define REG_CMDRD_ADDRL 0x005c
57 #define REG_CMDBUF_ADDR 0x0f14
59 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
60 #define SEQ_END_PLL (1<<0x0)
61 #define SEQ_END_SENSOR (1<<0x1)
62 #define SEQ_END_GPIO (1<<0x2)
63 #define SEQ_END_FROM (1<<0x3)
64 #define SEQ_END_STABLE_AE_AWB (1<<0x4)
65 #define SEQ_END_READY_I2C_CMD (1<<0x5)
67 #define REG_I2C_STATUS S5C73M3_REG(0x0009, 0x599E)
68 #define I2C_STATUS_CIS_I2C (1<<0x0)
69 #define I2C_STATUS_AF_INIT (1<<0x1)
70 #define I2C_STATUS_CAL_DATA (1<<0x2)
71 #define I2C_STATUS_FRAME_COUNT (1<<0x3)
72 #define I2C_STATUS_FROM_INIT (1<<0x4)
73 #define I2C_STATUS_I2C_CIS_STREAM_OFF (1<<0x5)
74 #define I2C_STATUS_I2C_N_CMD_OVER (1<<0x6)
75 #define I2C_STATUS_I2C_N_CMD_MISMATCH (1<<0x7)
76 #define I2C_STATUS_CHECK_BIN_CRC (1<<0x8)
77 #define I2C_STATUS_EXCEPTION (1<<0x9)
78 #define I2C_STATUS_INIF_INIT_STATE (0x8)
80 #define REG_STATUS S5C73M3_REG(0x0009, 0x5080)
81 #define REG_STATUS_BOOT_SUB_MAIN_ENTER 0xff01
82 #define REG_STATUS_BOOT_SRAM_TIMING_OK 0xff02
83 #define REG_STATUS_BOOT_INTERRUPTS_EN 0xff03
84 #define REG_STATUS_BOOT_R_PLL_DONE 0xff04
85 #define REG_STATUS_BOOT_R_PLL_LOCKTIME_DONE 0xff05
86 #define REG_STATUS_BOOT_DELAY_COUNT_DONE 0xff06
87 #define REG_STATUS_BOOT_I_PLL_DONE 0xff07
88 #define REG_STATUS_BOOT_I_PLL_LOCKTIME_DONE 0xff08
89 #define REG_STATUS_BOOT_PLL_INIT_OK 0xff09
90 #define REG_STATUS_BOOT_SENSOR_INIT_OK 0xff0a
91 #define REG_STATUS_BOOT_GPIO_SETTING_OK 0xff0b
92 #define REG_STATUS_BOOT_READ_CAL_DATA_OK 0xff0c
93 #define REG_STATUS_BOOT_STABLE_AE_AWB_OK 0xff0d
94 #define REG_STATUS_ISP_COMMAND_COMPLETED 0xffff
95 #define REG_STATUS_EXCEPTION_OCCURED 0xdead
97 #define COMM_RESULT_OFFSET S5C73M3_REG(0x0009, 0x5000)
99 #define COMM_IMG_OUTPUT 0x0902
100 #define COMM_IMG_OUTPUT_HDR 0x0008
101 #define COMM_IMG_OUTPUT_YUV 0x0009
102 #define COMM_IMG_OUTPUT_INTERLEAVED 0x000d
104 #define COMM_STILL_PRE_FLASH 0x0a00
105 #define COMM_STILL_PRE_FLASH_FIRE 0x0000
106 #define COMM_STILL_PRE_FLASH_NON_FIRED 0x0000
107 #define COMM_STILL_PRE_FLASH_FIRED 0x0001
109 #define COMM_STILL_MAIN_FLASH 0x0a02
110 #define COMM_STILL_MAIN_FLASH_CANCEL 0x0001
111 #define COMM_STILL_MAIN_FLASH_FIRE 0x0002
113 #define COMM_ZOOM_STEP 0x0b00
115 #define COMM_IMAGE_EFFECT 0x0b0a
116 #define COMM_IMAGE_EFFECT_NONE 0x0001
117 #define COMM_IMAGE_EFFECT_NEGATIVE 0x0002
118 #define COMM_IMAGE_EFFECT_AQUA 0x0003
119 #define COMM_IMAGE_EFFECT_SEPIA 0x0004
120 #define COMM_IMAGE_EFFECT_MONO 0x0005
122 #define COMM_IMAGE_QUALITY 0x0b0c
123 #define COMM_IMAGE_QUALITY_SUPERFINE 0x0000
124 #define COMM_IMAGE_QUALITY_FINE 0x0001
125 #define COMM_IMAGE_QUALITY_NORMAL 0x0002
127 #define COMM_FLASH_MODE 0x0b0e
128 #define COMM_FLASH_MODE_OFF 0x0000
129 #define COMM_FLASH_MODE_ON 0x0001
130 #define COMM_FLASH_MODE_AUTO 0x0002
132 #define COMM_FLASH_STATUS 0x0b80
133 #define COMM_FLASH_STATUS_OFF 0x0001
134 #define COMM_FLASH_STATUS_ON 0x0002
135 #define COMM_FLASH_STATUS_AUTO 0x0003
137 #define COMM_FLASH_TORCH 0x0b12
138 #define COMM_FLASH_TORCH_OFF 0x0000
139 #define COMM_FLASH_TORCH_ON 0x0001
141 #define COMM_AE_NEEDS_FLASH 0x0cba
142 #define COMM_AE_NEEDS_FLASH_OFF 0x0000
143 #define COMM_AE_NEEDS_FLASH_ON 0x0001
145 #define COMM_CHG_MODE 0x0b10
146 #define COMM_CHG_MODE_NEW 0x8000
147 #define COMM_CHG_MODE_SUBSAMPLING_HALF 0x2000
148 #define COMM_CHG_MODE_SUBSAMPLING_QUARTER 0x4000
150 #define COMM_CHG_MODE_YUV_320_240 0x0001
151 #define COMM_CHG_MODE_YUV_640_480 0x0002
152 #define COMM_CHG_MODE_YUV_880_720 0x0003
153 #define COMM_CHG_MODE_YUV_960_720 0x0004
154 #define COMM_CHG_MODE_YUV_1184_666 0x0005
155 #define COMM_CHG_MODE_YUV_1280_720 0x0006
156 #define COMM_CHG_MODE_YUV_1536_864 0x0007
157 #define COMM_CHG_MODE_YUV_1600_1200 0x0008
158 #define COMM_CHG_MODE_YUV_1632_1224 0x0009
159 #define COMM_CHG_MODE_YUV_1920_1080 0x000a
160 #define COMM_CHG_MODE_YUV_1920_1440 0x000b
161 #define COMM_CHG_MODE_YUV_2304_1296 0x000c
162 #define COMM_CHG_MODE_YUV_3264_2448 0x000d
163 #define COMM_CHG_MODE_YUV_352_288 0x000e
164 #define COMM_CHG_MODE_YUV_1008_672 0x000f
166 #define COMM_CHG_MODE_JPEG_640_480 0x0010
167 #define COMM_CHG_MODE_JPEG_800_450 0x0020
168 #define COMM_CHG_MODE_JPEG_800_600 0x0030
169 #define COMM_CHG_MODE_JPEG_1280_720 0x0040
170 #define COMM_CHG_MODE_JPEG_1280_960 0x0050
171 #define COMM_CHG_MODE_JPEG_1600_900 0x0060
172 #define COMM_CHG_MODE_JPEG_1600_1200 0x0070
173 #define COMM_CHG_MODE_JPEG_2048_1152 0x0080
174 #define COMM_CHG_MODE_JPEG_2048_1536 0x0090
175 #define COMM_CHG_MODE_JPEG_2560_1440 0x00a0
176 #define COMM_CHG_MODE_JPEG_2560_1920 0x00b0
177 #define COMM_CHG_MODE_JPEG_3264_2176 0x00c0
178 #define COMM_CHG_MODE_JPEG_1024_768 0x00d0
179 #define COMM_CHG_MODE_JPEG_3264_1836 0x00e0
180 #define COMM_CHG_MODE_JPEG_3264_2448 0x00f0
182 #define COMM_AF_CON 0x0e00
183 #define COMM_AF_CON_STOP 0x0000
184 #define COMM_AF_CON_SCAN 0x0001 /* Full Search */
185 #define COMM_AF_CON_START 0x0002 /* Fast Search */
187 #define COMM_AF_CAL 0x0e06
188 #define COMM_AF_TOUCH_AF 0x0e0a
190 #define REG_AF_STATUS S5C73M3_REG(0x0009, 0x5e80)
191 #define REG_CAF_STATUS_FIND_SEARCH_DIR 0x0001
192 #define REG_CAF_STATUS_FOCUSING 0x0002
193 #define REG_CAF_STATUS_FOCUSED 0x0003
194 #define REG_CAF_STATUS_UNFOCUSED 0x0004
195 #define REG_AF_STATUS_INVALID 0x0010
196 #define REG_AF_STATUS_FOCUSING 0x0020
197 #define REG_AF_STATUS_FOCUSED 0x0030
198 #define REG_AF_STATUS_UNFOCUSED 0x0040
200 #define REG_AF_TOUCH_POSITION S5C73M3_REG(0x0009, 0x5e8e)
201 #define COMM_AF_FACE_ZOOM 0x0e10
203 #define COMM_AF_MODE 0x0e02
204 #define COMM_AF_MODE_NORMAL 0x0000
205 #define COMM_AF_MODE_MACRO 0x0001
206 #define COMM_AF_MODE_MOVIE_CAF_START 0x0002
207 #define COMM_AF_MODE_MOVIE_CAF_STOP 0x0003
208 #define COMM_AF_MODE_PREVIEW_CAF_START 0x0004
209 #define COMM_AF_MODE_PREVIEW_CAF_STOP 0x0005
211 #define COMM_AF_SOFTLANDING 0x0e16
212 #define COMM_AF_SOFTLANDING_ON 0x0000
213 #define COMM_AF_SOFTLANDING_RES_COMPLETE 0x0001
215 #define COMM_FACE_DET 0x0e0c
216 #define COMM_FACE_DET_OFF 0x0000
217 #define COMM_FACE_DET_ON 0x0001
219 #define COMM_FACE_DET_OSD 0x0e0e
220 #define COMM_FACE_DET_OSD_OFF 0x0000
221 #define COMM_FACE_DET_OSD_ON 0x0001
223 #define COMM_AE_CON 0x0c00
224 #define COMM_AE_STOP 0x0000 /* lock */
225 #define COMM_AE_START 0x0001 /* unlock */
227 #define COMM_ISO 0x0c02
228 #define COMM_ISO_AUTO 0x0000
229 #define COMM_ISO_100 0x0001
230 #define COMM_ISO_200 0x0002
231 #define COMM_ISO_400 0x0003
232 #define COMM_ISO_800 0x0004
233 #define COMM_ISO_SPORTS 0x0005
234 #define COMM_ISO_NIGHT 0x0006
235 #define COMM_ISO_INDOOR 0x0007
237 /* 0x00000 (-2.0 EV)...0x0008 (2.0 EV), 0.5EV step */
238 #define COMM_EV 0x0c04
240 #define COMM_METERING 0x0c06
241 #define COMM_METERING_CENTER 0x0000
242 #define COMM_METERING_SPOT 0x0001
243 #define COMM_METERING_AVERAGE 0x0002
244 #define COMM_METERING_SMART 0x0003
246 #define COMM_WDR 0x0c08
247 #define COMM_WDR_OFF 0x0000
248 #define COMM_WDR_ON 0x0001
250 #define COMM_FLICKER_MODE 0x0c12
251 #define COMM_FLICKER_NONE 0x0000
252 #define COMM_FLICKER_MANUAL_50HZ 0x0001
253 #define COMM_FLICKER_MANUAL_60HZ 0x0002
254 #define COMM_FLICKER_AUTO 0x0003
255 #define COMM_FLICKER_AUTO_50HZ 0x0004
256 #define COMM_FLICKER_AUTO_60HZ 0x0005
258 #define COMM_FRAME_RATE 0x0c1e
259 #define COMM_FRAME_RATE_AUTO_SET 0x0000
260 #define COMM_FRAME_RATE_FIXED_30FPS 0x0002
261 #define COMM_FRAME_RATE_FIXED_20FPS 0x0003
262 #define COMM_FRAME_RATE_FIXED_15FPS 0x0004
263 #define COMM_FRAME_RATE_FIXED_60FPS 0x0007
264 #define COMM_FRAME_RATE_FIXED_120FPS 0x0008
265 #define COMM_FRAME_RATE_FIXED_7FPS 0x0009
266 #define COMM_FRAME_RATE_FIXED_10FPS 0x000a
267 #define COMM_FRAME_RATE_FIXED_90FPS 0x000b
268 #define COMM_FRAME_RATE_ANTI_SHAKE 0x0013
270 /* 0x0000...0x0004 -> sharpness: 0, 1, 2, -1, -2 */
271 #define COMM_SHARPNESS 0x0c14
273 /* 0x0000...0x0004 -> saturation: 0, 1, 2, -1, -2 */
274 #define COMM_SATURATION 0x0c16
276 /* 0x0000...0x0004 -> contrast: 0, 1, 2, -1, -2 */
277 #define COMM_CONTRAST 0x0c18
279 #define COMM_SCENE_MODE 0x0c1a
280 #define COMM_SCENE_MODE_NONE 0x0000
281 #define COMM_SCENE_MODE_PORTRAIT 0x0001
282 #define COMM_SCENE_MODE_LANDSCAPE 0x0002
283 #define COMM_SCENE_MODE_SPORTS 0x0003
284 #define COMM_SCENE_MODE_INDOOR 0x0004
285 #define COMM_SCENE_MODE_BEACH 0x0005
286 #define COMM_SCENE_MODE_SUNSET 0x0006
287 #define COMM_SCENE_MODE_DAWN 0x0007
288 #define COMM_SCENE_MODE_FALL 0x0008
289 #define COMM_SCENE_MODE_NIGHT 0x0009
290 #define COMM_SCENE_MODE_AGAINST_LIGHT 0x000a
291 #define COMM_SCENE_MODE_FIRE 0x000b
292 #define COMM_SCENE_MODE_TEXT 0x000c
293 #define COMM_SCENE_MODE_CANDLE 0x000d
295 #define COMM_AE_AUTO_BRACKET 0x0b14
296 #define COMM_AE_AUTO_BRAKET_EV05 0x0080
297 #define COMM_AE_AUTO_BRAKET_EV10 0x0100
298 #define COMM_AE_AUTO_BRAKET_EV15 0x0180
299 #define COMM_AE_AUTO_BRAKET_EV20 0x0200
301 #define COMM_SENSOR_STREAMING 0x090a
302 #define COMM_SENSOR_STREAMING_OFF 0x0000
303 #define COMM_SENSOR_STREAMING_ON 0x0001
305 #define COMM_AWB_MODE 0x0d02
306 #define COMM_AWB_MODE_INCANDESCENT 0x0000
307 #define COMM_AWB_MODE_FLUORESCENT1 0x0001
308 #define COMM_AWB_MODE_FLUORESCENT2 0x0002
309 #define COMM_AWB_MODE_DAYLIGHT 0x0003
310 #define COMM_AWB_MODE_CLOUDY 0x0004
311 #define COMM_AWB_MODE_AUTO 0x0005
313 #define COMM_AWB_CON 0x0d00
314 #define COMM_AWB_STOP 0x0000 /* lock */
315 #define COMM_AWB_START 0x0001 /* unlock */
317 #define COMM_FW_UPDATE 0x0906
318 #define COMM_FW_UPDATE_NOT_READY 0x0000
319 #define COMM_FW_UPDATE_SUCCESS 0x0005
320 #define COMM_FW_UPDATE_FAIL 0x0007
321 #define COMM_FW_UPDATE_BUSY 0xffff
324 #define S5C73M3_MAX_SUPPLIES 6
325 #define S5C73M3_DEFAULT_MCLK_FREQ 24000000U
327 struct s5c73m3_ctrls {
328 struct v4l2_ctrl_handler handler;
329 struct {
330 /* exposure/exposure bias cluster */
331 struct v4l2_ctrl *auto_exposure;
332 struct v4l2_ctrl *exposure_bias;
333 struct v4l2_ctrl *exposure_metering;
335 struct {
336 /* iso/auto iso cluster */
337 struct v4l2_ctrl *auto_iso;
338 struct v4l2_ctrl *iso;
340 struct v4l2_ctrl *auto_wb;
341 struct {
342 /* continuous auto focus/auto focus cluster */
343 struct v4l2_ctrl *focus_auto;
344 struct v4l2_ctrl *af_start;
345 struct v4l2_ctrl *af_stop;
346 struct v4l2_ctrl *af_status;
347 struct v4l2_ctrl *af_distance;
350 struct v4l2_ctrl *aaa_lock;
351 struct v4l2_ctrl *colorfx;
352 struct v4l2_ctrl *contrast;
353 struct v4l2_ctrl *saturation;
354 struct v4l2_ctrl *sharpness;
355 struct v4l2_ctrl *zoom;
356 struct v4l2_ctrl *wdr;
357 struct v4l2_ctrl *stabilization;
358 struct v4l2_ctrl *jpeg_quality;
359 struct v4l2_ctrl *scene_mode;
362 enum s5c73m3_gpio_id {
363 STBY,
364 RST,
365 GPIO_NUM,
368 enum s5c73m3_resolution_types {
369 RES_ISP,
370 RES_JPEG,
373 struct s5c73m3_interval {
374 u16 fps_reg;
375 struct v4l2_fract interval;
376 /* Maximum rectangle for the interval */
377 struct v4l2_frmsize_discrete size;
380 struct s5c73m3 {
381 struct v4l2_subdev sensor_sd;
382 struct media_pad sensor_pads[S5C73M3_NUM_PADS];
384 struct v4l2_subdev oif_sd;
385 struct media_pad oif_pads[OIF_NUM_PADS];
387 struct spi_driver spidrv;
388 struct spi_device *spi_dev;
389 struct i2c_client *i2c_client;
390 u32 i2c_write_address;
391 u32 i2c_read_address;
393 struct regulator_bulk_data supplies[S5C73M3_MAX_SUPPLIES];
394 struct s5c73m3_gpio gpio[GPIO_NUM];
396 struct clk *clock;
398 /* External master clock frequency */
399 u32 mclk_frequency;
400 /* Video bus type - MIPI-CSI2/parallel */
401 enum v4l2_mbus_type bus_type;
403 const struct s5c73m3_frame_size *sensor_pix_size[2];
404 const struct s5c73m3_frame_size *oif_pix_size[2];
405 u32 mbus_code;
407 const struct s5c73m3_interval *fiv;
409 struct v4l2_mbus_frame_desc frame_desc;
410 /* protects the struct members below */
411 struct mutex lock;
413 struct s5c73m3_ctrls ctrls;
415 u8 streaming:1;
416 u8 apply_fmt:1;
417 u8 apply_fiv:1;
418 u8 isp_ready:1;
420 short power;
422 char sensor_fw[S5C73M3_SENSOR_FW_LEN + 2];
423 char sensor_type[S5C73M3_SENSOR_TYPE_LEN + 2];
424 char fw_file_version[2];
425 unsigned int fw_size;
428 struct s5c73m3_frame_size {
429 u32 width;
430 u32 height;
431 u8 reg_val;
434 extern int s5c73m3_dbg;
436 int s5c73m3_register_spi_driver(struct s5c73m3 *state);
437 void s5c73m3_unregister_spi_driver(struct s5c73m3 *state);
438 int s5c73m3_spi_write(struct s5c73m3 *state, const void *addr,
439 const unsigned int len, const unsigned int tx_size);
440 int s5c73m3_spi_read(struct s5c73m3 *state, void *addr,
441 const unsigned int len, const unsigned int tx_size);
443 int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data);
444 int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data);
445 int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data);
446 int s5c73m3_init_controls(struct s5c73m3 *state);
448 static inline struct v4l2_subdev *ctrl_to_sensor_sd(struct v4l2_ctrl *ctrl)
450 return &container_of(ctrl->handler, struct s5c73m3,
451 ctrls.handler)->sensor_sd;
454 static inline struct s5c73m3 *sensor_sd_to_s5c73m3(struct v4l2_subdev *sd)
456 return container_of(sd, struct s5c73m3, sensor_sd);
459 static inline struct s5c73m3 *oif_sd_to_s5c73m3(struct v4l2_subdev *sd)
461 return container_of(sd, struct s5c73m3, oif_sd);
463 #endif /* S5C73M3_H_ */