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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / mmc / host / mxcmmc.c
blobd110f9e98c4b45cc587378f740988acc2b3b3cfa
1 /*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
32 #include <linux/io.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
36 #include <linux/types.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_dma.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include <asm/dma.h>
44 #include <asm/irq.h>
45 #include <linux/platform_data/mmc-mxcmmc.h>
46
47 #include <linux/platform_data/dma-imx.h>
48
49 #define DRIVER_NAME "mxc-mmc"
50 #define MXCMCI_TIMEOUT_MS 10000
51
52 #define MMC_REG_STR_STP_CLK 0x00
53 #define MMC_REG_STATUS 0x04
54 #define MMC_REG_CLK_RATE 0x08
55 #define MMC_REG_CMD_DAT_CONT 0x0C
56 #define MMC_REG_RES_TO 0x10
57 #define MMC_REG_READ_TO 0x14
58 #define MMC_REG_BLK_LEN 0x18
59 #define MMC_REG_NOB 0x1C
60 #define MMC_REG_REV_NO 0x20
61 #define MMC_REG_INT_CNTR 0x24
62 #define MMC_REG_CMD 0x28
63 #define MMC_REG_ARG 0x2C
64 #define MMC_REG_RES_FIFO 0x34
65 #define MMC_REG_BUFFER_ACCESS 0x38
66
67 #define STR_STP_CLK_RESET (1 << 3)
68 #define STR_STP_CLK_START_CLK (1 << 1)
69 #define STR_STP_CLK_STOP_CLK (1 << 0)
70
71 #define STATUS_CARD_INSERTION (1 << 31)
72 #define STATUS_CARD_REMOVAL (1 << 30)
73 #define STATUS_YBUF_EMPTY (1 << 29)
74 #define STATUS_XBUF_EMPTY (1 << 28)
75 #define STATUS_YBUF_FULL (1 << 27)
76 #define STATUS_XBUF_FULL (1 << 26)
77 #define STATUS_BUF_UND_RUN (1 << 25)
78 #define STATUS_BUF_OVFL (1 << 24)
79 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
80 #define STATUS_END_CMD_RESP (1 << 13)
81 #define STATUS_WRITE_OP_DONE (1 << 12)
82 #define STATUS_DATA_TRANS_DONE (1 << 11)
83 #define STATUS_READ_OP_DONE (1 << 11)
84 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86 #define STATUS_BUF_READ_RDY (1 << 7)
87 #define STATUS_BUF_WRITE_RDY (1 << 6)
88 #define STATUS_RESP_CRC_ERR (1 << 5)
89 #define STATUS_CRC_READ_ERR (1 << 3)
90 #define STATUS_CRC_WRITE_ERR (1 << 2)
91 #define STATUS_TIME_OUT_RESP (1 << 1)
92 #define STATUS_TIME_OUT_READ (1 << 0)
93 #define STATUS_ERR_MASK 0x2f
94
95 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
98 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99 #define CMD_DAT_CONT_INIT (1 << 7)
100 #define CMD_DAT_CONT_WRITE (1 << 4)
101 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105
106 #define INT_SDIO_INT_WKP_EN (1 << 18)
107 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
108 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109 #define INT_CARD_INSERTION_EN (1 << 15)
110 #define INT_CARD_REMOVAL_EN (1 << 14)
111 #define INT_SDIO_IRQ_EN (1 << 13)
112 #define INT_DAT0_EN (1 << 12)
113 #define INT_BUF_READ_EN (1 << 4)
114 #define INT_BUF_WRITE_EN (1 << 3)
115 #define INT_END_CMD_RES_EN (1 << 2)
116 #define INT_WRITE_OP_DONE_EN (1 << 1)
117 #define INT_READ_OP_EN (1 << 0)
118
119 enum mxcmci_type {
120 IMX21_MMC,
121 IMX31_MMC,
122 MPC512X_MMC,
123 };
124
125 struct mxcmci_host {
126 struct mmc_host *mmc;
127 void __iomem *base;
128 dma_addr_t phys_base;
129 int detect_irq;
130 struct dma_chan *dma;
131 struct dma_async_tx_descriptor *desc;
132 int do_dma;
133 int default_irq_mask;
134 int use_sdio;
135 unsigned int power_mode;
136 struct imxmmc_platform_data *pdata;
137
138 struct mmc_request *req;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
141
142 unsigned int datasize;
143 unsigned int dma_dir;
144
145 u16 rev_no;
146 unsigned int cmdat;
147
148 struct clk *clk_ipg;
149 struct clk *clk_per;
150
151 int clock;
152
153 struct work_struct datawork;
154 spinlock_t lock;
155
156 int burstlen;
157 int dmareq;
158 struct dma_slave_config dma_slave_config;
159 struct imx_dma_data dma_data;
160
161 struct timer_list watchdog;
162 enum mxcmci_type devtype;
163 };
164
165 static const struct platform_device_id mxcmci_devtype[] = {
166 {
167 .name = "imx21-mmc",
168 .driver_data = IMX21_MMC,
169 }, {
170 .name = "imx31-mmc",
171 .driver_data = IMX31_MMC,
172 }, {
173 .name = "mpc512x-sdhc",
174 .driver_data = MPC512X_MMC,
175 }, {
176 /* sentinel */
177 }
178 };
179 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
180
181 static const struct of_device_id mxcmci_of_match[] = {
182 {
183 .compatible = "fsl,imx21-mmc",
184 .data = &mxcmci_devtype[IMX21_MMC],
185 }, {
186 .compatible = "fsl,imx31-mmc",
187 .data = &mxcmci_devtype[IMX31_MMC],
188 }, {
189 .compatible = "fsl,mpc5121-sdhc",
190 .data = &mxcmci_devtype[MPC512X_MMC],
191 }, {
192 /* sentinel */
193 }
194 };
195 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
196
197 static inline int is_imx31_mmc(struct mxcmci_host *host)
198 {
199 return host->devtype == IMX31_MMC;
200 }
201
202 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
203 {
204 return host->devtype == MPC512X_MMC;
205 }
206
207 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
208 {
209 if (IS_ENABLED(CONFIG_PPC_MPC512x))
210 return ioread32be(host->base + reg);
211 else
212 return readl(host->base + reg);
213 }
214
215 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
216 {
217 if (IS_ENABLED(CONFIG_PPC_MPC512x))
218 iowrite32be(val, host->base + reg);
219 else
220 writel(val, host->base + reg);
221 }
222
223 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
224 {
225 if (IS_ENABLED(CONFIG_PPC_MPC512x))
226 return ioread32be(host->base + reg);
227 else
228 return readw(host->base + reg);
229 }
230
231 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
232 {
233 if (IS_ENABLED(CONFIG_PPC_MPC512x))
234 iowrite32be(val, host->base + reg);
235 else
236 writew(val, host->base + reg);
237 }
238
239 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
240
241 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
242 {
243 if (!IS_ERR(host->mmc->supply.vmmc)) {
244 if (host->power_mode == MMC_POWER_UP)
245 mmc_regulator_set_ocr(host->mmc,
246 host->mmc->supply.vmmc, vdd);
247 else if (host->power_mode == MMC_POWER_OFF)
248 mmc_regulator_set_ocr(host->mmc,
249 host->mmc->supply.vmmc, 0);
250 }
251
252 if (host->pdata && host->pdata->setpower)
253 host->pdata->setpower(mmc_dev(host->mmc), vdd);
254 }
255
256 static inline int mxcmci_use_dma(struct mxcmci_host *host)
257 {
258 return host->do_dma;
259 }
260
261 static void mxcmci_softreset(struct mxcmci_host *host)
262 {
263 int i;
264
265 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
266
267 /* reset sequence */
268 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
269 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
270 MMC_REG_STR_STP_CLK);
271
272 for (i = 0; i < 8; i++)
273 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
274
275 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
276 }
277
278 #if IS_ENABLED(CONFIG_PPC_MPC512x)
279 static inline void buffer_swap32(u32 *buf, int len)
280 {
281 int i;
282
283 for (i = 0; i < ((len + 3) / 4); i++) {
284 *buf = swab32(*buf);
285 buf++;
286 }
287 }
288
289 static void mxcmci_swap_buffers(struct mmc_data *data)
290 {
291 struct scatterlist *sg;
292 int i;
293
294 for_each_sg(data->sg, sg, data->sg_len, i)
295 buffer_swap32(sg_virt(sg), sg->length);
296 }
297 #else
298 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
299 #endif
300
301 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
302 {
303 unsigned int nob = data->blocks;
304 unsigned int blksz = data->blksz;
305 unsigned int datasize = nob * blksz;
306 struct scatterlist *sg;
307 enum dma_transfer_direction slave_dirn;
308 int i, nents;
309
310 if (data->flags & MMC_DATA_STREAM)
311 nob = 0xffff;
312
313 host->data = data;
314 data->bytes_xfered = 0;
315
316 mxcmci_writew(host, nob, MMC_REG_NOB);
317 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
318 host->datasize = datasize;
319
320 if (!mxcmci_use_dma(host))
321 return 0;
322
323 for_each_sg(data->sg, sg, data->sg_len, i) {
324 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
325 host->do_dma = 0;
326 return 0;
327 }
328 }
329
330 if (data->flags & MMC_DATA_READ) {
331 host->dma_dir = DMA_FROM_DEVICE;
332 slave_dirn = DMA_DEV_TO_MEM;
333 } else {
334 host->dma_dir = DMA_TO_DEVICE;
335 slave_dirn = DMA_MEM_TO_DEV;
336
337 mxcmci_swap_buffers(data);
338 }
339
340 nents = dma_map_sg(host->dma->device->dev, data->sg,
341 data->sg_len, host->dma_dir);
342 if (nents != data->sg_len)
343 return -EINVAL;
344
345 host->desc = dmaengine_prep_slave_sg(host->dma,
346 data->sg, data->sg_len, slave_dirn,
347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
348
349 if (!host->desc) {
350 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
351 host->dma_dir);
352 host->do_dma = 0;
353 return 0; /* Fall back to PIO */
354 }
355 wmb();
356
357 dmaengine_submit(host->desc);
358 dma_async_issue_pending(host->dma);
359
360 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
361
362 return 0;
363 }
364
365 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
366 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
367
368 static void mxcmci_dma_callback(void *data)
369 {
370 struct mxcmci_host *host = data;
371 u32 stat;
372
373 del_timer(&host->watchdog);
374
375 stat = mxcmci_readl(host, MMC_REG_STATUS);
376
377 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
378
379 mxcmci_data_done(host, stat);
380 }
381
382 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
383 unsigned int cmdat)
384 {
385 u32 int_cntr = host->default_irq_mask;
386 unsigned long flags;
387
388 WARN_ON(host->cmd != NULL);
389 host->cmd = cmd;
390
391 switch (mmc_resp_type(cmd)) {
392 case MMC_RSP_R1: /* short CRC, OPCODE */
393 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
394 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
395 break;
396 case MMC_RSP_R2: /* long 136 bit + CRC */
397 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
398 break;
399 case MMC_RSP_R3: /* short */
400 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
401 break;
402 case MMC_RSP_NONE:
403 break;
404 default:
405 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
406 mmc_resp_type(cmd));
407 cmd->error = -EINVAL;
408 return -EINVAL;
409 }
410
411 int_cntr = INT_END_CMD_RES_EN;
412
413 if (mxcmci_use_dma(host)) {
414 if (host->dma_dir == DMA_FROM_DEVICE) {
415 host->desc->callback = mxcmci_dma_callback;
416 host->desc->callback_param = host;
417 } else {
418 int_cntr |= INT_WRITE_OP_DONE_EN;
419 }
420 }
421
422 spin_lock_irqsave(&host->lock, flags);
423 if (host->use_sdio)
424 int_cntr |= INT_SDIO_IRQ_EN;
425 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
426 spin_unlock_irqrestore(&host->lock, flags);
427
428 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
429 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
430 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
431
432 return 0;
433 }
434
435 static void mxcmci_finish_request(struct mxcmci_host *host,
436 struct mmc_request *req)
437 {
438 u32 int_cntr = host->default_irq_mask;
439 unsigned long flags;
440
441 spin_lock_irqsave(&host->lock, flags);
442 if (host->use_sdio)
443 int_cntr |= INT_SDIO_IRQ_EN;
444 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
445 spin_unlock_irqrestore(&host->lock, flags);
446
447 host->req = NULL;
448 host->cmd = NULL;
449 host->data = NULL;
450
451 mmc_request_done(host->mmc, req);
452 }
453
454 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
455 {
456 struct mmc_data *data = host->data;
457 int data_error;
458
459 if (mxcmci_use_dma(host)) {
460 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
461 host->dma_dir);
462 mxcmci_swap_buffers(data);
463 }
464
465 if (stat & STATUS_ERR_MASK) {
466 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
467 stat);
468 if (stat & STATUS_CRC_READ_ERR) {
469 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
470 data->error = -EILSEQ;
471 } else if (stat & STATUS_CRC_WRITE_ERR) {
472 u32 err_code = (stat >> 9) & 0x3;
473 if (err_code == 2) { /* No CRC response */
474 dev_err(mmc_dev(host->mmc),
475 "%s: No CRC -ETIMEDOUT\n", __func__);
476 data->error = -ETIMEDOUT;
477 } else {
478 dev_err(mmc_dev(host->mmc),
479 "%s: -EILSEQ\n", __func__);
480 data->error = -EILSEQ;
481 }
482 } else if (stat & STATUS_TIME_OUT_READ) {
483 dev_err(mmc_dev(host->mmc),
484 "%s: read -ETIMEDOUT\n", __func__);
485 data->error = -ETIMEDOUT;
486 } else {
487 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
488 data->error = -EIO;
489 }
490 } else {
491 data->bytes_xfered = host->datasize;
492 }
493
494 data_error = data->error;
495
496 host->data = NULL;
497
498 return data_error;
499 }
500
501 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
502 {
503 struct mmc_command *cmd = host->cmd;
504 int i;
505 u32 a, b, c;
506
507 if (!cmd)
508 return;
509
510 if (stat & STATUS_TIME_OUT_RESP) {
511 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
512 cmd->error = -ETIMEDOUT;
513 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
514 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
515 cmd->error = -EILSEQ;
516 }
517
518 if (cmd->flags & MMC_RSP_PRESENT) {
519 if (cmd->flags & MMC_RSP_136) {
520 for (i = 0; i < 4; i++) {
521 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
522 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
523 cmd->resp[i] = a << 16 | b;
524 }
525 } else {
526 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
527 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
528 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
529 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
530 }
531 }
532 }
533
534 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
535 {
536 u32 stat;
537 unsigned long timeout = jiffies + HZ;
538
539 do {
540 stat = mxcmci_readl(host, MMC_REG_STATUS);
541 if (stat & STATUS_ERR_MASK)
542 return stat;
543 if (time_after(jiffies, timeout)) {
544 mxcmci_softreset(host);
545 mxcmci_set_clk_rate(host, host->clock);
546 return STATUS_TIME_OUT_READ;
547 }
548 if (stat & mask)
549 return 0;
550 cpu_relax();
551 } while (1);
552 }
553
554 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
555 {
556 unsigned int stat;
557 u32 *buf = _buf;
558
559 while (bytes > 3) {
560 stat = mxcmci_poll_status(host,
561 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
562 if (stat)
563 return stat;
564 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
565 bytes -= 4;
566 }
567
568 if (bytes) {
569 u8 *b = (u8 *)buf;
570 u32 tmp;
571
572 stat = mxcmci_poll_status(host,
573 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
574 if (stat)
575 return stat;
576 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
577 memcpy(b, &tmp, bytes);
578 }
579
580 return 0;
581 }
582
583 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
584 {
585 unsigned int stat;
586 u32 *buf = _buf;
587
588 while (bytes > 3) {
589 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
590 if (stat)
591 return stat;
592 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
593 bytes -= 4;
594 }
595
596 if (bytes) {
597 u8 *b = (u8 *)buf;
598 u32 tmp;
599
600 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
601 if (stat)
602 return stat;
603
604 memcpy(&tmp, b, bytes);
605 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
606 }
607
608 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
609 }
610
611 static int mxcmci_transfer_data(struct mxcmci_host *host)
612 {
613 struct mmc_data *data = host->req->data;
614 struct scatterlist *sg;
615 int stat, i;
616
617 host->data = data;
618 host->datasize = 0;
619
620 if (data->flags & MMC_DATA_READ) {
621 for_each_sg(data->sg, sg, data->sg_len, i) {
622 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
623 if (stat)
624 return stat;
625 host->datasize += sg->length;
626 }
627 } else {
628 for_each_sg(data->sg, sg, data->sg_len, i) {
629 stat = mxcmci_push(host, sg_virt(sg), sg->length);
630 if (stat)
631 return stat;
632 host->datasize += sg->length;
633 }
634 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
635 if (stat)
636 return stat;
637 }
638 return 0;
639 }
640
641 static void mxcmci_datawork(struct work_struct *work)
642 {
643 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
644 datawork);
645 int datastat = mxcmci_transfer_data(host);
646
647 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
648 MMC_REG_STATUS);
649 mxcmci_finish_data(host, datastat);
650
651 if (host->req->stop) {
652 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
653 mxcmci_finish_request(host, host->req);
654 return;
655 }
656 } else {
657 mxcmci_finish_request(host, host->req);
658 }
659 }
660
661 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
662 {
663 struct mmc_request *req;
664 int data_error;
665 unsigned long flags;
666
667 spin_lock_irqsave(&host->lock, flags);
668
669 if (!host->data) {
670 spin_unlock_irqrestore(&host->lock, flags);
671 return;
672 }
673
674 if (!host->req) {
675 spin_unlock_irqrestore(&host->lock, flags);
676 return;
677 }
678
679 req = host->req;
680 if (!req->stop)
681 host->req = NULL; /* we will handle finish req below */
682
683 data_error = mxcmci_finish_data(host, stat);
684
685 spin_unlock_irqrestore(&host->lock, flags);
686
687 mxcmci_read_response(host, stat);
688 host->cmd = NULL;
689
690 if (req->stop) {
691 if (mxcmci_start_cmd(host, req->stop, 0)) {
692 mxcmci_finish_request(host, req);
693 return;
694 }
695 } else {
696 mxcmci_finish_request(host, req);
697 }
698 }
699
700 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
701 {
702 mxcmci_read_response(host, stat);
703 host->cmd = NULL;
704
705 if (!host->data && host->req) {
706 mxcmci_finish_request(host, host->req);
707 return;
708 }
709
710 /* For the DMA case the DMA engine handles the data transfer
711 * automatically. For non DMA we have to do it ourselves.
712 * Don't do it in interrupt context though.
713 */
714 if (!mxcmci_use_dma(host) && host->data)
715 schedule_work(&host->datawork);
716
717 }
718
719 static irqreturn_t mxcmci_irq(int irq, void *devid)
720 {
721 struct mxcmci_host *host = devid;
722 unsigned long flags;
723 bool sdio_irq;
724 u32 stat;
725
726 stat = mxcmci_readl(host, MMC_REG_STATUS);
727 mxcmci_writel(host,
728 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
729 STATUS_WRITE_OP_DONE),
730 MMC_REG_STATUS);
731
732 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
733
734 spin_lock_irqsave(&host->lock, flags);
735 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
736 spin_unlock_irqrestore(&host->lock, flags);
737
738 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
739 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
740
741 if (sdio_irq) {
742 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
743 mmc_signal_sdio_irq(host->mmc);
744 }
745
746 if (stat & STATUS_END_CMD_RESP)
747 mxcmci_cmd_done(host, stat);
748
749 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
750 del_timer(&host->watchdog);
751 mxcmci_data_done(host, stat);
752 }
753
754 if (host->default_irq_mask &&
755 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
756 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
757
758 return IRQ_HANDLED;
759 }
760
761 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
762 {
763 struct mxcmci_host *host = mmc_priv(mmc);
764 unsigned int cmdat = host->cmdat;
765 int error;
766
767 WARN_ON(host->req != NULL);
768
769 host->req = req;
770 host->cmdat &= ~CMD_DAT_CONT_INIT;
771
772 if (host->dma)
773 host->do_dma = 1;
774
775 if (req->data) {
776 error = mxcmci_setup_data(host, req->data);
777 if (error) {
778 req->cmd->error = error;
779 goto out;
780 }
781
782
783 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
784
785 if (req->data->flags & MMC_DATA_WRITE)
786 cmdat |= CMD_DAT_CONT_WRITE;
787 }
788
789 error = mxcmci_start_cmd(host, req->cmd, cmdat);
790
791 out:
792 if (error)
793 mxcmci_finish_request(host, req);
794 }
795
796 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
797 {
798 unsigned int divider;
799 int prescaler = 0;
800 unsigned int clk_in = clk_get_rate(host->clk_per);
801
802 while (prescaler <= 0x800) {
803 for (divider = 1; divider <= 0xF; divider++) {
804 int x;
805
806 x = (clk_in / (divider + 1));
807
808 if (prescaler)
809 x /= (prescaler * 2);
810
811 if (x <= clk_ios)
812 break;
813 }
814 if (divider < 0x10)
815 break;
816
817 if (prescaler == 0)
818 prescaler = 1;
819 else
820 prescaler <<= 1;
821 }
822
823 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
824
825 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
826 prescaler, divider, clk_in, clk_ios);
827 }
828
829 static int mxcmci_setup_dma(struct mmc_host *mmc)
830 {
831 struct mxcmci_host *host = mmc_priv(mmc);
832 struct dma_slave_config *config = &host->dma_slave_config;
833
834 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
835 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
836 config->dst_addr_width = 4;
837 config->src_addr_width = 4;
838 config->dst_maxburst = host->burstlen;
839 config->src_maxburst = host->burstlen;
840 config->device_fc = false;
841
842 return dmaengine_slave_config(host->dma, config);
843 }
844
845 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
846 {
847 struct mxcmci_host *host = mmc_priv(mmc);
848 int burstlen, ret;
849
850 /*
851 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
852 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
853 */
854 if (ios->bus_width == MMC_BUS_WIDTH_4)
855 burstlen = 16;
856 else
857 burstlen = 4;
858
859 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
860 host->burstlen = burstlen;
861 ret = mxcmci_setup_dma(mmc);
862 if (ret) {
863 dev_err(mmc_dev(host->mmc),
864 "failed to config DMA channel. Falling back to PIO\n");
865 dma_release_channel(host->dma);
866 host->do_dma = 0;
867 host->dma = NULL;
868 }
869 }
870
871 if (ios->bus_width == MMC_BUS_WIDTH_4)
872 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
873 else
874 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
875
876 if (host->power_mode != ios->power_mode) {
877 host->power_mode = ios->power_mode;
878 mxcmci_set_power(host, ios->vdd);
879
880 if (ios->power_mode == MMC_POWER_ON)
881 host->cmdat |= CMD_DAT_CONT_INIT;
882 }
883
884 if (ios->clock) {
885 mxcmci_set_clk_rate(host, ios->clock);
886 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
887 } else {
888 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
889 }
890
891 host->clock = ios->clock;
892 }
893
894 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
895 {
896 struct mmc_host *mmc = data;
897
898 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
899
900 mmc_detect_change(mmc, msecs_to_jiffies(250));
901 return IRQ_HANDLED;
902 }
903
904 static int mxcmci_get_ro(struct mmc_host *mmc)
905 {
906 struct mxcmci_host *host = mmc_priv(mmc);
907
908 if (host->pdata && host->pdata->get_ro)
909 return !!host->pdata->get_ro(mmc_dev(mmc));
910 /*
911 * If board doesn't support read only detection (no mmc_gpio
912 * context or gpio is invalid), then let the mmc core decide
913 * what to do.
914 */
915 return mmc_gpio_get_ro(mmc);
916 }
917
918 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
919 {
920 struct mxcmci_host *host = mmc_priv(mmc);
921 unsigned long flags;
922 u32 int_cntr;
923
924 spin_lock_irqsave(&host->lock, flags);
925 host->use_sdio = enable;
926 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
927
928 if (enable)
929 int_cntr |= INT_SDIO_IRQ_EN;
930 else
931 int_cntr &= ~INT_SDIO_IRQ_EN;
932
933 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
934 spin_unlock_irqrestore(&host->lock, flags);
935 }
936
937 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
938 {
939 struct mxcmci_host *mxcmci = mmc_priv(host);
940
941 /*
942 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
943 * multi-block transfers when connected SDIO peripheral doesn't
944 * drive the BUSY line as required by the specs.
945 * One way to prevent this is to only allow 1-bit transfers.
946 */
947
948 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
949 host->caps &= ~MMC_CAP_4_BIT_DATA;
950 else
951 host->caps |= MMC_CAP_4_BIT_DATA;
952 }
953
954 static bool filter(struct dma_chan *chan, void *param)
955 {
956 struct mxcmci_host *host = param;
957
958 if (!imx_dma_is_general_purpose(chan))
959 return false;
960
961 chan->private = &host->dma_data;
962
963 return true;
964 }
965
966 static void mxcmci_watchdog(unsigned long data)
967 {
968 struct mmc_host *mmc = (struct mmc_host *)data;
969 struct mxcmci_host *host = mmc_priv(mmc);
970 struct mmc_request *req = host->req;
971 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
972
973 if (host->dma_dir == DMA_FROM_DEVICE) {
974 dmaengine_terminate_all(host->dma);
975 dev_err(mmc_dev(host->mmc),
976 "%s: read time out (status = 0x%08x)\n",
977 __func__, stat);
978 } else {
979 dev_err(mmc_dev(host->mmc),
980 "%s: write time out (status = 0x%08x)\n",
981 __func__, stat);
982 mxcmci_softreset(host);
983 }
984
985 /* Mark transfer as erroneus and inform the upper layers */
986
987 if (host->data)
988 host->data->error = -ETIMEDOUT;
989 host->req = NULL;
990 host->cmd = NULL;
991 host->data = NULL;
992 mmc_request_done(host->mmc, req);
993 }
994
995 static const struct mmc_host_ops mxcmci_ops = {
996 .request = mxcmci_request,
997 .set_ios = mxcmci_set_ios,
998 .get_ro = mxcmci_get_ro,
999 .enable_sdio_irq = mxcmci_enable_sdio_irq,
1000 .init_card = mxcmci_init_card,
1001 };
1002
1003 static int mxcmci_probe(struct platform_device *pdev)
1004 {
1005 struct mmc_host *mmc;
1006 struct mxcmci_host *host;
1007 struct resource *res;
1008 int ret = 0, irq;
1009 bool dat3_card_detect = false;
1010 dma_cap_mask_t mask;
1011 const struct of_device_id *of_id;
1012 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1013
1014 pr_info("i.MX/MPC512x SDHC driver\n");
1015
1016 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1017
1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019 irq = platform_get_irq(pdev, 0);
1020 if (irq < 0)
1021 return -EINVAL;
1022
1023 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1024 if (!mmc)
1025 return -ENOMEM;
1026
1027 host = mmc_priv(mmc);
1028
1029 host->base = devm_ioremap_resource(&pdev->dev, res);
1030 if (IS_ERR(host->base)) {
1031 ret = PTR_ERR(host->base);
1032 goto out_free;
1033 }
1034
1035 host->phys_base = res->start;
1036
1037 ret = mmc_of_parse(mmc);
1038 if (ret)
1039 goto out_free;
1040 mmc->ops = &mxcmci_ops;
1041
1042 /* For devicetree parsing, the bus width is read from devicetree */
1043 if (pdata)
1044 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1045 else
1046 mmc->caps |= MMC_CAP_SDIO_IRQ;
1047
1048 /* MMC core transfer sizes tunable parameters */
1049 mmc->max_blk_size = 2048;
1050 mmc->max_blk_count = 65535;
1051 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1052 mmc->max_seg_size = mmc->max_req_size;
1053
1054 if (of_id) {
1055 const struct platform_device_id *id_entry = of_id->data;
1056 host->devtype = id_entry->driver_data;
1057 } else {
1058 host->devtype = pdev->id_entry->driver_data;
1059 }
1060
1061 /* adjust max_segs after devtype detection */
1062 if (!is_mpc512x_mmc(host))
1063 mmc->max_segs = 64;
1064
1065 host->mmc = mmc;
1066 host->pdata = pdata;
1067 spin_lock_init(&host->lock);
1068
1069 if (pdata)
1070 dat3_card_detect = pdata->dat3_card_detect;
1071 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1072 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1073 dat3_card_detect = true;
1074
1075 ret = mmc_regulator_get_supply(mmc);
1076 if (ret == -EPROBE_DEFER)
1077 goto out_free;
1078
1079 if (!mmc->ocr_avail) {
1080 if (pdata && pdata->ocr_avail)
1081 mmc->ocr_avail = pdata->ocr_avail;
1082 else
1083 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1084 }
1085
1086 if (dat3_card_detect)
1087 host->default_irq_mask =
1088 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1089 else
1090 host->default_irq_mask = 0;
1091
1092 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1093 if (IS_ERR(host->clk_ipg)) {
1094 ret = PTR_ERR(host->clk_ipg);
1095 goto out_free;
1096 }
1097
1098 host->clk_per = devm_clk_get(&pdev->dev, "per");
1099 if (IS_ERR(host->clk_per)) {
1100 ret = PTR_ERR(host->clk_per);
1101 goto out_free;
1102 }
1103
1104 clk_prepare_enable(host->clk_per);
1105 clk_prepare_enable(host->clk_ipg);
1106
1107 mxcmci_softreset(host);
1108
1109 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1110 if (host->rev_no != 0x400) {
1111 ret = -ENODEV;
1112 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1113 host->rev_no);
1114 goto out_clk_put;
1115 }
1116
1117 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1118 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1119
1120 /* recommended in data sheet */
1121 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1122
1123 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1124
1125 if (!host->pdata) {
1126 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1127 } else {
1128 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1129 if (res) {
1130 host->dmareq = res->start;
1131 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1132 host->dma_data.priority = DMA_PRIO_LOW;
1133 host->dma_data.dma_request = host->dmareq;
1134 dma_cap_zero(mask);
1135 dma_cap_set(DMA_SLAVE, mask);
1136 host->dma = dma_request_channel(mask, filter, host);
1137 }
1138 }
1139 if (host->dma)
1140 mmc->max_seg_size = dma_get_max_seg_size(
1141 host->dma->device->dev);
1142 else
1143 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1144
1145 INIT_WORK(&host->datawork, mxcmci_datawork);
1146
1147 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1148 dev_name(&pdev->dev), host);
1149 if (ret)
1150 goto out_free_dma;
1151
1152 platform_set_drvdata(pdev, mmc);
1153
1154 if (host->pdata && host->pdata->init) {
1155 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1156 host->mmc);
1157 if (ret)
1158 goto out_free_dma;
1159 }
1160
1161 init_timer(&host->watchdog);
1162 host->watchdog.function = &mxcmci_watchdog;
1163 host->watchdog.data = (unsigned long)mmc;
1164
1165 mmc_add_host(mmc);
1166
1167 return 0;
1168
1169 out_free_dma:
1170 if (host->dma)
1171 dma_release_channel(host->dma);
1172
1173 out_clk_put:
1174 clk_disable_unprepare(host->clk_per);
1175 clk_disable_unprepare(host->clk_ipg);
1176
1177 out_free:
1178 mmc_free_host(mmc);
1179
1180 return ret;
1181 }
1182
1183 static int mxcmci_remove(struct platform_device *pdev)
1184 {
1185 struct mmc_host *mmc = platform_get_drvdata(pdev);
1186 struct mxcmci_host *host = mmc_priv(mmc);
1187
1188 mmc_remove_host(mmc);
1189
1190 if (host->pdata && host->pdata->exit)
1191 host->pdata->exit(&pdev->dev, mmc);
1192
1193 if (host->dma)
1194 dma_release_channel(host->dma);
1195
1196 clk_disable_unprepare(host->clk_per);
1197 clk_disable_unprepare(host->clk_ipg);
1198
1199 mmc_free_host(mmc);
1200
1201 return 0;
1202 }
1203
1204 static int __maybe_unused mxcmci_suspend(struct device *dev)
1205 {
1206 struct mmc_host *mmc = dev_get_drvdata(dev);
1207 struct mxcmci_host *host = mmc_priv(mmc);
1208
1209 clk_disable_unprepare(host->clk_per);
1210 clk_disable_unprepare(host->clk_ipg);
1211 return 0;
1212 }
1213
1214 static int __maybe_unused mxcmci_resume(struct device *dev)
1215 {
1216 struct mmc_host *mmc = dev_get_drvdata(dev);
1217 struct mxcmci_host *host = mmc_priv(mmc);
1218
1219 clk_prepare_enable(host->clk_per);
1220 clk_prepare_enable(host->clk_ipg);
1221 return 0;
1222 }
1223
1224 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1225
1226 static struct platform_driver mxcmci_driver = {
1227 .probe = mxcmci_probe,
1228 .remove = mxcmci_remove,
1229 .id_table = mxcmci_devtype,
1230 .driver = {
1231 .name = DRIVER_NAME,
1232 .pm = &mxcmci_pm_ops,
1233 .of_match_table = mxcmci_of_match,
1234 }
1235 };
1236
1237 module_platform_driver(mxcmci_driver);
1238
1239 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1240 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1241 MODULE_LICENSE("GPL");
1242 MODULE_ALIAS("platform:mxc-mmc");
Linux with added FPC-III support