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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
blob93137483ecde93fc509328c9445b8c61c65f8a48
1 /* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
35
36 struct realtek_pci_sdmmc {
37 struct platform_device *pdev;
38 struct rtsx_pcr *pcr;
39 struct mmc_host *mmc;
40 struct mmc_request *mrq;
41 struct workqueue_struct *workq;
42 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
43
44 struct work_struct work;
45 struct mutex host_mutex;
46
47 u8 ssc_depth;
48 unsigned int clock;
49 bool vpclk;
50 bool double_clk;
51 bool eject;
52 bool initial_mode;
53 int power_state;
54 #define SDMMC_POWER_ON 1
55 #define SDMMC_POWER_OFF 0
56
57 int sg_count;
58 s32 cookie;
59 int cookie_sg_count;
60 bool using_cookie;
61 };
62
63 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
64 {
65 return &(host->pdev->dev);
66 }
67
68 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
69 {
70 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
72 }
73
74 #ifdef DEBUG
75 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
76 {
77 u16 len = end - start + 1;
78 int i;
79 u8 data[8];
80
81 for (i = 0; i < len; i += 8) {
82 int j;
83 int n = min(8, len - i);
84
85 memset(&data, 0, sizeof(data));
86 for (j = 0; j < n; j++)
87 rtsx_pci_read_register(host->pcr, start + i + j,
88 data + j);
89 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
90 start + i, n, data);
91 }
92 }
93
94 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
95 {
96 dump_reg_range(host, 0xFDA0, 0xFDB3);
97 dump_reg_range(host, 0xFD52, 0xFD69);
98 }
99 #else
100 #define sd_print_debug_regs(host)
101 #endif /* DEBUG */
102
103 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
104 {
105 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
106 }
107
108 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
109 {
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
111 SD_CMD_START | cmd->opcode);
112 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
113 }
114
115 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
116 {
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
121 }
122
123 static int sd_response_type(struct mmc_command *cmd)
124 {
125 switch (mmc_resp_type(cmd)) {
126 case MMC_RSP_NONE:
127 return SD_RSP_TYPE_R0;
128 case MMC_RSP_R1:
129 return SD_RSP_TYPE_R1;
130 case MMC_RSP_R1 & ~MMC_RSP_CRC:
131 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
132 case MMC_RSP_R1B:
133 return SD_RSP_TYPE_R1b;
134 case MMC_RSP_R2:
135 return SD_RSP_TYPE_R2;
136 case MMC_RSP_R3:
137 return SD_RSP_TYPE_R3;
138 default:
139 return -EINVAL;
140 }
141 }
142
143 static int sd_status_index(int resp_type)
144 {
145 if (resp_type == SD_RSP_TYPE_R0)
146 return 0;
147 else if (resp_type == SD_RSP_TYPE_R2)
148 return 16;
149
150 return 5;
151 }
152 /*
153 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
154 *
155 * @pre: if called in pre_req()
156 * return:
157 * 0 - do dma_map_sg()
158 * 1 - using cookie
159 */
160 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
161 struct mmc_data *data, bool pre)
162 {
163 struct rtsx_pcr *pcr = host->pcr;
164 int read = data->flags & MMC_DATA_READ;
165 int count = 0;
166 int using_cookie = 0;
167
168 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
169 dev_err(sdmmc_dev(host),
170 "error: data->host_cookie = %d, host->cookie = %d\n",
171 data->host_cookie, host->cookie);
172 data->host_cookie = 0;
173 }
174
175 if (pre || data->host_cookie != host->cookie) {
176 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
177 } else {
178 count = host->cookie_sg_count;
179 using_cookie = 1;
180 }
181
182 if (pre) {
183 host->cookie_sg_count = count;
184 if (++host->cookie < 0)
185 host->cookie = 1;
186 data->host_cookie = host->cookie;
187 } else {
188 host->sg_count = count;
189 }
190
191 return using_cookie;
192 }
193
194 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
195 bool is_first_req)
196 {
197 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
198 struct mmc_data *data = mrq->data;
199
200 if (data->host_cookie) {
201 dev_err(sdmmc_dev(host),
202 "error: reset data->host_cookie = %d\n",
203 data->host_cookie);
204 data->host_cookie = 0;
205 }
206
207 sd_pre_dma_transfer(host, data, true);
208 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
209 }
210
211 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
212 int err)
213 {
214 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
215 struct rtsx_pcr *pcr = host->pcr;
216 struct mmc_data *data = mrq->data;
217 int read = data->flags & MMC_DATA_READ;
218
219 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
220 data->host_cookie = 0;
221 }
222
223 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
224 struct mmc_command *cmd)
225 {
226 struct rtsx_pcr *pcr = host->pcr;
227 u8 cmd_idx = (u8)cmd->opcode;
228 u32 arg = cmd->arg;
229 int err = 0;
230 int timeout = 100;
231 int i;
232 u8 *ptr;
233 int rsp_type;
234 int stat_idx;
235 bool clock_toggled = false;
236
237 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
238 __func__, cmd_idx, arg);
239
240 rsp_type = sd_response_type(cmd);
241 if (rsp_type < 0)
242 goto out;
243
244 stat_idx = sd_status_index(rsp_type);
245
246 if (rsp_type == SD_RSP_TYPE_R1b)
247 timeout = 3000;
248
249 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
250 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
251 0xFF, SD_CLK_TOGGLE_EN);
252 if (err < 0)
253 goto out;
254
255 clock_toggled = true;
256 }
257
258 rtsx_pci_init_cmd(pcr);
259 sd_cmd_set_sd_cmd(pcr, cmd);
260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
261 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
262 0x01, PINGPONG_BUFFER);
263 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
264 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
265 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
266 SD_TRANSFER_END | SD_STAT_IDLE,
267 SD_TRANSFER_END | SD_STAT_IDLE);
268
269 if (rsp_type == SD_RSP_TYPE_R2) {
270 /* Read data from ping-pong buffer */
271 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
272 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
273 } else if (rsp_type != SD_RSP_TYPE_R0) {
274 /* Read data from SD_CMDx registers */
275 for (i = SD_CMD0; i <= SD_CMD4; i++)
276 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
277 }
278
279 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
280
281 err = rtsx_pci_send_cmd(pcr, timeout);
282 if (err < 0) {
283 sd_print_debug_regs(host);
284 sd_clear_error(host);
285 dev_dbg(sdmmc_dev(host),
286 "rtsx_pci_send_cmd error (err = %d)\n", err);
287 goto out;
288 }
289
290 if (rsp_type == SD_RSP_TYPE_R0) {
291 err = 0;
292 goto out;
293 }
294
295 /* Eliminate returned value of CHECK_REG_CMD */
296 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
297
298 /* Check (Start,Transmission) bit of Response */
299 if ((ptr[0] & 0xC0) != 0) {
300 err = -EILSEQ;
301 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
302 goto out;
303 }
304
305 /* Check CRC7 */
306 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
307 if (ptr[stat_idx] & SD_CRC7_ERR) {
308 err = -EILSEQ;
309 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
310 goto out;
311 }
312 }
313
314 if (rsp_type == SD_RSP_TYPE_R2) {
315 /*
316 * The controller offloads the last byte {CRC-7, end bit 1'b1}
317 * of response type R2. Assign dummy CRC, 0, and end bit to the
318 * byte(ptr[16], goes into the LSB of resp[3] later).
319 */
320 ptr[16] = 1;
321
322 for (i = 0; i < 4; i++) {
323 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
324 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
325 i, cmd->resp[i]);
326 }
327 } else {
328 cmd->resp[0] = get_unaligned_be32(ptr + 1);
329 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
330 cmd->resp[0]);
331 }
332
333 out:
334 cmd->error = err;
335
336 if (err && clock_toggled)
337 rtsx_pci_write_register(pcr, SD_BUS_STAT,
338 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
339 }
340
341 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
342 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
343 {
344 struct rtsx_pcr *pcr = host->pcr;
345 int err;
346 u8 trans_mode;
347
348 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
349 __func__, cmd->opcode, cmd->arg);
350
351 if (!buf)
352 buf_len = 0;
353
354 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
355 trans_mode = SD_TM_AUTO_TUNING;
356 else
357 trans_mode = SD_TM_NORMAL_READ;
358
359 rtsx_pci_init_cmd(pcr);
360 sd_cmd_set_sd_cmd(pcr, cmd);
361 sd_cmd_set_data_len(pcr, 1, byte_cnt);
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
363 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
364 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
365 if (trans_mode != SD_TM_AUTO_TUNING)
366 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
367 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
368
369 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
370 0xFF, trans_mode | SD_TRANSFER_START);
371 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
372 SD_TRANSFER_END, SD_TRANSFER_END);
373
374 err = rtsx_pci_send_cmd(pcr, timeout);
375 if (err < 0) {
376 sd_print_debug_regs(host);
377 dev_dbg(sdmmc_dev(host),
378 "rtsx_pci_send_cmd fail (err = %d)\n", err);
379 return err;
380 }
381
382 if (buf && buf_len) {
383 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
384 if (err < 0) {
385 dev_dbg(sdmmc_dev(host),
386 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
387 return err;
388 }
389 }
390
391 return 0;
392 }
393
394 static int sd_write_data(struct realtek_pci_sdmmc *host,
395 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
396 int timeout)
397 {
398 struct rtsx_pcr *pcr = host->pcr;
399 int err;
400
401 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
402 __func__, cmd->opcode, cmd->arg);
403
404 if (!buf)
405 buf_len = 0;
406
407 sd_send_cmd_get_rsp(host, cmd);
408 if (cmd->error)
409 return cmd->error;
410
411 if (buf && buf_len) {
412 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
413 if (err < 0) {
414 dev_dbg(sdmmc_dev(host),
415 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
416 return err;
417 }
418 }
419
420 rtsx_pci_init_cmd(pcr);
421 sd_cmd_set_data_len(pcr, 1, byte_cnt);
422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
423 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
424 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
425 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
426 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
427 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
428 SD_TRANSFER_END, SD_TRANSFER_END);
429
430 err = rtsx_pci_send_cmd(pcr, timeout);
431 if (err < 0) {
432 sd_print_debug_regs(host);
433 dev_dbg(sdmmc_dev(host),
434 "rtsx_pci_send_cmd fail (err = %d)\n", err);
435 return err;
436 }
437
438 return 0;
439 }
440
441 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
442 struct mmc_request *mrq)
443 {
444 struct rtsx_pcr *pcr = host->pcr;
445 struct mmc_host *mmc = host->mmc;
446 struct mmc_card *card = mmc->card;
447 struct mmc_command *cmd = mrq->cmd;
448 struct mmc_data *data = mrq->data;
449 int uhs = mmc_card_uhs(card);
450 u8 cfg2 = 0;
451 int err;
452 int resp_type;
453 size_t data_len = data->blksz * data->blocks;
454
455 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
456 __func__, cmd->opcode, cmd->arg);
457
458 resp_type = sd_response_type(cmd);
459 if (resp_type < 0)
460 return resp_type;
461
462 if (!uhs)
463 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
464
465 rtsx_pci_init_cmd(pcr);
466 sd_cmd_set_sd_cmd(pcr, cmd);
467 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
469 DMA_DONE_INT, DMA_DONE_INT);
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
471 0xFF, (u8)(data_len >> 24));
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
473 0xFF, (u8)(data_len >> 16));
474 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
475 0xFF, (u8)(data_len >> 8));
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
477 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
478 0x03 | DMA_PACK_SIZE_MASK,
479 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
480 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
481 0x01, RING_BUFFER);
482 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
483 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
484 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
485 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
486 SD_TRANSFER_END, SD_TRANSFER_END);
487 rtsx_pci_send_cmd_no_wait(pcr);
488
489 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
490 if (err < 0) {
491 sd_print_debug_regs(host);
492 sd_clear_error(host);
493 return err;
494 }
495
496 return 0;
497 }
498
499 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
500 struct mmc_request *mrq)
501 {
502 struct rtsx_pcr *pcr = host->pcr;
503 struct mmc_host *mmc = host->mmc;
504 struct mmc_card *card = mmc->card;
505 struct mmc_command *cmd = mrq->cmd;
506 struct mmc_data *data = mrq->data;
507 int uhs = mmc_card_uhs(card);
508 u8 cfg2;
509 int err;
510 size_t data_len = data->blksz * data->blocks;
511
512 sd_send_cmd_get_rsp(host, cmd);
513 if (cmd->error)
514 return cmd->error;
515
516 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
517 __func__, cmd->opcode, cmd->arg);
518
519 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
520 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
521
522 if (!uhs)
523 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
524
525 rtsx_pci_init_cmd(pcr);
526 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
528 DMA_DONE_INT, DMA_DONE_INT);
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
530 0xFF, (u8)(data_len >> 24));
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
532 0xFF, (u8)(data_len >> 16));
533 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
534 0xFF, (u8)(data_len >> 8));
535 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
536 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
537 0x03 | DMA_PACK_SIZE_MASK,
538 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
539 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
540 0x01, RING_BUFFER);
541 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
542 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
543 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
544 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
545 SD_TRANSFER_END, SD_TRANSFER_END);
546 rtsx_pci_send_cmd_no_wait(pcr);
547 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
548 if (err < 0) {
549 sd_clear_error(host);
550 return err;
551 }
552
553 return 0;
554 }
555
556 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
557 {
558 struct mmc_data *data = mrq->data;
559
560 if (host->sg_count < 0) {
561 data->error = host->sg_count;
562 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
563 __func__, host->sg_count);
564 return data->error;
565 }
566
567 if (data->flags & MMC_DATA_READ)
568 return sd_read_long_data(host, mrq);
569
570 return sd_write_long_data(host, mrq);
571 }
572
573 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
574 {
575 rtsx_pci_write_register(host->pcr, SD_CFG1,
576 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
577 }
578
579 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
580 {
581 rtsx_pci_write_register(host->pcr, SD_CFG1,
582 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
583 }
584
585 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
586 struct mmc_request *mrq)
587 {
588 struct mmc_command *cmd = mrq->cmd;
589 struct mmc_data *data = mrq->data;
590 u8 *buf;
591
592 buf = kzalloc(data->blksz, GFP_NOIO);
593 if (!buf) {
594 cmd->error = -ENOMEM;
595 return;
596 }
597
598 if (data->flags & MMC_DATA_READ) {
599 if (host->initial_mode)
600 sd_disable_initial_mode(host);
601
602 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
603 data->blksz, 200);
604
605 if (host->initial_mode)
606 sd_enable_initial_mode(host);
607
608 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
609 } else {
610 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
611
612 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
613 data->blksz, 200);
614 }
615
616 kfree(buf);
617 }
618
619 static int sd_change_phase(struct realtek_pci_sdmmc *host,
620 u8 sample_point, bool rx)
621 {
622 struct rtsx_pcr *pcr = host->pcr;
623 int err;
624
625 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
626 __func__, rx ? "RX" : "TX", sample_point);
627
628 rtsx_pci_init_cmd(pcr);
629
630 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
631 if (rx)
632 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
633 SD_VPRX_CTL, 0x1F, sample_point);
634 else
635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
636 SD_VPTX_CTL, 0x1F, sample_point);
637 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
638 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
639 PHASE_NOT_RESET, PHASE_NOT_RESET);
640 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
641 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
642
643 err = rtsx_pci_send_cmd(pcr, 100);
644 if (err < 0)
645 return err;
646
647 return 0;
648 }
649
650 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
651 {
652 bit %= RTSX_PHASE_MAX;
653 return phase_map & (1 << bit);
654 }
655
656 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
657 {
658 int i;
659
660 for (i = 0; i < RTSX_PHASE_MAX; i++) {
661 if (test_phase_bit(phase_map, start_bit + i) == 0)
662 return i;
663 }
664 return RTSX_PHASE_MAX;
665 }
666
667 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
668 {
669 int start = 0, len = 0;
670 int start_final = 0, len_final = 0;
671 u8 final_phase = 0xFF;
672
673 if (phase_map == 0) {
674 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
675 return final_phase;
676 }
677
678 while (start < RTSX_PHASE_MAX) {
679 len = sd_get_phase_len(phase_map, start);
680 if (len_final < len) {
681 start_final = start;
682 len_final = len;
683 }
684 start += len ? len : 1;
685 }
686
687 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
688 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
689 phase_map, len_final, final_phase);
690
691 return final_phase;
692 }
693
694 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
695 {
696 int err, i;
697 u8 val = 0;
698
699 for (i = 0; i < 100; i++) {
700 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
701 if (val & SD_DATA_IDLE)
702 return;
703
704 udelay(100);
705 }
706 }
707
708 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
709 u8 opcode, u8 sample_point)
710 {
711 int err;
712 struct mmc_command cmd = {0};
713
714 err = sd_change_phase(host, sample_point, true);
715 if (err < 0)
716 return err;
717
718 cmd.opcode = opcode;
719 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
720 if (err < 0) {
721 /* Wait till SD DATA IDLE */
722 sd_wait_data_idle(host);
723 sd_clear_error(host);
724 return err;
725 }
726
727 return 0;
728 }
729
730 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
731 u8 opcode, u32 *phase_map)
732 {
733 int err, i;
734 u32 raw_phase_map = 0;
735
736 for (i = 0; i < RTSX_PHASE_MAX; i++) {
737 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
738 if (err == 0)
739 raw_phase_map |= 1 << i;
740 }
741
742 if (phase_map)
743 *phase_map = raw_phase_map;
744
745 return 0;
746 }
747
748 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
749 {
750 int err, i;
751 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
752 u8 final_phase;
753
754 for (i = 0; i < RX_TUNING_CNT; i++) {
755 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
756 if (err < 0)
757 return err;
758
759 if (raw_phase_map[i] == 0)
760 break;
761 }
762
763 phase_map = 0xFFFFFFFF;
764 for (i = 0; i < RX_TUNING_CNT; i++) {
765 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
766 i, raw_phase_map[i]);
767 phase_map &= raw_phase_map[i];
768 }
769 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
770
771 if (phase_map) {
772 final_phase = sd_search_final_phase(host, phase_map);
773 if (final_phase == 0xFF)
774 return -EINVAL;
775
776 err = sd_change_phase(host, final_phase, true);
777 if (err < 0)
778 return err;
779 } else {
780 return -EINVAL;
781 }
782
783 return 0;
784 }
785
786 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
787 struct mmc_data *data)
788 {
789 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
790 }
791
792 static inline int sd_rw_cmd(struct mmc_command *cmd)
793 {
794 return mmc_op_multi(cmd->opcode) ||
795 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
796 (cmd->opcode == MMC_WRITE_BLOCK);
797 }
798
799 static void sd_request(struct work_struct *work)
800 {
801 struct realtek_pci_sdmmc *host = container_of(work,
802 struct realtek_pci_sdmmc, work);
803 struct rtsx_pcr *pcr = host->pcr;
804
805 struct mmc_host *mmc = host->mmc;
806 struct mmc_request *mrq = host->mrq;
807 struct mmc_command *cmd = mrq->cmd;
808 struct mmc_data *data = mrq->data;
809
810 unsigned int data_size = 0;
811 int err;
812
813 if (host->eject || !sd_get_cd_int(host)) {
814 cmd->error = -ENOMEDIUM;
815 goto finish;
816 }
817
818 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
819 if (err) {
820 cmd->error = err;
821 goto finish;
822 }
823
824 mutex_lock(&pcr->pcr_mutex);
825
826 rtsx_pci_start_run(pcr);
827
828 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
829 host->initial_mode, host->double_clk, host->vpclk);
830 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
831 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
832 CARD_SHARE_MASK, CARD_SHARE_48_SD);
833
834 mutex_lock(&host->host_mutex);
835 host->mrq = mrq;
836 mutex_unlock(&host->host_mutex);
837
838 if (mrq->data)
839 data_size = data->blocks * data->blksz;
840
841 if (!data_size) {
842 sd_send_cmd_get_rsp(host, cmd);
843 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
844 cmd->error = sd_rw_multi(host, mrq);
845 if (!host->using_cookie)
846 sdmmc_post_req(host->mmc, host->mrq, 0);
847
848 if (mmc_op_multi(cmd->opcode) && mrq->stop)
849 sd_send_cmd_get_rsp(host, mrq->stop);
850 } else {
851 sd_normal_rw(host, mrq);
852 }
853
854 if (mrq->data) {
855 if (cmd->error || data->error)
856 data->bytes_xfered = 0;
857 else
858 data->bytes_xfered = data->blocks * data->blksz;
859 }
860
861 mutex_unlock(&pcr->pcr_mutex);
862
863 finish:
864 if (cmd->error) {
865 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
866 cmd->opcode, cmd->arg, cmd->error);
867 }
868
869 mutex_lock(&host->host_mutex);
870 host->mrq = NULL;
871 mutex_unlock(&host->host_mutex);
872
873 mmc_request_done(mmc, mrq);
874 }
875
876 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
877 {
878 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
879 struct mmc_data *data = mrq->data;
880
881 mutex_lock(&host->host_mutex);
882 host->mrq = mrq;
883 mutex_unlock(&host->host_mutex);
884
885 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
886 host->using_cookie = sd_pre_dma_transfer(host, data, false);
887
888 queue_work(host->workq, &host->work);
889 }
890
891 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
892 unsigned char bus_width)
893 {
894 int err = 0;
895 u8 width[] = {
896 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
897 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
898 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
899 };
900
901 if (bus_width <= MMC_BUS_WIDTH_8)
902 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
903 0x03, width[bus_width]);
904
905 return err;
906 }
907
908 static int sd_power_on(struct realtek_pci_sdmmc *host)
909 {
910 struct rtsx_pcr *pcr = host->pcr;
911 int err;
912
913 if (host->power_state == SDMMC_POWER_ON)
914 return 0;
915
916 rtsx_pci_init_cmd(pcr);
917 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
919 CARD_SHARE_MASK, CARD_SHARE_48_SD);
920 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
921 SD_CLK_EN, SD_CLK_EN);
922 err = rtsx_pci_send_cmd(pcr, 100);
923 if (err < 0)
924 return err;
925
926 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
927 if (err < 0)
928 return err;
929
930 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
931 if (err < 0)
932 return err;
933
934 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
935 if (err < 0)
936 return err;
937
938 host->power_state = SDMMC_POWER_ON;
939 return 0;
940 }
941
942 static int sd_power_off(struct realtek_pci_sdmmc *host)
943 {
944 struct rtsx_pcr *pcr = host->pcr;
945 int err;
946
947 host->power_state = SDMMC_POWER_OFF;
948
949 rtsx_pci_init_cmd(pcr);
950
951 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
952 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
953
954 err = rtsx_pci_send_cmd(pcr, 100);
955 if (err < 0)
956 return err;
957
958 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
959 if (err < 0)
960 return err;
961
962 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
963 }
964
965 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
966 unsigned char power_mode)
967 {
968 int err;
969
970 if (power_mode == MMC_POWER_OFF)
971 err = sd_power_off(host);
972 else
973 err = sd_power_on(host);
974
975 return err;
976 }
977
978 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
979 {
980 struct rtsx_pcr *pcr = host->pcr;
981 int err = 0;
982
983 rtsx_pci_init_cmd(pcr);
984
985 switch (timing) {
986 case MMC_TIMING_UHS_SDR104:
987 case MMC_TIMING_UHS_SDR50:
988 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
989 0x0C | SD_ASYNC_FIFO_NOT_RST,
990 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
992 CLK_LOW_FREQ, CLK_LOW_FREQ);
993 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
994 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
996 break;
997
998 case MMC_TIMING_MMC_DDR52:
999 case MMC_TIMING_UHS_DDR50:
1000 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1001 0x0C | SD_ASYNC_FIFO_NOT_RST,
1002 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1004 CLK_LOW_FREQ, CLK_LOW_FREQ);
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1006 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1008 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1009 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1011 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1012 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1013 break;
1014
1015 case MMC_TIMING_MMC_HS:
1016 case MMC_TIMING_SD_HS:
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1018 0x0C, SD_20_MODE);
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1020 CLK_LOW_FREQ, CLK_LOW_FREQ);
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1022 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1025 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1027 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1028 break;
1029
1030 default:
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1032 SD_CFG1, 0x0C, SD_20_MODE);
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1034 CLK_LOW_FREQ, CLK_LOW_FREQ);
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1036 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1039 SD_PUSH_POINT_CTL, 0xFF, 0);
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1041 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1042 break;
1043 }
1044
1045 err = rtsx_pci_send_cmd(pcr, 100);
1046
1047 return err;
1048 }
1049
1050 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1051 {
1052 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1053 struct rtsx_pcr *pcr = host->pcr;
1054
1055 if (host->eject)
1056 return;
1057
1058 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1059 return;
1060
1061 mutex_lock(&pcr->pcr_mutex);
1062
1063 rtsx_pci_start_run(pcr);
1064
1065 sd_set_bus_width(host, ios->bus_width);
1066 sd_set_power_mode(host, ios->power_mode);
1067 sd_set_timing(host, ios->timing);
1068
1069 host->vpclk = false;
1070 host->double_clk = true;
1071
1072 switch (ios->timing) {
1073 case MMC_TIMING_UHS_SDR104:
1074 case MMC_TIMING_UHS_SDR50:
1075 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1076 host->vpclk = true;
1077 host->double_clk = false;
1078 break;
1079 case MMC_TIMING_MMC_DDR52:
1080 case MMC_TIMING_UHS_DDR50:
1081 case MMC_TIMING_UHS_SDR25:
1082 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1083 break;
1084 default:
1085 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1086 break;
1087 }
1088
1089 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1090
1091 host->clock = ios->clock;
1092 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1093 host->initial_mode, host->double_clk, host->vpclk);
1094
1095 mutex_unlock(&pcr->pcr_mutex);
1096 }
1097
1098 static int sdmmc_get_ro(struct mmc_host *mmc)
1099 {
1100 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1101 struct rtsx_pcr *pcr = host->pcr;
1102 int ro = 0;
1103 u32 val;
1104
1105 if (host->eject)
1106 return -ENOMEDIUM;
1107
1108 mutex_lock(&pcr->pcr_mutex);
1109
1110 rtsx_pci_start_run(pcr);
1111
1112 /* Check SD mechanical write-protect switch */
1113 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1114 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1115 if (val & SD_WRITE_PROTECT)
1116 ro = 1;
1117
1118 mutex_unlock(&pcr->pcr_mutex);
1119
1120 return ro;
1121 }
1122
1123 static int sdmmc_get_cd(struct mmc_host *mmc)
1124 {
1125 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1126 struct rtsx_pcr *pcr = host->pcr;
1127 int cd = 0;
1128 u32 val;
1129
1130 if (host->eject)
1131 return cd;
1132
1133 mutex_lock(&pcr->pcr_mutex);
1134
1135 rtsx_pci_start_run(pcr);
1136
1137 /* Check SD card detect */
1138 val = rtsx_pci_card_exist(pcr);
1139 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1140 if (val & SD_EXIST)
1141 cd = 1;
1142
1143 mutex_unlock(&pcr->pcr_mutex);
1144
1145 return cd;
1146 }
1147
1148 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1149 {
1150 struct rtsx_pcr *pcr = host->pcr;
1151 int err;
1152 u8 stat;
1153
1154 /* Reference to Signal Voltage Switch Sequence in SD spec.
1155 * Wait for a period of time so that the card can drive SD_CMD and
1156 * SD_DAT[3:0] to low after sending back CMD11 response.
1157 */
1158 mdelay(1);
1159
1160 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1161 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1162 * abort the voltage switch sequence;
1163 */
1164 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1165 if (err < 0)
1166 return err;
1167
1168 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1169 SD_DAT1_STATUS | SD_DAT0_STATUS))
1170 return -EINVAL;
1171
1172 /* Stop toggle SD clock */
1173 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1174 0xFF, SD_CLK_FORCE_STOP);
1175 if (err < 0)
1176 return err;
1177
1178 return 0;
1179 }
1180
1181 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1182 {
1183 struct rtsx_pcr *pcr = host->pcr;
1184 int err;
1185 u8 stat, mask, val;
1186
1187 /* Wait 1.8V output of voltage regulator in card stable */
1188 msleep(50);
1189
1190 /* Toggle SD clock again */
1191 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1192 if (err < 0)
1193 return err;
1194
1195 /* Wait for a period of time so that the card can drive
1196 * SD_DAT[3:0] to high at 1.8V
1197 */
1198 msleep(20);
1199
1200 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1201 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1202 if (err < 0)
1203 return err;
1204
1205 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1206 SD_DAT1_STATUS | SD_DAT0_STATUS;
1207 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1208 SD_DAT1_STATUS | SD_DAT0_STATUS;
1209 if ((stat & mask) != val) {
1210 dev_dbg(sdmmc_dev(host),
1211 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1212 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1213 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1214 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1215 return -EINVAL;
1216 }
1217
1218 return 0;
1219 }
1220
1221 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1222 {
1223 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1224 struct rtsx_pcr *pcr = host->pcr;
1225 int err = 0;
1226 u8 voltage;
1227
1228 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1229 __func__, ios->signal_voltage);
1230
1231 if (host->eject)
1232 return -ENOMEDIUM;
1233
1234 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1235 if (err)
1236 return err;
1237
1238 mutex_lock(&pcr->pcr_mutex);
1239
1240 rtsx_pci_start_run(pcr);
1241
1242 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1243 voltage = OUTPUT_3V3;
1244 else
1245 voltage = OUTPUT_1V8;
1246
1247 if (voltage == OUTPUT_1V8) {
1248 err = sd_wait_voltage_stable_1(host);
1249 if (err < 0)
1250 goto out;
1251 }
1252
1253 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1254 if (err < 0)
1255 goto out;
1256
1257 if (voltage == OUTPUT_1V8) {
1258 err = sd_wait_voltage_stable_2(host);
1259 if (err < 0)
1260 goto out;
1261 }
1262
1263 out:
1264 /* Stop toggle SD clock in idle */
1265 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1266 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1267
1268 mutex_unlock(&pcr->pcr_mutex);
1269
1270 return err;
1271 }
1272
1273 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1274 {
1275 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1276 struct rtsx_pcr *pcr = host->pcr;
1277 int err = 0;
1278
1279 if (host->eject)
1280 return -ENOMEDIUM;
1281
1282 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1283 if (err)
1284 return err;
1285
1286 mutex_lock(&pcr->pcr_mutex);
1287
1288 rtsx_pci_start_run(pcr);
1289
1290 /* Set initial TX phase */
1291 switch (mmc->ios.timing) {
1292 case MMC_TIMING_UHS_SDR104:
1293 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1294 break;
1295
1296 case MMC_TIMING_UHS_SDR50:
1297 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1298 break;
1299
1300 case MMC_TIMING_UHS_DDR50:
1301 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1302 break;
1303
1304 default:
1305 err = 0;
1306 }
1307
1308 if (err)
1309 goto out;
1310
1311 /* Tuning RX phase */
1312 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1313 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1314 err = sd_tuning_rx(host, opcode);
1315 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1316 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1317
1318 out:
1319 mutex_unlock(&pcr->pcr_mutex);
1320
1321 return err;
1322 }
1323
1324 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1325 .pre_req = sdmmc_pre_req,
1326 .post_req = sdmmc_post_req,
1327 .request = sdmmc_request,
1328 .set_ios = sdmmc_set_ios,
1329 .get_ro = sdmmc_get_ro,
1330 .get_cd = sdmmc_get_cd,
1331 .start_signal_voltage_switch = sdmmc_switch_voltage,
1332 .execute_tuning = sdmmc_execute_tuning,
1333 };
1334
1335 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1336 {
1337 struct mmc_host *mmc = host->mmc;
1338 struct rtsx_pcr *pcr = host->pcr;
1339
1340 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1341
1342 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1343 mmc->caps |= MMC_CAP_UHS_SDR50;
1344 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1345 mmc->caps |= MMC_CAP_UHS_SDR104;
1346 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1347 mmc->caps |= MMC_CAP_UHS_DDR50;
1348 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1349 mmc->caps |= MMC_CAP_1_8V_DDR;
1350 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1351 mmc->caps |= MMC_CAP_8_BIT_DATA;
1352 }
1353
1354 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1355 {
1356 struct mmc_host *mmc = host->mmc;
1357
1358 mmc->f_min = 250000;
1359 mmc->f_max = 208000000;
1360 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1361 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1362 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1363 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1364 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1365 mmc->max_current_330 = 400;
1366 mmc->max_current_180 = 800;
1367 mmc->ops = &realtek_pci_sdmmc_ops;
1368
1369 init_extra_caps(host);
1370
1371 mmc->max_segs = 256;
1372 mmc->max_seg_size = 65536;
1373 mmc->max_blk_size = 512;
1374 mmc->max_blk_count = 65535;
1375 mmc->max_req_size = 524288;
1376 }
1377
1378 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1379 {
1380 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1381
1382 host->cookie = -1;
1383 mmc_detect_change(host->mmc, 0);
1384 }
1385
1386 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1387 {
1388 struct mmc_host *mmc;
1389 struct realtek_pci_sdmmc *host;
1390 struct rtsx_pcr *pcr;
1391 struct pcr_handle *handle = pdev->dev.platform_data;
1392
1393 if (!handle)
1394 return -ENXIO;
1395
1396 pcr = handle->pcr;
1397 if (!pcr)
1398 return -ENXIO;
1399
1400 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1401
1402 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1403 if (!mmc)
1404 return -ENOMEM;
1405
1406 host = mmc_priv(mmc);
1407 host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME);
1408 if (!host->workq) {
1409 mmc_free_host(mmc);
1410 return -ENOMEM;
1411 }
1412 host->pcr = pcr;
1413 host->mmc = mmc;
1414 host->pdev = pdev;
1415 host->cookie = -1;
1416 host->power_state = SDMMC_POWER_OFF;
1417 INIT_WORK(&host->work, sd_request);
1418 platform_set_drvdata(pdev, host);
1419 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1420 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1421
1422 mutex_init(&host->host_mutex);
1423
1424 realtek_init_host(host);
1425
1426 mmc_add_host(mmc);
1427
1428 return 0;
1429 }
1430
1431 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1432 {
1433 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1434 struct rtsx_pcr *pcr;
1435 struct mmc_host *mmc;
1436
1437 if (!host)
1438 return 0;
1439
1440 pcr = host->pcr;
1441 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1442 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1443 mmc = host->mmc;
1444
1445 cancel_work_sync(&host->work);
1446
1447 mutex_lock(&host->host_mutex);
1448 if (host->mrq) {
1449 dev_dbg(&(pdev->dev),
1450 "%s: Controller removed during transfer\n",
1451 mmc_hostname(mmc));
1452
1453 rtsx_pci_complete_unfinished_transfer(pcr);
1454
1455 host->mrq->cmd->error = -ENOMEDIUM;
1456 if (host->mrq->stop)
1457 host->mrq->stop->error = -ENOMEDIUM;
1458 mmc_request_done(mmc, host->mrq);
1459 }
1460 mutex_unlock(&host->host_mutex);
1461
1462 mmc_remove_host(mmc);
1463 host->eject = true;
1464
1465 flush_workqueue(host->workq);
1466 destroy_workqueue(host->workq);
1467 host->workq = NULL;
1468
1469 mmc_free_host(mmc);
1470
1471 dev_dbg(&(pdev->dev),
1472 ": Realtek PCI-E SDMMC controller has been removed\n");
1473
1474 return 0;
1475 }
1476
1477 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1478 {
1479 .name = DRV_NAME_RTSX_PCI_SDMMC,
1480 }, {
1481 /* sentinel */
1482 }
1483 };
1484 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1485
1486 static struct platform_driver rtsx_pci_sdmmc_driver = {
1487 .probe = rtsx_pci_sdmmc_drv_probe,
1488 .remove = rtsx_pci_sdmmc_drv_remove,
1489 .id_table = rtsx_pci_sdmmc_ids,
1490 .driver = {
1491 .name = DRV_NAME_RTSX_PCI_SDMMC,
1492 },
1493 };
1494 module_platform_driver(rtsx_pci_sdmmc_driver);
1495
1496 MODULE_LICENSE("GPL");
1497 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1498 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
Linux with added FPC-III support