2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/slab.h>
23 #include "sdhci-pltfm.h"
25 #define CORE_MCI_VERSION 0x50
26 #define CORE_VERSION_MAJOR_SHIFT 28
27 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
28 #define CORE_VERSION_MINOR_MASK 0xff
30 #define CORE_HC_MODE 0x78
31 #define HC_MODE_EN 0x1
32 #define CORE_POWER 0x0
33 #define CORE_SW_RST BIT(7)
36 #define CORE_DLL_LOCK BIT(7)
37 #define CORE_DLL_EN BIT(16)
38 #define CORE_CDR_EN BIT(17)
39 #define CORE_CK_OUT_EN BIT(18)
40 #define CORE_CDR_EXT_EN BIT(19)
41 #define CORE_DLL_PDN BIT(29)
42 #define CORE_DLL_RST BIT(30)
43 #define CORE_DLL_CONFIG 0x100
44 #define CORE_DLL_STATUS 0x108
46 #define CORE_VENDOR_SPEC 0x10c
47 #define CORE_CLK_PWRSAVE BIT(1)
49 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
51 #define CDR_SELEXT_SHIFT 20
52 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
53 #define CMUX_SHIFT_PHASE_SHIFT 24
54 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
56 struct sdhci_msm_host
{
57 struct platform_device
*pdev
;
58 void __iomem
*core_mem
; /* MSM SDCC mapped address */
59 struct clk
*clk
; /* main SD/MMC bus clock */
60 struct clk
*pclk
; /* SDHC peripheral bus clock */
61 struct clk
*bus_clk
; /* SDHC bus voter clock */
63 struct sdhci_pltfm_data sdhci_msm_pdata
;
66 /* Platform specific tuning */
67 static inline int msm_dll_poll_ck_out_en(struct sdhci_host
*host
, u8 poll
)
71 struct mmc_host
*mmc
= host
->mmc
;
73 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
74 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
77 while (ck_out_en
!= poll
) {
78 if (--wait_cnt
== 0) {
79 dev_err(mmc_dev(mmc
), "%s: CK_OUT_EN bit is not %d\n",
80 mmc_hostname(mmc
), poll
);
85 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
92 static int msm_config_cm_dll_phase(struct sdhci_host
*host
, u8 phase
)
95 static const u8 grey_coded_phase_table
[] = {
96 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
97 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
101 struct mmc_host
*mmc
= host
->mmc
;
103 spin_lock_irqsave(&host
->lock
, flags
);
105 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
106 config
&= ~(CORE_CDR_EN
| CORE_CK_OUT_EN
);
107 config
|= (CORE_CDR_EXT_EN
| CORE_DLL_EN
);
108 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
110 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
111 rc
= msm_dll_poll_ck_out_en(host
, 0);
116 * Write the selected DLL clock output phase (0 ... 15)
117 * to CDR_SELEXT bit field of DLL_CONFIG register.
119 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
120 config
&= ~CDR_SELEXT_MASK
;
121 config
|= grey_coded_phase_table
[phase
] << CDR_SELEXT_SHIFT
;
122 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
124 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
125 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
126 | CORE_CK_OUT_EN
), host
->ioaddr
+ CORE_DLL_CONFIG
);
128 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
129 rc
= msm_dll_poll_ck_out_en(host
, 1);
133 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
134 config
|= CORE_CDR_EN
;
135 config
&= ~CORE_CDR_EXT_EN
;
136 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
140 dev_err(mmc_dev(mmc
), "%s: Failed to set DLL phase: %d\n",
141 mmc_hostname(mmc
), phase
);
143 spin_unlock_irqrestore(&host
->lock
, flags
);
148 * Find out the greatest range of consecuitive selected
149 * DLL clock output phases that can be used as sampling
150 * setting for SD3.0 UHS-I card read operation (in SDR104
151 * timing mode) or for eMMC4.5 card read operation (in HS200
153 * Select the 3/4 of the range and configure the DLL with the
154 * selected DLL clock output phase.
157 static int msm_find_most_appropriate_phase(struct sdhci_host
*host
,
158 u8
*phase_table
, u8 total_phases
)
161 u8 ranges
[MAX_PHASES
][MAX_PHASES
] = { {0}, {0} };
162 u8 phases_per_row
[MAX_PHASES
] = { 0 };
163 int row_index
= 0, col_index
= 0, selected_row_index
= 0, curr_max
= 0;
164 int i
, cnt
, phase_0_raw_index
= 0, phase_15_raw_index
= 0;
165 bool phase_0_found
= false, phase_15_found
= false;
166 struct mmc_host
*mmc
= host
->mmc
;
168 if (!total_phases
|| (total_phases
> MAX_PHASES
)) {
169 dev_err(mmc_dev(mmc
), "%s: Invalid argument: total_phases=%d\n",
170 mmc_hostname(mmc
), total_phases
);
174 for (cnt
= 0; cnt
< total_phases
; cnt
++) {
175 ranges
[row_index
][col_index
] = phase_table
[cnt
];
176 phases_per_row
[row_index
] += 1;
179 if ((cnt
+ 1) == total_phases
) {
181 /* check if next phase in phase_table is consecutive or not */
182 } else if ((phase_table
[cnt
] + 1) != phase_table
[cnt
+ 1]) {
188 if (row_index
>= MAX_PHASES
)
191 /* Check if phase-0 is present in first valid window? */
193 phase_0_found
= true;
194 phase_0_raw_index
= 0;
195 /* Check if cycle exist between 2 valid windows */
196 for (cnt
= 1; cnt
<= row_index
; cnt
++) {
197 if (phases_per_row
[cnt
]) {
198 for (i
= 0; i
< phases_per_row
[cnt
]; i
++) {
199 if (ranges
[cnt
][i
] == 15) {
200 phase_15_found
= true;
201 phase_15_raw_index
= cnt
;
209 /* If 2 valid windows form cycle then merge them as single window */
210 if (phase_0_found
&& phase_15_found
) {
211 /* number of phases in raw where phase 0 is present */
212 u8 phases_0
= phases_per_row
[phase_0_raw_index
];
213 /* number of phases in raw where phase 15 is present */
214 u8 phases_15
= phases_per_row
[phase_15_raw_index
];
216 if (phases_0
+ phases_15
>= MAX_PHASES
)
218 * If there are more than 1 phase windows then total
219 * number of phases in both the windows should not be
220 * more than or equal to MAX_PHASES.
224 /* Merge 2 cyclic windows */
226 for (cnt
= 0; cnt
< phases_0
; cnt
++) {
227 ranges
[phase_15_raw_index
][i
] =
228 ranges
[phase_0_raw_index
][cnt
];
229 if (++i
>= MAX_PHASES
)
233 phases_per_row
[phase_0_raw_index
] = 0;
234 phases_per_row
[phase_15_raw_index
] = phases_15
+ phases_0
;
237 for (cnt
= 0; cnt
<= row_index
; cnt
++) {
238 if (phases_per_row
[cnt
] > curr_max
) {
239 curr_max
= phases_per_row
[cnt
];
240 selected_row_index
= cnt
;
244 i
= (curr_max
* 3) / 4;
248 ret
= ranges
[selected_row_index
][i
];
250 if (ret
>= MAX_PHASES
) {
252 dev_err(mmc_dev(mmc
), "%s: Invalid phase selected=%d\n",
253 mmc_hostname(mmc
), ret
);
259 static inline void msm_cm_dll_set_freq(struct sdhci_host
*host
)
261 u32 mclk_freq
= 0, config
;
263 /* Program the MCLK value to MCLK_FREQ bit field */
264 if (host
->clock
<= 112000000)
266 else if (host
->clock
<= 125000000)
268 else if (host
->clock
<= 137000000)
270 else if (host
->clock
<= 150000000)
272 else if (host
->clock
<= 162000000)
274 else if (host
->clock
<= 175000000)
276 else if (host
->clock
<= 187000000)
278 else if (host
->clock
<= 200000000)
281 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
282 config
&= ~CMUX_SHIFT_PHASE_MASK
;
283 config
|= mclk_freq
<< CMUX_SHIFT_PHASE_SHIFT
;
284 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
287 /* Initialize the DLL (Programmable Delay Line) */
288 static int msm_init_cm_dll(struct sdhci_host
*host
)
290 struct mmc_host
*mmc
= host
->mmc
;
294 spin_lock_irqsave(&host
->lock
, flags
);
297 * Make sure that clock is always enabled when DLL
298 * tuning is in progress. Keeping PWRSAVE ON may
299 * turn off the clock.
301 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
)
302 & ~CORE_CLK_PWRSAVE
), host
->ioaddr
+ CORE_VENDOR_SPEC
);
304 /* Write 1 to DLL_RST bit of DLL_CONFIG register */
305 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
306 | CORE_DLL_RST
), host
->ioaddr
+ CORE_DLL_CONFIG
);
308 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
309 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
310 | CORE_DLL_PDN
), host
->ioaddr
+ CORE_DLL_CONFIG
);
311 msm_cm_dll_set_freq(host
);
313 /* Write 0 to DLL_RST bit of DLL_CONFIG register */
314 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
315 & ~CORE_DLL_RST
), host
->ioaddr
+ CORE_DLL_CONFIG
);
317 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
318 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
319 & ~CORE_DLL_PDN
), host
->ioaddr
+ CORE_DLL_CONFIG
);
321 /* Set DLL_EN bit to 1. */
322 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
323 | CORE_DLL_EN
), host
->ioaddr
+ CORE_DLL_CONFIG
);
325 /* Set CK_OUT_EN bit to 1. */
326 writel_relaxed((readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
)
327 | CORE_CK_OUT_EN
), host
->ioaddr
+ CORE_DLL_CONFIG
);
329 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
330 while (!(readl_relaxed(host
->ioaddr
+ CORE_DLL_STATUS
) &
332 /* max. wait for 50us sec for LOCK bit to be set */
333 if (--wait_cnt
== 0) {
334 dev_err(mmc_dev(mmc
), "%s: DLL failed to LOCK\n",
336 spin_unlock_irqrestore(&host
->lock
, flags
);
342 spin_unlock_irqrestore(&host
->lock
, flags
);
346 static int sdhci_msm_execute_tuning(struct sdhci_host
*host
, u32 opcode
)
348 int tuning_seq_cnt
= 3;
349 u8 phase
, tuned_phases
[16], tuned_phase_cnt
= 0;
351 struct mmc_host
*mmc
= host
->mmc
;
352 struct mmc_ios ios
= host
->mmc
->ios
;
355 * Tuning is required for SDR104, HS200 and HS400 cards and
356 * if clock frequency is greater than 100MHz in these modes.
358 if (host
->clock
<= 100 * 1000 * 1000 ||
359 !((ios
.timing
== MMC_TIMING_MMC_HS200
) ||
360 (ios
.timing
== MMC_TIMING_UHS_SDR104
)))
364 /* First of all reset the tuning block */
365 rc
= msm_init_cm_dll(host
);
371 /* Set the phase in delay line hw block */
372 rc
= msm_config_cm_dll_phase(host
, phase
);
376 rc
= mmc_send_tuning(mmc
, opcode
, NULL
);
378 /* Tuning is successful at this tuning point */
379 tuned_phases
[tuned_phase_cnt
++] = phase
;
380 dev_dbg(mmc_dev(mmc
), "%s: Found good phase = %d\n",
381 mmc_hostname(mmc
), phase
);
383 } while (++phase
< ARRAY_SIZE(tuned_phases
));
385 if (tuned_phase_cnt
) {
386 rc
= msm_find_most_appropriate_phase(host
, tuned_phases
,
394 * Finally set the selected phase in delay
397 rc
= msm_config_cm_dll_phase(host
, phase
);
400 dev_dbg(mmc_dev(mmc
), "%s: Setting the tuning phase to %d\n",
401 mmc_hostname(mmc
), phase
);
403 if (--tuning_seq_cnt
)
406 dev_dbg(mmc_dev(mmc
), "%s: No tuning point found\n",
414 static const struct of_device_id sdhci_msm_dt_match
[] = {
415 { .compatible
= "qcom,sdhci-msm-v4" },
419 MODULE_DEVICE_TABLE(of
, sdhci_msm_dt_match
);
421 static struct sdhci_ops sdhci_msm_ops
= {
422 .platform_execute_tuning
= sdhci_msm_execute_tuning
,
423 .reset
= sdhci_reset
,
424 .set_clock
= sdhci_set_clock
,
425 .set_bus_width
= sdhci_set_bus_width
,
426 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
429 static int sdhci_msm_probe(struct platform_device
*pdev
)
431 struct sdhci_host
*host
;
432 struct sdhci_pltfm_host
*pltfm_host
;
433 struct sdhci_msm_host
*msm_host
;
434 struct resource
*core_memres
;
436 u16 host_version
, core_minor
;
437 u32 core_version
, caps
;
440 msm_host
= devm_kzalloc(&pdev
->dev
, sizeof(*msm_host
), GFP_KERNEL
);
444 msm_host
->sdhci_msm_pdata
.ops
= &sdhci_msm_ops
;
445 host
= sdhci_pltfm_init(pdev
, &msm_host
->sdhci_msm_pdata
, 0);
447 return PTR_ERR(host
);
449 pltfm_host
= sdhci_priv(host
);
450 pltfm_host
->priv
= msm_host
;
451 msm_host
->mmc
= host
->mmc
;
452 msm_host
->pdev
= pdev
;
454 ret
= mmc_of_parse(host
->mmc
);
458 sdhci_get_of_property(pdev
);
460 /* Setup SDCC bus voter clock. */
461 msm_host
->bus_clk
= devm_clk_get(&pdev
->dev
, "bus");
462 if (!IS_ERR(msm_host
->bus_clk
)) {
463 /* Vote for max. clk rate for max. performance */
464 ret
= clk_set_rate(msm_host
->bus_clk
, INT_MAX
);
467 ret
= clk_prepare_enable(msm_host
->bus_clk
);
472 /* Setup main peripheral bus clock */
473 msm_host
->pclk
= devm_clk_get(&pdev
->dev
, "iface");
474 if (IS_ERR(msm_host
->pclk
)) {
475 ret
= PTR_ERR(msm_host
->pclk
);
476 dev_err(&pdev
->dev
, "Perpheral clk setup failed (%d)\n", ret
);
477 goto bus_clk_disable
;
480 ret
= clk_prepare_enable(msm_host
->pclk
);
482 goto bus_clk_disable
;
484 /* Setup SDC MMC clock */
485 msm_host
->clk
= devm_clk_get(&pdev
->dev
, "core");
486 if (IS_ERR(msm_host
->clk
)) {
487 ret
= PTR_ERR(msm_host
->clk
);
488 dev_err(&pdev
->dev
, "SDC MMC clk setup failed (%d)\n", ret
);
492 /* Vote for maximum clock rate for maximum performance */
493 ret
= clk_set_rate(msm_host
->clk
, INT_MAX
);
495 dev_warn(&pdev
->dev
, "core clock boost failed\n");
497 ret
= clk_prepare_enable(msm_host
->clk
);
501 core_memres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
502 msm_host
->core_mem
= devm_ioremap_resource(&pdev
->dev
, core_memres
);
504 if (IS_ERR(msm_host
->core_mem
)) {
505 dev_err(&pdev
->dev
, "Failed to remap registers\n");
506 ret
= PTR_ERR(msm_host
->core_mem
);
510 /* Reset the core and Enable SDHC mode */
511 writel_relaxed(readl_relaxed(msm_host
->core_mem
+ CORE_POWER
) |
512 CORE_SW_RST
, msm_host
->core_mem
+ CORE_POWER
);
514 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
515 usleep_range(1000, 5000);
516 if (readl(msm_host
->core_mem
+ CORE_POWER
) & CORE_SW_RST
) {
517 dev_err(&pdev
->dev
, "Stuck in reset\n");
522 /* Set HC_MODE_EN bit in HC_MODE register */
523 writel_relaxed(HC_MODE_EN
, (msm_host
->core_mem
+ CORE_HC_MODE
));
525 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
526 host
->quirks
|= SDHCI_QUIRK_SINGLE_POWER_WRITE
;
528 host_version
= readw_relaxed((host
->ioaddr
+ SDHCI_HOST_VERSION
));
529 dev_dbg(&pdev
->dev
, "Host Version: 0x%x Vendor Version 0x%x\n",
530 host_version
, ((host_version
& SDHCI_VENDOR_VER_MASK
) >>
531 SDHCI_VENDOR_VER_SHIFT
));
533 core_version
= readl_relaxed(msm_host
->core_mem
+ CORE_MCI_VERSION
);
534 core_major
= (core_version
& CORE_VERSION_MAJOR_MASK
) >>
535 CORE_VERSION_MAJOR_SHIFT
;
536 core_minor
= core_version
& CORE_VERSION_MINOR_MASK
;
537 dev_dbg(&pdev
->dev
, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
538 core_version
, core_major
, core_minor
);
541 * Support for some capabilities is not advertised by newer
542 * controller versions and must be explicitly enabled.
544 if (core_major
>= 1 && core_minor
!= 0x11 && core_minor
!= 0x12) {
545 caps
= readl_relaxed(host
->ioaddr
+ SDHCI_CAPABILITIES
);
546 caps
|= SDHCI_CAN_VDD_300
| SDHCI_CAN_DO_8BIT
;
547 writel_relaxed(caps
, host
->ioaddr
+
548 CORE_VENDOR_SPEC_CAPABILITIES0
);
551 ret
= sdhci_add_host(host
);
558 clk_disable_unprepare(msm_host
->clk
);
560 clk_disable_unprepare(msm_host
->pclk
);
562 if (!IS_ERR(msm_host
->bus_clk
))
563 clk_disable_unprepare(msm_host
->bus_clk
);
565 sdhci_pltfm_free(pdev
);
569 static int sdhci_msm_remove(struct platform_device
*pdev
)
571 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
572 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
573 struct sdhci_msm_host
*msm_host
= pltfm_host
->priv
;
574 int dead
= (readl_relaxed(host
->ioaddr
+ SDHCI_INT_STATUS
) ==
577 sdhci_remove_host(host
, dead
);
578 sdhci_pltfm_free(pdev
);
579 clk_disable_unprepare(msm_host
->clk
);
580 clk_disable_unprepare(msm_host
->pclk
);
581 if (!IS_ERR(msm_host
->bus_clk
))
582 clk_disable_unprepare(msm_host
->bus_clk
);
586 static struct platform_driver sdhci_msm_driver
= {
587 .probe
= sdhci_msm_probe
,
588 .remove
= sdhci_msm_remove
,
591 .of_match_table
= sdhci_msm_dt_match
,
595 module_platform_driver(sdhci_msm_driver
);
597 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
598 MODULE_LICENSE("GPL v2");