drivers/pwm/pwm-tegra.c

   1 /*
   2  * drivers/pwm/pwm-tegra.c
   3  *
   4  * Tegra pulse-width-modulation controller driver
   5  *
   6  * Copyright (c) 2010, NVIDIA Corporation.
   7  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/of.h>
  29 #include <linux/pwm.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/slab.h>
  32
  33 #define PWM_ENABLE      (1 << 31)
  34 #define PWM_DUTY_WIDTH  8
  35 #define PWM_DUTY_SHIFT  16
  36 #define PWM_SCALE_WIDTH 13
  37 #define PWM_SCALE_SHIFT 0
  38
  39 #define NUM_PWM 4
  40
  41 struct tegra_pwm_chip {
  42         struct pwm_chip         chip;
  43         struct device           *dev;
  44
  45         struct clk              *clk;
  46
  47         void __iomem            *mmio_base;
  48 };
  49
  50 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
  51 {
  52         return container_of(chip, struct tegra_pwm_chip, chip);
  53 }
  54
  55 static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
  56 {
  57         return readl(chip->mmio_base + (num << 4));
  58 }
  59
  60 static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
  61                              unsigned long val)
  62 {
  63         writel(val, chip->mmio_base + (num << 4));
  64 }
  65
  66 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  67                             int duty_ns, int period_ns)
  68 {
  69         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
  70         unsigned long long c;
  71         unsigned long rate, hz;
  72         unsigned long long ns100 = NSEC_PER_SEC;
  73         u32 val = 0;
  74         int err;
  75
  76         /*
  77          * Convert from duty_ns / period_ns to a fixed number of duty ticks
  78          * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
  79          * nearest integer during division.
  80          */
  81         c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
  82         do_div(c, period_ns);
  83
  84         val = (u32)c << PWM_DUTY_SHIFT;
  85
  86         /*
  87          * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
  88          * cycles at the PWM clock rate will take period_ns nanoseconds.
  89          */
  90         rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
  91
  92         /* Consider precision in PWM_SCALE_WIDTH rate calculation */
  93         ns100 *= 100;
  94         hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
  95         rate = DIV_ROUND_CLOSEST(rate * 100, hz);
  96
  97         /*
  98          * Since the actual PWM divider is the register's frequency divider
  99          * field minus 1, we need to decrement to get the correct value to
 100          * write to the register.
 101          */
 102         if (rate > 0)
 103                 rate--;
 104
 105         /*
 106          * Make sure that the rate will fit in the register's frequency
 107          * divider field.
 108          */
 109         if (rate >> PWM_SCALE_WIDTH)
 110                 return -EINVAL;
 111
 112         val |= rate << PWM_SCALE_SHIFT;
 113
 114         /*
 115          * If the PWM channel is disabled, make sure to turn on the clock
 116          * before writing the register. Otherwise, keep it enabled.
 117          */
 118         if (!pwm_is_enabled(pwm)) {
 119                 err = clk_prepare_enable(pc->clk);
 120                 if (err < 0)
 121                         return err;
 122         } else
 123                 val |= PWM_ENABLE;
 124
 125         pwm_writel(pc, pwm->hwpwm, val);
 126
 127         /*
 128          * If the PWM is not enabled, turn the clock off again to save power.
 129          */
 130         if (!pwm_is_enabled(pwm))
 131                 clk_disable_unprepare(pc->clk);
 132
 133         return 0;
 134 }
 135
 136 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 137 {
 138         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
 139         int rc = 0;
 140         u32 val;
 141
 142         rc = clk_prepare_enable(pc->clk);
 143         if (rc < 0)
 144                 return rc;
 145
 146         val = pwm_readl(pc, pwm->hwpwm);
 147         val |= PWM_ENABLE;
 148         pwm_writel(pc, pwm->hwpwm, val);
 149
 150         return 0;
 151 }
 152
 153 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 154 {
 155         struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
 156         u32 val;
 157
 158         val = pwm_readl(pc, pwm->hwpwm);
 159         val &= ~PWM_ENABLE;
 160         pwm_writel(pc, pwm->hwpwm, val);
 161
 162         clk_disable_unprepare(pc->clk);
 163 }
 164
 165 static const struct pwm_ops tegra_pwm_ops = {
 166         .config = tegra_pwm_config,
 167         .enable = tegra_pwm_enable,
 168         .disable = tegra_pwm_disable,
 169         .owner = THIS_MODULE,
 170 };
 171
 172 static int tegra_pwm_probe(struct platform_device *pdev)
 173 {
 174         struct tegra_pwm_chip *pwm;
 175         struct resource *r;
 176         int ret;
 177
 178         pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 179         if (!pwm)
 180                 return -ENOMEM;
 181
 182         pwm->dev = &pdev->dev;
 183
 184         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 185         pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 186         if (IS_ERR(pwm->mmio_base))
 187                 return PTR_ERR(pwm->mmio_base);
 188
 189         platform_set_drvdata(pdev, pwm);
 190
 191         pwm->clk = devm_clk_get(&pdev->dev, NULL);
 192         if (IS_ERR(pwm->clk))
 193                 return PTR_ERR(pwm->clk);
 194
 195         pwm->chip.dev = &pdev->dev;
 196         pwm->chip.ops = &tegra_pwm_ops;
 197         pwm->chip.base = -1;
 198         pwm->chip.npwm = NUM_PWM;
 199
 200         ret = pwmchip_add(&pwm->chip);
 201         if (ret < 0) {
 202                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 203                 return ret;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int tegra_pwm_remove(struct platform_device *pdev)
 210 {
 211         struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
 212         int i;
 213
 214         if (WARN_ON(!pc))
 215                 return -ENODEV;
 216
 217         for (i = 0; i < NUM_PWM; i++) {
 218                 struct pwm_device *pwm = &pc->chip.pwms[i];
 219
 220                 if (!pwm_is_enabled(pwm))
 221                         if (clk_prepare_enable(pc->clk) < 0)
 222                                 continue;
 223
 224                 pwm_writel(pc, i, 0);
 225
 226                 clk_disable_unprepare(pc->clk);
 227         }
 228
 229         return pwmchip_remove(&pc->chip);
 230 }
 231
 232 static const struct of_device_id tegra_pwm_of_match[] = {
 233         { .compatible = "nvidia,tegra20-pwm" },
 234         { .compatible = "nvidia,tegra30-pwm" },
 235         { }
 236 };
 237
 238 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
 239
 240 static struct platform_driver tegra_pwm_driver = {
 241         .driver = {
 242                 .name = "tegra-pwm",
 243                 .of_match_table = tegra_pwm_of_match,
 244         },
 245         .probe = tegra_pwm_probe,
 246         .remove = tegra_pwm_remove,
 247 };
 248
 249 module_platform_driver(tegra_pwm_driver);
 250
 251 MODULE_LICENSE("GPL");
 252 MODULE_AUTHOR("NVIDIA Corporation");
 253 MODULE_ALIAS("platform:tegra-pwm");