?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / drivers / vfio / pci / vfio_pci_config.c
blobc55c632a3b249f652d9fb2640e603ec326f7971f
1 /*
2 * VFIO PCI config space virtualization
3 *
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
14 */
15
16 /*
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
24 */
25
26 #include <linux/fs.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
31
32 #include "vfio_pci_private.h"
33
34 #define PCI_CFG_SPACE_SIZE 256
35
36 /* Useful "pseudo" capabilities */
37 #define PCI_CAP_ID_BASIC 0
38 #define PCI_CAP_ID_INVALID 0xFF
39
40 #define is_bar(offset) \
41 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
42 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
43
44 /*
45 * Lengths of PCI Config Capabilities
46 * 0: Removed from the user visible capability list
47 * FF: Variable length
48 */
49 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
50 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
51 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
52 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
53 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
54 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
55 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
56 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
57 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
58 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
59 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
60 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
61 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
62 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
63 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
64 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
65 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
66 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
67 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
68 [PCI_CAP_ID_SATA] = 0xFF,
69 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
70 };
71
72 /*
73 * Lengths of PCIe/PCI-X Extended Config Capabilities
74 * 0: Removed or masked from the user visible capabilty list
75 * FF: Variable length
76 */
77 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
78 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
79 [PCI_EXT_CAP_ID_VC] = 0xFF,
80 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
81 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
82 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
85 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
86 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
87 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
88 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
89 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
90 [PCI_EXT_CAP_ID_ACS] = 0xFF,
91 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
92 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
93 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
94 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
95 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
96 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
97 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
99 [PCI_EXT_CAP_ID_DPA] = 0xFF,
100 [PCI_EXT_CAP_ID_TPH] = 0xFF,
101 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
102 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
104 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
105 };
106
107 /*
108 * Read/Write Permission Bits - one bit for each bit in capability
109 * Any field can be read if it exists, but what is read depends on
110 * whether the field is 'virtualized', or just pass thru to the
111 * hardware. Any virtualized field is also virtualized for writes.
112 * Writes are only permitted if they have a 1 bit here.
113 */
114 struct perm_bits {
115 u8 *virt; /* read/write virtual data, not hw */
116 u8 *write; /* writeable bits */
117 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
118 struct perm_bits *perm, int offset, __le32 *val);
119 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
120 struct perm_bits *perm, int offset, __le32 val);
121 };
122
123 #define NO_VIRT 0
124 #define ALL_VIRT 0xFFFFFFFFU
125 #define NO_WRITE 0
126 #define ALL_WRITE 0xFFFFFFFFU
127
128 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
129 __le32 *val, int count)
130 {
131 int ret = -EINVAL;
132 u32 tmp_val = 0;
133
134 switch (count) {
135 case 1:
136 {
137 u8 tmp;
138 ret = pci_user_read_config_byte(pdev, offset, &tmp);
139 tmp_val = tmp;
140 break;
141 }
142 case 2:
143 {
144 u16 tmp;
145 ret = pci_user_read_config_word(pdev, offset, &tmp);
146 tmp_val = tmp;
147 break;
148 }
149 case 4:
150 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
151 break;
152 }
153
154 *val = cpu_to_le32(tmp_val);
155
156 return pcibios_err_to_errno(ret);
157 }
158
159 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
160 __le32 val, int count)
161 {
162 int ret = -EINVAL;
163 u32 tmp_val = le32_to_cpu(val);
164
165 switch (count) {
166 case 1:
167 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
168 break;
169 case 2:
170 ret = pci_user_write_config_word(pdev, offset, tmp_val);
171 break;
172 case 4:
173 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
174 break;
175 }
176
177 return pcibios_err_to_errno(ret);
178 }
179
180 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
181 int count, struct perm_bits *perm,
182 int offset, __le32 *val)
183 {
184 __le32 virt = 0;
185
186 memcpy(val, vdev->vconfig + pos, count);
187
188 memcpy(&virt, perm->virt + offset, count);
189
190 /* Any non-virtualized bits? */
191 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
192 struct pci_dev *pdev = vdev->pdev;
193 __le32 phys_val = 0;
194 int ret;
195
196 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
197 if (ret)
198 return ret;
199
200 *val = (phys_val & ~virt) | (*val & virt);
201 }
202
203 return count;
204 }
205
206 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
207 int count, struct perm_bits *perm,
208 int offset, __le32 val)
209 {
210 __le32 virt = 0, write = 0;
211
212 memcpy(&write, perm->write + offset, count);
213
214 if (!write)
215 return count; /* drop, no writable bits */
216
217 memcpy(&virt, perm->virt + offset, count);
218
219 /* Virtualized and writable bits go to vconfig */
220 if (write & virt) {
221 __le32 virt_val = 0;
222
223 memcpy(&virt_val, vdev->vconfig + pos, count);
224
225 virt_val &= ~(write & virt);
226 virt_val |= (val & (write & virt));
227
228 memcpy(vdev->vconfig + pos, &virt_val, count);
229 }
230
231 /* Non-virtualzed and writable bits go to hardware */
232 if (write & ~virt) {
233 struct pci_dev *pdev = vdev->pdev;
234 __le32 phys_val = 0;
235 int ret;
236
237 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
238 if (ret)
239 return ret;
240
241 phys_val &= ~(write & ~virt);
242 phys_val |= (val & (write & ~virt));
243
244 ret = vfio_user_config_write(pdev, pos, phys_val, count);
245 if (ret)
246 return ret;
247 }
248
249 return count;
250 }
251
252 /* Allow direct read from hardware, except for capability next pointer */
253 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
254 int count, struct perm_bits *perm,
255 int offset, __le32 *val)
256 {
257 int ret;
258
259 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
260 if (ret)
261 return pcibios_err_to_errno(ret);
262
263 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
264 if (offset < 4)
265 memcpy(val, vdev->vconfig + pos, count);
266 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
267 if (offset == PCI_CAP_LIST_ID && count > 1)
268 memcpy(val, vdev->vconfig + pos,
269 min(PCI_CAP_FLAGS, count));
270 else if (offset == PCI_CAP_LIST_NEXT)
271 memcpy(val, vdev->vconfig + pos, 1);
272 }
273
274 return count;
275 }
276
277 /* Raw access skips any kind of virtualization */
278 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
279 int count, struct perm_bits *perm,
280 int offset, __le32 val)
281 {
282 int ret;
283
284 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
285 if (ret)
286 return ret;
287
288 return count;
289 }
290
291 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
292 int count, struct perm_bits *perm,
293 int offset, __le32 *val)
294 {
295 int ret;
296
297 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
298 if (ret)
299 return pcibios_err_to_errno(ret);
300
301 return count;
302 }
303
304 /* Default capability regions to read-only, no-virtualization */
305 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
306 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
307 };
308 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
309 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
310 };
311 /*
312 * Default unassigned regions to raw read-write access. Some devices
313 * require this to function as they hide registers between the gaps in
314 * config space (be2net). Like MMIO and I/O port registers, we have
315 * to trust the hardware isolation.
316 */
317 static struct perm_bits unassigned_perms = {
318 .readfn = vfio_raw_config_read,
319 .writefn = vfio_raw_config_write
320 };
321
322 static void free_perm_bits(struct perm_bits *perm)
323 {
324 kfree(perm->virt);
325 kfree(perm->write);
326 perm->virt = NULL;
327 perm->write = NULL;
328 }
329
330 static int alloc_perm_bits(struct perm_bits *perm, int size)
331 {
332 /*
333 * Round up all permission bits to the next dword, this lets us
334 * ignore whether a read/write exceeds the defined capability
335 * structure. We can do this because:
336 * - Standard config space is already dword aligned
337 * - Capabilities are all dword alinged (bits 0:1 of next reserved)
338 * - Express capabilities defined as dword aligned
339 */
340 size = round_up(size, 4);
341
342 /*
343 * Zero state is
344 * - All Readable, None Writeable, None Virtualized
345 */
346 perm->virt = kzalloc(size, GFP_KERNEL);
347 perm->write = kzalloc(size, GFP_KERNEL);
348 if (!perm->virt || !perm->write) {
349 free_perm_bits(perm);
350 return -ENOMEM;
351 }
352
353 perm->readfn = vfio_default_config_read;
354 perm->writefn = vfio_default_config_write;
355
356 return 0;
357 }
358
359 /*
360 * Helper functions for filling in permission tables
361 */
362 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
363 {
364 p->virt[off] = virt;
365 p->write[off] = write;
366 }
367
368 /* Handle endian-ness - pci and tables are little-endian */
369 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
370 {
371 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
372 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
373 }
374
375 /* Handle endian-ness - pci and tables are little-endian */
376 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
377 {
378 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
379 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
380 }
381
382 /*
383 * Restore the *real* BARs after we detect a FLR or backdoor reset.
384 * (backdoor = some device specific technique that we didn't catch)
385 */
386 static void vfio_bar_restore(struct vfio_pci_device *vdev)
387 {
388 struct pci_dev *pdev = vdev->pdev;
389 u32 *rbar = vdev->rbar;
390 int i;
391
392 if (pdev->is_virtfn)
393 return;
394
395 pr_info("%s: %s reset recovery - restoring bars\n",
396 __func__, dev_name(&pdev->dev));
397
398 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
399 pci_user_write_config_dword(pdev, i, *rbar);
400
401 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
402 }
403
404 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
405 {
406 unsigned long flags = pci_resource_flags(pdev, bar);
407 u32 val;
408
409 if (flags & IORESOURCE_IO)
410 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
411
412 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
413
414 if (flags & IORESOURCE_PREFETCH)
415 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
416
417 if (flags & IORESOURCE_MEM_64)
418 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
419
420 return cpu_to_le32(val);
421 }
422
423 /*
424 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
425 * to reflect the hardware capabilities. This implements BAR sizing.
426 */
427 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
428 {
429 struct pci_dev *pdev = vdev->pdev;
430 int i;
431 __le32 *bar;
432 u64 mask;
433
434 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
435
436 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
437 if (!pci_resource_start(pdev, i)) {
438 *bar = 0; /* Unmapped by host = unimplemented to user */
439 continue;
440 }
441
442 mask = ~(pci_resource_len(pdev, i) - 1);
443
444 *bar &= cpu_to_le32((u32)mask);
445 *bar |= vfio_generate_bar_flags(pdev, i);
446
447 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
448 bar++;
449 *bar &= cpu_to_le32((u32)(mask >> 32));
450 i++;
451 }
452 }
453
454 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
455
456 /*
457 * NB. we expose the actual BAR size here, regardless of whether
458 * we can read it. When we report the REGION_INFO for the ROM
459 * we report what PCI tells us is the actual ROM size.
460 */
461 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
462 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
463 mask |= PCI_ROM_ADDRESS_ENABLE;
464 *bar &= cpu_to_le32((u32)mask);
465 } else
466 *bar = 0;
467
468 vdev->bardirty = false;
469 }
470
471 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
472 int count, struct perm_bits *perm,
473 int offset, __le32 *val)
474 {
475 if (is_bar(offset)) /* pos == offset for basic config */
476 vfio_bar_fixup(vdev);
477
478 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
479
480 /* Mask in virtual memory enable for SR-IOV devices */
481 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
482 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
483 u32 tmp_val = le32_to_cpu(*val);
484
485 tmp_val |= cmd & PCI_COMMAND_MEMORY;
486 *val = cpu_to_le32(tmp_val);
487 }
488
489 return count;
490 }
491
492 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
493 int count, struct perm_bits *perm,
494 int offset, __le32 val)
495 {
496 struct pci_dev *pdev = vdev->pdev;
497 __le16 *virt_cmd;
498 u16 new_cmd = 0;
499 int ret;
500
501 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
502
503 if (offset == PCI_COMMAND) {
504 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
505 u16 phys_cmd;
506
507 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
508 if (ret)
509 return ret;
510
511 new_cmd = le32_to_cpu(val);
512
513 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
514 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
515 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
516
517 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
518 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
519 new_io = !!(new_cmd & PCI_COMMAND_IO);
520
521 /*
522 * If the user is writing mem/io enable (new_mem/io) and we
523 * think it's already enabled (virt_mem/io), but the hardware
524 * shows it disabled (phys_mem/io, then the device has
525 * undergone some kind of backdoor reset and needs to be
526 * restored before we allow it to enable the bars.
527 * SR-IOV devices will trigger this, but we catch them later
528 */
529 if ((new_mem && virt_mem && !phys_mem) ||
530 (new_io && virt_io && !phys_io))
531 vfio_bar_restore(vdev);
532 }
533
534 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
535 if (count < 0)
536 return count;
537
538 /*
539 * Save current memory/io enable bits in vconfig to allow for
540 * the test above next time.
541 */
542 if (offset == PCI_COMMAND) {
543 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
544
545 *virt_cmd &= cpu_to_le16(~mask);
546 *virt_cmd |= cpu_to_le16(new_cmd & mask);
547 }
548
549 /* Emulate INTx disable */
550 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
551 bool virt_intx_disable;
552
553 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
554 PCI_COMMAND_INTX_DISABLE);
555
556 if (virt_intx_disable && !vdev->virq_disabled) {
557 vdev->virq_disabled = true;
558 vfio_pci_intx_mask(vdev);
559 } else if (!virt_intx_disable && vdev->virq_disabled) {
560 vdev->virq_disabled = false;
561 vfio_pci_intx_unmask(vdev);
562 }
563 }
564
565 if (is_bar(offset))
566 vdev->bardirty = true;
567
568 return count;
569 }
570
571 /* Permissions for the Basic PCI Header */
572 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
573 {
574 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
575 return -ENOMEM;
576
577 perm->readfn = vfio_basic_config_read;
578 perm->writefn = vfio_basic_config_write;
579
580 /* Virtualized for SR-IOV functions, which just have FFFF */
581 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
582 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
583
584 /*
585 * Virtualize INTx disable, we use it internally for interrupt
586 * control and can emulate it for non-PCI 2.3 devices.
587 */
588 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
589
590 /* Virtualize capability list, we might want to skip/disable */
591 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
592
593 /* No harm to write */
594 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
595 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
596 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
597
598 /* Virtualize all bars, can't touch the real ones */
599 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
600 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
601 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
602 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
603 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
604 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
605 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
606
607 /* Allow us to adjust capability chain */
608 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
609
610 /* Sometimes used by sw, just virtualize */
611 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
612
613 /* Virtualize interrupt pin to allow hiding INTx */
614 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
615
616 return 0;
617 }
618
619 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
620 int count, struct perm_bits *perm,
621 int offset, __le32 val)
622 {
623 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
624 if (count < 0)
625 return count;
626
627 if (offset == PCI_PM_CTRL) {
628 pci_power_t state;
629
630 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
631 case 0:
632 state = PCI_D0;
633 break;
634 case 1:
635 state = PCI_D1;
636 break;
637 case 2:
638 state = PCI_D2;
639 break;
640 case 3:
641 state = PCI_D3hot;
642 break;
643 }
644
645 pci_set_power_state(vdev->pdev, state);
646 }
647
648 return count;
649 }
650
651 /* Permissions for the Power Management capability */
652 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
653 {
654 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
655 return -ENOMEM;
656
657 perm->writefn = vfio_pm_config_write;
658
659 /*
660 * We always virtualize the next field so we can remove
661 * capabilities from the chain if we want to.
662 */
663 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
664
665 /*
666 * Power management is defined *per function*, so we can let
667 * the user change power state, but we trap and initiate the
668 * change ourselves, so the state bits are read-only.
669 */
670 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
671 return 0;
672 }
673
674 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
675 int count, struct perm_bits *perm,
676 int offset, __le32 val)
677 {
678 struct pci_dev *pdev = vdev->pdev;
679 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
680 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
681 u16 addr;
682 u32 data;
683
684 /*
685 * Write through to emulation. If the write includes the upper byte
686 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
687 * have work to do.
688 */
689 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
690 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
691 offset + count <= PCI_VPD_ADDR + 1)
692 return count;
693
694 addr = le16_to_cpu(*paddr);
695
696 if (addr & PCI_VPD_ADDR_F) {
697 data = le32_to_cpu(*pdata);
698 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
699 return count;
700 } else {
701 if (pci_read_vpd(pdev, addr, 4, &data) != 4)
702 return count;
703 *pdata = cpu_to_le32(data);
704 }
705
706 /*
707 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
708 * signal completion. If an error occurs above, we assume that not
709 * toggling this bit will induce a driver timeout.
710 */
711 addr ^= PCI_VPD_ADDR_F;
712 *paddr = cpu_to_le16(addr);
713
714 return count;
715 }
716
717 /* Permissions for Vital Product Data capability */
718 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
719 {
720 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
721 return -ENOMEM;
722
723 perm->writefn = vfio_vpd_config_write;
724
725 /*
726 * We always virtualize the next field so we can remove
727 * capabilities from the chain if we want to.
728 */
729 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
730
731 /*
732 * Both the address and data registers are virtualized to
733 * enable access through the pci_vpd_read/write functions
734 */
735 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
736 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
737
738 return 0;
739 }
740
741 /* Permissions for PCI-X capability */
742 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
743 {
744 /* Alloc 24, but only 8 are used in v0 */
745 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
746 return -ENOMEM;
747
748 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
749
750 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
751 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
752 return 0;
753 }
754
755 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
756 int count, struct perm_bits *perm,
757 int offset, __le32 val)
758 {
759 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
760 offset + PCI_EXP_DEVCTL);
761 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
762
763 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
764 if (count < 0)
765 return count;
766
767 /*
768 * The FLR bit is virtualized, if set and the device supports PCIe
769 * FLR, issue a reset_function. Regardless, clear the bit, the spec
770 * requires it to be always read as zero. NB, reset_function might
771 * not use a PCIe FLR, we don't have that level of granularity.
772 */
773 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
774 u32 cap;
775 int ret;
776
777 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
778
779 ret = pci_user_read_config_dword(vdev->pdev,
780 pos - offset + PCI_EXP_DEVCAP,
781 &cap);
782
783 if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
784 pci_try_reset_function(vdev->pdev);
785 }
786
787 /*
788 * MPS is virtualized to the user, writes do not change the physical
789 * register since determining a proper MPS value requires a system wide
790 * device view. The MRRS is largely independent of MPS, but since the
791 * user does not have that system-wide view, they might set a safe, but
792 * inefficiently low value. Here we allow writes through to hardware,
793 * but we set the floor to the physical device MPS setting, so that
794 * we can at least use full TLPs, as defined by the MPS value.
795 *
796 * NB, if any devices actually depend on an artificially low MRRS
797 * setting, this will need to be revisited, perhaps with a quirk
798 * though pcie_set_readrq().
799 */
800 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
801 readrq = 128 <<
802 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
803 readrq = max(readrq, pcie_get_mps(vdev->pdev));
804
805 pcie_set_readrq(vdev->pdev, readrq);
806 }
807
808 return count;
809 }
810
811 /* Permissions for PCI Express capability */
812 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
813 {
814 /* Alloc larger of two possible sizes */
815 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
816 return -ENOMEM;
817
818 perm->writefn = vfio_exp_config_write;
819
820 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
821
822 /*
823 * Allow writes to device control fields, except devctl_phantom,
824 * which could confuse IOMMU, MPS, which can break communication
825 * with other physical devices, and the ARI bit in devctl2, which
826 * is set at probe time. FLR and MRRS get virtualized via our
827 * writefn.
828 */
829 p_setw(perm, PCI_EXP_DEVCTL,
830 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
831 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
832 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
833 return 0;
834 }
835
836 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
837 int count, struct perm_bits *perm,
838 int offset, __le32 val)
839 {
840 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
841
842 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
843 if (count < 0)
844 return count;
845
846 /*
847 * The FLR bit is virtualized, if set and the device supports AF
848 * FLR, issue a reset_function. Regardless, clear the bit, the spec
849 * requires it to be always read as zero. NB, reset_function might
850 * not use an AF FLR, we don't have that level of granularity.
851 */
852 if (*ctrl & PCI_AF_CTRL_FLR) {
853 u8 cap;
854 int ret;
855
856 *ctrl &= ~PCI_AF_CTRL_FLR;
857
858 ret = pci_user_read_config_byte(vdev->pdev,
859 pos - offset + PCI_AF_CAP,
860 &cap);
861
862 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
863 pci_try_reset_function(vdev->pdev);
864 }
865
866 return count;
867 }
868
869 /* Permissions for Advanced Function capability */
870 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
871 {
872 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
873 return -ENOMEM;
874
875 perm->writefn = vfio_af_config_write;
876
877 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
878 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
879 return 0;
880 }
881
882 /* Permissions for Advanced Error Reporting extended capability */
883 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
884 {
885 u32 mask;
886
887 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
888 return -ENOMEM;
889
890 /*
891 * Virtualize the first dword of all express capabilities
892 * because it includes the next pointer. This lets us later
893 * remove capabilities from the chain if we need to.
894 */
895 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
896
897 /* Writable bits mask */
898 mask = PCI_ERR_UNC_UND | /* Undefined */
899 PCI_ERR_UNC_DLP | /* Data Link Protocol */
900 PCI_ERR_UNC_SURPDN | /* Surprise Down */
901 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
902 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
903 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
904 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
905 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
906 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
907 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
908 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
909 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
910 PCI_ERR_UNC_ACSV | /* ACS Violation */
911 PCI_ERR_UNC_INTN | /* internal error */
912 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
913 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
914 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
915 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
916 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
917 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
918
919 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
920 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
921 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
922 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
923 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
924 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
925 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
926 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
927 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
928 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
929
930 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
931 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
932 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
933 return 0;
934 }
935
936 /* Permissions for Power Budgeting extended capability */
937 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
938 {
939 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
940 return -ENOMEM;
941
942 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
943
944 /* Writing the data selector is OK, the info is still read-only */
945 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
946 return 0;
947 }
948
949 /*
950 * Initialize the shared permission tables
951 */
952 void vfio_pci_uninit_perm_bits(void)
953 {
954 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
955
956 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
957 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
958 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
959 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
960 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
961
962 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
963 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
964 }
965
966 int __init vfio_pci_init_perm_bits(void)
967 {
968 int ret;
969
970 /* Basic config space */
971 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
972
973 /* Capabilities */
974 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
975 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
976 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
977 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
978 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
979 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
980
981 /* Extended capabilities */
982 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
983 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
984 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
985
986 if (ret)
987 vfio_pci_uninit_perm_bits();
988
989 return ret;
990 }
991
992 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
993 {
994 u8 cap;
995 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
996 PCI_STD_HEADER_SIZEOF;
997 cap = vdev->pci_config_map[pos];
998
999 if (cap == PCI_CAP_ID_BASIC)
1000 return 0;
1001
1002 /* XXX Can we have to abutting capabilities of the same type? */
1003 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1004 pos--;
1005
1006 return pos;
1007 }
1008
1009 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1010 int count, struct perm_bits *perm,
1011 int offset, __le32 *val)
1012 {
1013 /* Update max available queue size from msi_qmax */
1014 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1015 __le16 *flags;
1016 int start;
1017
1018 start = vfio_find_cap_start(vdev, pos);
1019
1020 flags = (__le16 *)&vdev->vconfig[start];
1021
1022 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1023 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1024 }
1025
1026 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1027 }
1028
1029 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1030 int count, struct perm_bits *perm,
1031 int offset, __le32 val)
1032 {
1033 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1034 if (count < 0)
1035 return count;
1036
1037 /* Fixup and write configured queue size and enable to hardware */
1038 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1039 __le16 *pflags;
1040 u16 flags;
1041 int start, ret;
1042
1043 start = vfio_find_cap_start(vdev, pos);
1044
1045 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1046
1047 flags = le16_to_cpu(*pflags);
1048
1049 /* MSI is enabled via ioctl */
1050 if (!is_msi(vdev))
1051 flags &= ~PCI_MSI_FLAGS_ENABLE;
1052
1053 /* Check queue size */
1054 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1055 flags &= ~PCI_MSI_FLAGS_QSIZE;
1056 flags |= vdev->msi_qmax << 4;
1057 }
1058
1059 /* Write back to virt and to hardware */
1060 *pflags = cpu_to_le16(flags);
1061 ret = pci_user_write_config_word(vdev->pdev,
1062 start + PCI_MSI_FLAGS,
1063 flags);
1064 if (ret)
1065 return pcibios_err_to_errno(ret);
1066 }
1067
1068 return count;
1069 }
1070
1071 /*
1072 * MSI determination is per-device, so this routine gets used beyond
1073 * initialization time. Don't add __init
1074 */
1075 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1076 {
1077 if (alloc_perm_bits(perm, len))
1078 return -ENOMEM;
1079
1080 perm->readfn = vfio_msi_config_read;
1081 perm->writefn = vfio_msi_config_write;
1082
1083 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1084
1085 /*
1086 * The upper byte of the control register is reserved,
1087 * just setup the lower byte.
1088 */
1089 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1090 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1091 if (flags & PCI_MSI_FLAGS_64BIT) {
1092 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1093 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1094 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1095 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1096 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1097 }
1098 } else {
1099 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1100 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1101 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1102 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1103 }
1104 }
1105 return 0;
1106 }
1107
1108 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1109 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1110 {
1111 struct pci_dev *pdev = vdev->pdev;
1112 int len, ret;
1113 u16 flags;
1114
1115 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1116 if (ret)
1117 return pcibios_err_to_errno(ret);
1118
1119 len = 10; /* Minimum size */
1120 if (flags & PCI_MSI_FLAGS_64BIT)
1121 len += 4;
1122 if (flags & PCI_MSI_FLAGS_MASKBIT)
1123 len += 10;
1124
1125 if (vdev->msi_perm)
1126 return len;
1127
1128 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1129 if (!vdev->msi_perm)
1130 return -ENOMEM;
1131
1132 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1133 if (ret)
1134 return ret;
1135
1136 return len;
1137 }
1138
1139 /* Determine extended capability length for VC (2 & 9) and MFVC */
1140 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1141 {
1142 struct pci_dev *pdev = vdev->pdev;
1143 u32 tmp;
1144 int ret, evcc, phases, vc_arb;
1145 int len = PCI_CAP_VC_BASE_SIZEOF;
1146
1147 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1148 if (ret)
1149 return pcibios_err_to_errno(ret);
1150
1151 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1152 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1153 if (ret)
1154 return pcibios_err_to_errno(ret);
1155
1156 if (tmp & PCI_VC_CAP2_128_PHASE)
1157 phases = 128;
1158 else if (tmp & PCI_VC_CAP2_64_PHASE)
1159 phases = 64;
1160 else if (tmp & PCI_VC_CAP2_32_PHASE)
1161 phases = 32;
1162 else
1163 phases = 0;
1164
1165 vc_arb = phases * 4;
1166
1167 /*
1168 * Port arbitration tables are root & switch only;
1169 * function arbitration tables are function 0 only.
1170 * In either case, we'll never let user write them so
1171 * we don't care how big they are
1172 */
1173 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1174 if (vc_arb) {
1175 len = round_up(len, 16);
1176 len += vc_arb / 8;
1177 }
1178 return len;
1179 }
1180
1181 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1182 {
1183 struct pci_dev *pdev = vdev->pdev;
1184 u32 dword;
1185 u16 word;
1186 u8 byte;
1187 int ret;
1188
1189 switch (cap) {
1190 case PCI_CAP_ID_MSI:
1191 return vfio_msi_cap_len(vdev, pos);
1192 case PCI_CAP_ID_PCIX:
1193 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1194 if (ret)
1195 return pcibios_err_to_errno(ret);
1196
1197 if (PCI_X_CMD_VERSION(word)) {
1198 /* Test for extended capabilities */
1199 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1200 vdev->extended_caps = (dword != 0);
1201 return PCI_CAP_PCIX_SIZEOF_V2;
1202 } else
1203 return PCI_CAP_PCIX_SIZEOF_V0;
1204 case PCI_CAP_ID_VNDR:
1205 /* length follows next field */
1206 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1207 if (ret)
1208 return pcibios_err_to_errno(ret);
1209
1210 return byte;
1211 case PCI_CAP_ID_EXP:
1212 /* Test for extended capabilities */
1213 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1214 vdev->extended_caps = (dword != 0);
1215
1216 /* length based on version */
1217 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
1218 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1219 else
1220 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1221 case PCI_CAP_ID_HT:
1222 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1223 if (ret)
1224 return pcibios_err_to_errno(ret);
1225
1226 return (byte & HT_3BIT_CAP_MASK) ?
1227 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1228 case PCI_CAP_ID_SATA:
1229 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1230 if (ret)
1231 return pcibios_err_to_errno(ret);
1232
1233 byte &= PCI_SATA_REGS_MASK;
1234 if (byte == PCI_SATA_REGS_INLINE)
1235 return PCI_SATA_SIZEOF_LONG;
1236 else
1237 return PCI_SATA_SIZEOF_SHORT;
1238 default:
1239 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1240 dev_name(&pdev->dev), __func__, cap, pos);
1241 }
1242
1243 return 0;
1244 }
1245
1246 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1247 {
1248 struct pci_dev *pdev = vdev->pdev;
1249 u8 byte;
1250 u32 dword;
1251 int ret;
1252
1253 switch (ecap) {
1254 case PCI_EXT_CAP_ID_VNDR:
1255 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1256 if (ret)
1257 return pcibios_err_to_errno(ret);
1258
1259 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1260 case PCI_EXT_CAP_ID_VC:
1261 case PCI_EXT_CAP_ID_VC9:
1262 case PCI_EXT_CAP_ID_MFVC:
1263 return vfio_vc_cap_len(vdev, epos);
1264 case PCI_EXT_CAP_ID_ACS:
1265 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1266 if (ret)
1267 return pcibios_err_to_errno(ret);
1268
1269 if (byte & PCI_ACS_EC) {
1270 int bits;
1271
1272 ret = pci_read_config_byte(pdev,
1273 epos + PCI_ACS_EGRESS_BITS,
1274 &byte);
1275 if (ret)
1276 return pcibios_err_to_errno(ret);
1277
1278 bits = byte ? round_up(byte, 32) : 256;
1279 return 8 + (bits / 8);
1280 }
1281 return 8;
1282
1283 case PCI_EXT_CAP_ID_REBAR:
1284 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1285 if (ret)
1286 return pcibios_err_to_errno(ret);
1287
1288 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1289 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1290
1291 return 4 + (byte * 8);
1292 case PCI_EXT_CAP_ID_DPA:
1293 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1294 if (ret)
1295 return pcibios_err_to_errno(ret);
1296
1297 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1298 return PCI_DPA_BASE_SIZEOF + byte + 1;
1299 case PCI_EXT_CAP_ID_TPH:
1300 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1301 if (ret)
1302 return pcibios_err_to_errno(ret);
1303
1304 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1305 int sts;
1306
1307 sts = dword & PCI_TPH_CAP_ST_MASK;
1308 sts >>= PCI_TPH_CAP_ST_SHIFT;
1309 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1310 }
1311 return PCI_TPH_BASE_SIZEOF;
1312 default:
1313 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1314 dev_name(&pdev->dev), __func__, ecap, epos);
1315 }
1316
1317 return 0;
1318 }
1319
1320 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1321 int offset, int size)
1322 {
1323 struct pci_dev *pdev = vdev->pdev;
1324 int ret = 0;
1325
1326 /*
1327 * We try to read physical config space in the largest chunks
1328 * we can, assuming that all of the fields support dword access.
1329 * pci_save_state() makes this same assumption and seems to do ok.
1330 */
1331 while (size) {
1332 int filled;
1333
1334 if (size >= 4 && !(offset % 4)) {
1335 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1336 u32 dword;
1337
1338 ret = pci_read_config_dword(pdev, offset, &dword);
1339 if (ret)
1340 return ret;
1341 *dwordp = cpu_to_le32(dword);
1342 filled = 4;
1343 } else if (size >= 2 && !(offset % 2)) {
1344 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1345 u16 word;
1346
1347 ret = pci_read_config_word(pdev, offset, &word);
1348 if (ret)
1349 return ret;
1350 *wordp = cpu_to_le16(word);
1351 filled = 2;
1352 } else {
1353 u8 *byte = &vdev->vconfig[offset];
1354 ret = pci_read_config_byte(pdev, offset, byte);
1355 if (ret)
1356 return ret;
1357 filled = 1;
1358 }
1359
1360 offset += filled;
1361 size -= filled;
1362 }
1363
1364 return ret;
1365 }
1366
1367 static int vfio_cap_init(struct vfio_pci_device *vdev)
1368 {
1369 struct pci_dev *pdev = vdev->pdev;
1370 u8 *map = vdev->pci_config_map;
1371 u16 status;
1372 u8 pos, *prev, cap;
1373 int loops, ret, caps = 0;
1374
1375 /* Any capabilities? */
1376 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1377 if (ret)
1378 return ret;
1379
1380 if (!(status & PCI_STATUS_CAP_LIST))
1381 return 0; /* Done */
1382
1383 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1384 if (ret)
1385 return ret;
1386
1387 /* Mark the previous position in case we want to skip a capability */
1388 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1389
1390 /* We can bound our loop, capabilities are dword aligned */
1391 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1392 while (pos && loops--) {
1393 u8 next;
1394 int i, len = 0;
1395
1396 ret = pci_read_config_byte(pdev, pos, &cap);
1397 if (ret)
1398 return ret;
1399
1400 ret = pci_read_config_byte(pdev,
1401 pos + PCI_CAP_LIST_NEXT, &next);
1402 if (ret)
1403 return ret;
1404
1405 if (cap <= PCI_CAP_ID_MAX) {
1406 len = pci_cap_length[cap];
1407 if (len == 0xFF) { /* Variable length */
1408 len = vfio_cap_len(vdev, cap, pos);
1409 if (len < 0)
1410 return len;
1411 }
1412 }
1413
1414 if (!len) {
1415 pr_info("%s: %s hiding cap 0x%x\n",
1416 __func__, dev_name(&pdev->dev), cap);
1417 *prev = next;
1418 pos = next;
1419 continue;
1420 }
1421
1422 /* Sanity check, do we overlap other capabilities? */
1423 for (i = 0; i < len; i++) {
1424 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1425 continue;
1426
1427 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1428 __func__, dev_name(&pdev->dev),
1429 pos + i, map[pos + i], cap);
1430 }
1431
1432 memset(map + pos, cap, len);
1433 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1434 if (ret)
1435 return ret;
1436
1437 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1438 pos = next;
1439 caps++;
1440 }
1441
1442 /* If we didn't fill any capabilities, clear the status flag */
1443 if (!caps) {
1444 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1445 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1446 }
1447
1448 return 0;
1449 }
1450
1451 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1452 {
1453 struct pci_dev *pdev = vdev->pdev;
1454 u8 *map = vdev->pci_config_map;
1455 u16 epos;
1456 __le32 *prev = NULL;
1457 int loops, ret, ecaps = 0;
1458
1459 if (!vdev->extended_caps)
1460 return 0;
1461
1462 epos = PCI_CFG_SPACE_SIZE;
1463
1464 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1465
1466 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1467 u32 header;
1468 u16 ecap;
1469 int i, len = 0;
1470 bool hidden = false;
1471
1472 ret = pci_read_config_dword(pdev, epos, &header);
1473 if (ret)
1474 return ret;
1475
1476 ecap = PCI_EXT_CAP_ID(header);
1477
1478 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1479 len = pci_ext_cap_length[ecap];
1480 if (len == 0xFF) {
1481 len = vfio_ext_cap_len(vdev, ecap, epos);
1482 if (len < 0)
1483 return ret;
1484 }
1485 }
1486
1487 if (!len) {
1488 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1489 __func__, dev_name(&pdev->dev), ecap, epos);
1490
1491 /* If not the first in the chain, we can skip over it */
1492 if (prev) {
1493 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1494 *prev &= cpu_to_le32(~(0xffcU << 20));
1495 *prev |= cpu_to_le32(val << 20);
1496 continue;
1497 }
1498
1499 /*
1500 * Otherwise, fill in a placeholder, the direct
1501 * readfn will virtualize this automatically
1502 */
1503 len = PCI_CAP_SIZEOF;
1504 hidden = true;
1505 }
1506
1507 for (i = 0; i < len; i++) {
1508 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1509 continue;
1510
1511 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1512 __func__, dev_name(&pdev->dev),
1513 epos + i, map[epos + i], ecap);
1514 }
1515
1516 /*
1517 * Even though ecap is 2 bytes, we're currently a long way
1518 * from exceeding 1 byte capabilities. If we ever make it
1519 * up to 0xFF we'll need to up this to a two-byte, byte map.
1520 */
1521 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID);
1522
1523 memset(map + epos, ecap, len);
1524 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1525 if (ret)
1526 return ret;
1527
1528 /*
1529 * If we're just using this capability to anchor the list,
1530 * hide the real ID. Only count real ecaps. XXX PCI spec
1531 * indicates to use cap id = 0, version = 0, next = 0 if
1532 * ecaps are absent, hope users check all the way to next.
1533 */
1534 if (hidden)
1535 *(__le32 *)&vdev->vconfig[epos] &=
1536 cpu_to_le32((0xffcU << 20));
1537 else
1538 ecaps++;
1539
1540 prev = (__le32 *)&vdev->vconfig[epos];
1541 epos = PCI_EXT_CAP_NEXT(header);
1542 }
1543
1544 if (!ecaps)
1545 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1546
1547 return 0;
1548 }
1549
1550 /*
1551 * For each device we allocate a pci_config_map that indicates the
1552 * capability occupying each dword and thus the struct perm_bits we
1553 * use for read and write. We also allocate a virtualized config
1554 * space which tracks reads and writes to bits that we emulate for
1555 * the user. Initial values filled from device.
1556 *
1557 * Using shared stuct perm_bits between all vfio-pci devices saves
1558 * us from allocating cfg_size buffers for virt and write for every
1559 * device. We could remove vconfig and allocate individual buffers
1560 * for each area requring emulated bits, but the array of pointers
1561 * would be comparable in size (at least for standard config space).
1562 */
1563 int vfio_config_init(struct vfio_pci_device *vdev)
1564 {
1565 struct pci_dev *pdev = vdev->pdev;
1566 u8 *map, *vconfig;
1567 int ret;
1568
1569 /*
1570 * Config space, caps and ecaps are all dword aligned, so we could
1571 * use one byte per dword to record the type. However, there are
1572 * no requiremenst on the length of a capability, so the gap between
1573 * capabilities needs byte granularity.
1574 */
1575 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1576 if (!map)
1577 return -ENOMEM;
1578
1579 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1580 if (!vconfig) {
1581 kfree(map);
1582 return -ENOMEM;
1583 }
1584
1585 vdev->pci_config_map = map;
1586 vdev->vconfig = vconfig;
1587
1588 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1589 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1590 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1591
1592 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1593 if (ret)
1594 goto out;
1595
1596 vdev->bardirty = true;
1597
1598 /*
1599 * XXX can we just pci_load_saved_state/pci_restore_state?
1600 * may need to rebuild vconfig after that
1601 */
1602
1603 /* For restore after reset */
1604 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1605 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1606 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1607 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1608 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1609 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1610 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1611
1612 if (pdev->is_virtfn) {
1613 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1614 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1615 }
1616
1617 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX))
1618 vconfig[PCI_INTERRUPT_PIN] = 0;
1619
1620 ret = vfio_cap_init(vdev);
1621 if (ret)
1622 goto out;
1623
1624 ret = vfio_ecap_init(vdev);
1625 if (ret)
1626 goto out;
1627
1628 return 0;
1629
1630 out:
1631 kfree(map);
1632 vdev->pci_config_map = NULL;
1633 kfree(vconfig);
1634 vdev->vconfig = NULL;
1635 return pcibios_err_to_errno(ret);
1636 }
1637
1638 void vfio_config_free(struct vfio_pci_device *vdev)
1639 {
1640 kfree(vdev->vconfig);
1641 vdev->vconfig = NULL;
1642 kfree(vdev->pci_config_map);
1643 vdev->pci_config_map = NULL;
1644 kfree(vdev->msi_perm);
1645 vdev->msi_perm = NULL;
1646 }
1647
1648 /*
1649 * Find the remaining number of bytes in a dword that match the given
1650 * position. Stop at either the end of the capability or the dword boundary.
1651 */
1652 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1653 loff_t pos)
1654 {
1655 u8 cap = vdev->pci_config_map[pos];
1656 size_t i;
1657
1658 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1659 /* nop */;
1660
1661 return i;
1662 }
1663
1664 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1665 size_t count, loff_t *ppos, bool iswrite)
1666 {
1667 struct pci_dev *pdev = vdev->pdev;
1668 struct perm_bits *perm;
1669 __le32 val = 0;
1670 int cap_start = 0, offset;
1671 u8 cap_id;
1672 ssize_t ret;
1673
1674 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1675 *ppos + count > pdev->cfg_size)
1676 return -EFAULT;
1677
1678 /*
1679 * Chop accesses into aligned chunks containing no more than a
1680 * single capability. Caller increments to the next chunk.
1681 */
1682 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1683 if (count >= 4 && !(*ppos % 4))
1684 count = 4;
1685 else if (count >= 2 && !(*ppos % 2))
1686 count = 2;
1687 else
1688 count = 1;
1689
1690 ret = count;
1691
1692 cap_id = vdev->pci_config_map[*ppos];
1693
1694 if (cap_id == PCI_CAP_ID_INVALID) {
1695 perm = &unassigned_perms;
1696 cap_start = *ppos;
1697 } else {
1698 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1699 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1700
1701 perm = &ecap_perms[cap_id];
1702 cap_start = vfio_find_cap_start(vdev, *ppos);
1703 } else {
1704 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1705
1706 perm = &cap_perms[cap_id];
1707
1708 if (cap_id == PCI_CAP_ID_MSI)
1709 perm = vdev->msi_perm;
1710
1711 if (cap_id > PCI_CAP_ID_BASIC)
1712 cap_start = vfio_find_cap_start(vdev, *ppos);
1713 }
1714 }
1715
1716 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1717 WARN_ON(cap_start > *ppos);
1718
1719 offset = *ppos - cap_start;
1720
1721 if (iswrite) {
1722 if (!perm->writefn)
1723 return ret;
1724
1725 if (copy_from_user(&val, buf, count))
1726 return -EFAULT;
1727
1728 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1729 } else {
1730 if (perm->readfn) {
1731 ret = perm->readfn(vdev, *ppos, count,
1732 perm, offset, &val);
1733 if (ret < 0)
1734 return ret;
1735 }
1736
1737 if (copy_to_user(buf, &val, count))
1738 return -EFAULT;
1739 }
1740
1741 return ret;
1742 }
1743
1744 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1745 size_t count, loff_t *ppos, bool iswrite)
1746 {
1747 size_t done = 0;
1748 int ret = 0;
1749 loff_t pos = *ppos;
1750
1751 pos &= VFIO_PCI_OFFSET_MASK;
1752
1753 while (count) {
1754 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1755 if (ret < 0)
1756 return ret;
1757
1758 count -= ret;
1759 done += ret;
1760 buf += ret;
1761 pos += ret;
1762 }
1763
1764 *ppos += done;
1765
1766 return done;
1767 }
Linux with added FPC-III support