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dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / sound / pci / hda / hda_intel.c
blob95a82e428f37ff451214c0f15c07dea286a9b286
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_HDA_CGCTL 0x48
94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
95 #define INTEL_SCH_HDA_DEVC 0x78
96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98 /* Define IN stream 0 FIFO size offset in VIA controller */
99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100 /* Define VIA HD Audio Device ID*/
101 #define VIA_HDAC_DEVICE_ID 0x3288
102
103 /* max number of SDs */
104 /* ICH, ATI and VIA have 4 playback and 4 capture */
105 #define ICH6_NUM_CAPTURE 4
106 #define ICH6_NUM_PLAYBACK 4
107
108 /* ULI has 6 playback and 5 capture */
109 #define ULI_NUM_CAPTURE 5
110 #define ULI_NUM_PLAYBACK 6
111
112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
113 #define ATIHDMI_NUM_CAPTURE 0
114 #define ATIHDMI_NUM_PLAYBACK 8
115
116 /* TERA has 4 playback and 3 capture */
117 #define TERA_NUM_CAPTURE 3
118 #define TERA_NUM_PLAYBACK 4
119
120
121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
124 static char *model[SNDRV_CARDS];
125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_only[SNDRV_CARDS];
129 static int jackpoll_ms[SNDRV_CARDS];
130 static bool single_cmd;
131 static int enable_msi = -1;
132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
133 static char *patch[SNDRV_CARDS];
134 #endif
135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138 #endif
139
140 module_param_array(index, int, NULL, 0444);
141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
142 module_param_array(id, charp, NULL, 0444);
143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
144 module_param_array(enable, bool, NULL, 0444);
145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146 module_param_array(model, charp, NULL, 0444);
147 MODULE_PARM_DESC(model, "Use the given board model.");
148 module_param_array(position_fix, int, NULL, 0444);
149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
151 module_param_array(bdl_pos_adj, int, NULL, 0644);
152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
153 module_param_array(probe_mask, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
155 module_param_array(probe_only, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
157 module_param_array(jackpoll_ms, int, NULL, 0444);
158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
159 module_param(single_cmd, bool, 0444);
160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
162 module_param(enable_msi, bint, 0444);
163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
165 module_param_array(patch, charp, NULL, 0444);
166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167 #endif
168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
169 module_param_array(beep_mode, bool, NULL, 0444);
170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
171 "(0=off, 1=on) (default=1).");
172 #endif
173
174 #ifdef CONFIG_PM
175 static int param_set_xint(const char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops param_ops_xint = {
177 .set = param_set_xint,
178 .get = param_get_int,
179 };
180 #define param_check_xint param_check_int
181
182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
183 module_param(power_save, xint, 0644);
184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
186
187 static bool pm_blacklist = true;
188 module_param(pm_blacklist, bool, 0644);
189 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
190
191 /* reset the HD-audio controller in power save mode.
192 * this may give more power-saving, but will take longer time to
193 * wake up.
194 */
195 static bool power_save_controller = 1;
196 module_param(power_save_controller, bool, 0644);
197 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
198 #else
199 #define power_save 0
200 #endif /* CONFIG_PM */
201
202 static int align_buffer_size = -1;
203 module_param(align_buffer_size, bint, 0644);
204 MODULE_PARM_DESC(align_buffer_size,
205 "Force buffer and period sizes to be multiple of 128 bytes.");
206
207 #ifdef CONFIG_X86
208 static int hda_snoop = -1;
209 module_param_named(snoop, hda_snoop, bint, 0444);
210 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
211 #else
212 #define hda_snoop true
213 #endif
214
215
216 MODULE_LICENSE("GPL");
217 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
218 "{Intel, ICH6M},"
219 "{Intel, ICH7},"
220 "{Intel, ESB2},"
221 "{Intel, ICH8},"
222 "{Intel, ICH9},"
223 "{Intel, ICH10},"
224 "{Intel, PCH},"
225 "{Intel, CPT},"
226 "{Intel, PPT},"
227 "{Intel, LPT},"
228 "{Intel, LPT_LP},"
229 "{Intel, WPT_LP},"
230 "{Intel, SPT},"
231 "{Intel, SPT_LP},"
232 "{Intel, HPT},"
233 "{Intel, PBG},"
234 "{Intel, SCH},"
235 "{ATI, SB450},"
236 "{ATI, SB600},"
237 "{ATI, RS600},"
238 "{ATI, RS690},"
239 "{ATI, RS780},"
240 "{ATI, R600},"
241 "{ATI, RV630},"
242 "{ATI, RV610},"
243 "{ATI, RV670},"
244 "{ATI, RV635},"
245 "{ATI, RV620},"
246 "{ATI, RV770},"
247 "{VIA, VT8251},"
248 "{VIA, VT8237A},"
249 "{SiS, SIS966},"
250 "{ULI, M5461}}");
251 MODULE_DESCRIPTION("Intel HDA driver");
252
253 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
254 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
255 #define SUPPORT_VGA_SWITCHEROO
256 #endif
257 #endif
258
259
260 /*
261 */
262
263 /* driver types */
264 enum {
265 AZX_DRIVER_ICH,
266 AZX_DRIVER_PCH,
267 AZX_DRIVER_SCH,
268 AZX_DRIVER_HDMI,
269 AZX_DRIVER_ATI,
270 AZX_DRIVER_ATIHDMI,
271 AZX_DRIVER_ATIHDMI_NS,
272 AZX_DRIVER_VIA,
273 AZX_DRIVER_SIS,
274 AZX_DRIVER_ULI,
275 AZX_DRIVER_NVIDIA,
276 AZX_DRIVER_TERA,
277 AZX_DRIVER_CTX,
278 AZX_DRIVER_CTHDA,
279 AZX_DRIVER_CMEDIA,
280 AZX_DRIVER_GENERIC,
281 AZX_NUM_DRIVERS, /* keep this as last entry */
282 };
283
284 #define azx_get_snoop_type(chip) \
285 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
286 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
287
288 /* quirks for old Intel chipsets */
289 #define AZX_DCAPS_INTEL_ICH \
290 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
291
292 /* quirks for Intel PCH */
293 #define AZX_DCAPS_INTEL_PCH_NOPM \
294 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
295 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
296
297 #define AZX_DCAPS_INTEL_PCH \
298 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
299
300 #define AZX_DCAPS_INTEL_HASWELL \
301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
304
305 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
306 #define AZX_DCAPS_INTEL_BROADWELL \
307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
309 AZX_DCAPS_SNOOP_TYPE(SCH))
310
311 #define AZX_DCAPS_INTEL_BAYTRAIL \
312 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
313
314 #define AZX_DCAPS_INTEL_BRASWELL \
315 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
316
317 #define AZX_DCAPS_INTEL_SKYLAKE \
318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
320
321 #define AZX_DCAPS_INTEL_BROXTON \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
324
325 /* quirks for ATI SB / AMD Hudson */
326 #define AZX_DCAPS_PRESET_ATI_SB \
327 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
328 AZX_DCAPS_SNOOP_TYPE(ATI))
329
330 /* quirks for ATI/AMD HDMI */
331 #define AZX_DCAPS_PRESET_ATI_HDMI \
332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
333 AZX_DCAPS_NO_MSI64)
334
335 /* quirks for ATI HDMI with snoop off */
336 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
337 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
338
339 /* quirks for Nvidia */
340 #define AZX_DCAPS_PRESET_NVIDIA \
341 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
342 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
343
344 #define AZX_DCAPS_PRESET_CTHDA \
345 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
346 AZX_DCAPS_NO_64BIT |\
347 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
348
349 /*
350 * vga_switcheroo support
351 */
352 #ifdef SUPPORT_VGA_SWITCHEROO
353 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
354 #else
355 #define use_vga_switcheroo(chip) 0
356 #endif
357
358 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
359 ((pci)->device == 0x0c0c) || \
360 ((pci)->device == 0x0d0c) || \
361 ((pci)->device == 0x160c))
362
363 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
364 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
365 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
366 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
367 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
368 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
369 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
370 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
371
372 static char *driver_short_names[] = {
373 [AZX_DRIVER_ICH] = "HDA Intel",
374 [AZX_DRIVER_PCH] = "HDA Intel PCH",
375 [AZX_DRIVER_SCH] = "HDA Intel MID",
376 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
377 [AZX_DRIVER_ATI] = "HDA ATI SB",
378 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
379 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
380 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
381 [AZX_DRIVER_SIS] = "HDA SIS966",
382 [AZX_DRIVER_ULI] = "HDA ULI M5461",
383 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
384 [AZX_DRIVER_TERA] = "HDA Teradici",
385 [AZX_DRIVER_CTX] = "HDA Creative",
386 [AZX_DRIVER_CTHDA] = "HDA Creative",
387 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
388 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
389 };
390
391 #ifdef CONFIG_X86
392 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
393 {
394 int pages;
395
396 if (azx_snoop(chip))
397 return;
398 if (!dmab || !dmab->area || !dmab->bytes)
399 return;
400
401 #ifdef CONFIG_SND_DMA_SGBUF
402 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
403 struct snd_sg_buf *sgbuf = dmab->private_data;
404 if (chip->driver_type == AZX_DRIVER_CMEDIA)
405 return; /* deal with only CORB/RIRB buffers */
406 if (on)
407 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
408 else
409 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
410 return;
411 }
412 #endif
413
414 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
415 if (on)
416 set_memory_wc((unsigned long)dmab->area, pages);
417 else
418 set_memory_wb((unsigned long)dmab->area, pages);
419 }
420
421 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
422 bool on)
423 {
424 __mark_pages_wc(chip, buf, on);
425 }
426 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
427 struct snd_pcm_substream *substream, bool on)
428 {
429 if (azx_dev->wc_marked != on) {
430 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
431 azx_dev->wc_marked = on;
432 }
433 }
434 #else
435 /* NOP for other archs */
436 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
437 bool on)
438 {
439 }
440 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
441 struct snd_pcm_substream *substream, bool on)
442 {
443 }
444 #endif
445
446 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
447
448 /*
449 * initialize the PCI registers
450 */
451 /* update bits in a PCI register byte */
452 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
453 unsigned char mask, unsigned char val)
454 {
455 unsigned char data;
456
457 pci_read_config_byte(pci, reg, &data);
458 data &= ~mask;
459 data |= (val & mask);
460 pci_write_config_byte(pci, reg, data);
461 }
462
463 static void azx_init_pci(struct azx *chip)
464 {
465 int snoop_type = azx_get_snoop_type(chip);
466
467 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
468 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
469 * Ensuring these bits are 0 clears playback static on some HD Audio
470 * codecs.
471 * The PCI register TCSEL is defined in the Intel manuals.
472 */
473 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
474 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
475 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
476 }
477
478 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
479 * we need to enable snoop.
480 */
481 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
482 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
483 azx_snoop(chip));
484 update_pci_byte(chip->pci,
485 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
486 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
487 }
488
489 /* For NVIDIA HDA, enable snoop */
490 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
491 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
492 azx_snoop(chip));
493 update_pci_byte(chip->pci,
494 NVIDIA_HDA_TRANSREG_ADDR,
495 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
496 update_pci_byte(chip->pci,
497 NVIDIA_HDA_ISTRM_COH,
498 0x01, NVIDIA_HDA_ENABLE_COHBIT);
499 update_pci_byte(chip->pci,
500 NVIDIA_HDA_OSTRM_COH,
501 0x01, NVIDIA_HDA_ENABLE_COHBIT);
502 }
503
504 /* Enable SCH/PCH snoop if needed */
505 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
506 unsigned short snoop;
507 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
508 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
509 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
510 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
511 if (!azx_snoop(chip))
512 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
513 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
514 pci_read_config_word(chip->pci,
515 INTEL_SCH_HDA_DEVC, &snoop);
516 }
517 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
518 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
519 "Disabled" : "Enabled");
520 }
521 }
522
523 /*
524 * In BXT-P A0, HD-Audio DMA requests is later than expected,
525 * and makes an audio stream sensitive to system latencies when
526 * 24/32 bits are playing.
527 * Adjusting threshold of DMA fifo to force the DMA request
528 * sooner to improve latency tolerance at the expense of power.
529 */
530 static void bxt_reduce_dma_latency(struct azx *chip)
531 {
532 u32 val;
533
534 val = azx_readl(chip, SKL_EM4L);
535 val &= (0x3 << 20);
536 azx_writel(chip, SKL_EM4L, val);
537 }
538
539 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
540 {
541 struct hdac_bus *bus = azx_bus(chip);
542 struct pci_dev *pci = chip->pci;
543 u32 val;
544
545 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
546 snd_hdac_set_codec_wakeup(bus, true);
547 if (IS_SKL_PLUS(pci)) {
548 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
549 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
550 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
551 }
552 azx_init_chip(chip, full_reset);
553 if (IS_SKL_PLUS(pci)) {
554 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
555 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
556 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
557 }
558 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
559 snd_hdac_set_codec_wakeup(bus, false);
560
561 /* reduce dma latency to avoid noise */
562 if (IS_BXT(pci))
563 bxt_reduce_dma_latency(chip);
564 }
565
566 /* calculate runtime delay from LPIB */
567 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
568 unsigned int pos)
569 {
570 struct snd_pcm_substream *substream = azx_dev->core.substream;
571 int stream = substream->stream;
572 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
573 int delay;
574
575 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
576 delay = pos - lpib_pos;
577 else
578 delay = lpib_pos - pos;
579 if (delay < 0) {
580 if (delay >= azx_dev->core.delay_negative_threshold)
581 delay = 0;
582 else
583 delay += azx_dev->core.bufsize;
584 }
585
586 if (delay >= azx_dev->core.period_bytes) {
587 dev_info(chip->card->dev,
588 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
589 delay, azx_dev->core.period_bytes);
590 delay = 0;
591 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
592 chip->get_delay[stream] = NULL;
593 }
594
595 return bytes_to_frames(substream->runtime, delay);
596 }
597
598 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
599
600 /* called from IRQ */
601 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
602 {
603 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
604 int ok;
605
606 ok = azx_position_ok(chip, azx_dev);
607 if (ok == 1) {
608 azx_dev->irq_pending = 0;
609 return ok;
610 } else if (ok == 0) {
611 /* bogus IRQ, process it later */
612 azx_dev->irq_pending = 1;
613 schedule_work(&hda->irq_pending_work);
614 }
615 return 0;
616 }
617
618 /* Enable/disable i915 display power for the link */
619 static int azx_intel_link_power(struct azx *chip, bool enable)
620 {
621 struct hdac_bus *bus = azx_bus(chip);
622
623 return snd_hdac_display_power(bus, enable);
624 }
625
626 /*
627 * Check whether the current DMA position is acceptable for updating
628 * periods. Returns non-zero if it's OK.
629 *
630 * Many HD-audio controllers appear pretty inaccurate about
631 * the update-IRQ timing. The IRQ is issued before actually the
632 * data is processed. So, we need to process it afterwords in a
633 * workqueue.
634 */
635 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
636 {
637 struct snd_pcm_substream *substream = azx_dev->core.substream;
638 int stream = substream->stream;
639 u32 wallclk;
640 unsigned int pos;
641
642 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
643 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
644 return -1; /* bogus (too early) interrupt */
645
646 if (chip->get_position[stream])
647 pos = chip->get_position[stream](chip, azx_dev);
648 else { /* use the position buffer as default */
649 pos = azx_get_pos_posbuf(chip, azx_dev);
650 if (!pos || pos == (u32)-1) {
651 dev_info(chip->card->dev,
652 "Invalid position buffer, using LPIB read method instead.\n");
653 chip->get_position[stream] = azx_get_pos_lpib;
654 if (chip->get_position[0] == azx_get_pos_lpib &&
655 chip->get_position[1] == azx_get_pos_lpib)
656 azx_bus(chip)->use_posbuf = false;
657 pos = azx_get_pos_lpib(chip, azx_dev);
658 chip->get_delay[stream] = NULL;
659 } else {
660 chip->get_position[stream] = azx_get_pos_posbuf;
661 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
662 chip->get_delay[stream] = azx_get_delay_from_lpib;
663 }
664 }
665
666 if (pos >= azx_dev->core.bufsize)
667 pos = 0;
668
669 if (WARN_ONCE(!azx_dev->core.period_bytes,
670 "hda-intel: zero azx_dev->period_bytes"))
671 return -1; /* this shouldn't happen! */
672 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
673 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
674 /* NG - it's below the first next period boundary */
675 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
676 azx_dev->core.start_wallclk += wallclk;
677 return 1; /* OK, it's fine */
678 }
679
680 /*
681 * The work for pending PCM period updates.
682 */
683 static void azx_irq_pending_work(struct work_struct *work)
684 {
685 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
686 struct azx *chip = &hda->chip;
687 struct hdac_bus *bus = azx_bus(chip);
688 struct hdac_stream *s;
689 int pending, ok;
690
691 if (!hda->irq_pending_warned) {
692 dev_info(chip->card->dev,
693 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
694 chip->card->number);
695 hda->irq_pending_warned = 1;
696 }
697
698 for (;;) {
699 pending = 0;
700 spin_lock_irq(&bus->reg_lock);
701 list_for_each_entry(s, &bus->stream_list, list) {
702 struct azx_dev *azx_dev = stream_to_azx_dev(s);
703 if (!azx_dev->irq_pending ||
704 !s->substream ||
705 !s->running)
706 continue;
707 ok = azx_position_ok(chip, azx_dev);
708 if (ok > 0) {
709 azx_dev->irq_pending = 0;
710 spin_unlock(&bus->reg_lock);
711 snd_pcm_period_elapsed(s->substream);
712 spin_lock(&bus->reg_lock);
713 } else if (ok < 0) {
714 pending = 0; /* too early */
715 } else
716 pending++;
717 }
718 spin_unlock_irq(&bus->reg_lock);
719 if (!pending)
720 return;
721 msleep(1);
722 }
723 }
724
725 /* clear irq_pending flags and assure no on-going workq */
726 static void azx_clear_irq_pending(struct azx *chip)
727 {
728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
730
731 spin_lock_irq(&bus->reg_lock);
732 list_for_each_entry(s, &bus->stream_list, list) {
733 struct azx_dev *azx_dev = stream_to_azx_dev(s);
734 azx_dev->irq_pending = 0;
735 }
736 spin_unlock_irq(&bus->reg_lock);
737 }
738
739 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
740 {
741 struct hdac_bus *bus = azx_bus(chip);
742
743 if (request_irq(chip->pci->irq, azx_interrupt,
744 chip->msi ? 0 : IRQF_SHARED,
745 KBUILD_MODNAME, chip)) {
746 dev_err(chip->card->dev,
747 "unable to grab IRQ %d, disabling device\n",
748 chip->pci->irq);
749 if (do_disconnect)
750 snd_card_disconnect(chip->card);
751 return -1;
752 }
753 bus->irq = chip->pci->irq;
754 pci_intx(chip->pci, !chip->msi);
755 return 0;
756 }
757
758 /* get the current DMA position with correction on VIA chips */
759 static unsigned int azx_via_get_position(struct azx *chip,
760 struct azx_dev *azx_dev)
761 {
762 unsigned int link_pos, mini_pos, bound_pos;
763 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
764 unsigned int fifo_size;
765
766 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
767 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
768 /* Playback, no problem using link position */
769 return link_pos;
770 }
771
772 /* Capture */
773 /* For new chipset,
774 * use mod to get the DMA position just like old chipset
775 */
776 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
777 mod_dma_pos %= azx_dev->core.period_bytes;
778
779 /* azx_dev->fifo_size can't get FIFO size of in stream.
780 * Get from base address + offset.
781 */
782 fifo_size = readw(azx_bus(chip)->remap_addr +
783 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
784
785 if (azx_dev->insufficient) {
786 /* Link position never gather than FIFO size */
787 if (link_pos <= fifo_size)
788 return 0;
789
790 azx_dev->insufficient = 0;
791 }
792
793 if (link_pos <= fifo_size)
794 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
795 else
796 mini_pos = link_pos - fifo_size;
797
798 /* Find nearest previous boudary */
799 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
800 mod_link_pos = link_pos % azx_dev->core.period_bytes;
801 if (mod_link_pos >= fifo_size)
802 bound_pos = link_pos - mod_link_pos;
803 else if (mod_dma_pos >= mod_mini_pos)
804 bound_pos = mini_pos - mod_mini_pos;
805 else {
806 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
807 if (bound_pos >= azx_dev->core.bufsize)
808 bound_pos = 0;
809 }
810
811 /* Calculate real DMA position we want */
812 return bound_pos + mod_dma_pos;
813 }
814
815 #ifdef CONFIG_PM
816 static DEFINE_MUTEX(card_list_lock);
817 static LIST_HEAD(card_list);
818
819 static void azx_add_card_list(struct azx *chip)
820 {
821 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
822 mutex_lock(&card_list_lock);
823 list_add(&hda->list, &card_list);
824 mutex_unlock(&card_list_lock);
825 }
826
827 static void azx_del_card_list(struct azx *chip)
828 {
829 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
830 mutex_lock(&card_list_lock);
831 list_del_init(&hda->list);
832 mutex_unlock(&card_list_lock);
833 }
834
835 /* trigger power-save check at writing parameter */
836 static int param_set_xint(const char *val, const struct kernel_param *kp)
837 {
838 struct hda_intel *hda;
839 struct azx *chip;
840 int prev = power_save;
841 int ret = param_set_int(val, kp);
842
843 if (ret || prev == power_save)
844 return ret;
845
846 mutex_lock(&card_list_lock);
847 list_for_each_entry(hda, &card_list, list) {
848 chip = &hda->chip;
849 if (!hda->probe_continued || chip->disabled)
850 continue;
851 snd_hda_set_power_save(&chip->bus, power_save * 1000);
852 }
853 mutex_unlock(&card_list_lock);
854 return 0;
855 }
856 #else
857 #define azx_add_card_list(chip) /* NOP */
858 #define azx_del_card_list(chip) /* NOP */
859 #endif /* CONFIG_PM */
860
861 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
862 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
863 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
864 * BCLK = CDCLK * M / N
865 * The values will be lost when the display power well is disabled and need to
866 * be restored to avoid abnormal playback speed.
867 */
868 static void haswell_set_bclk(struct hda_intel *hda)
869 {
870 struct azx *chip = &hda->chip;
871 int cdclk_freq;
872 unsigned int bclk_m, bclk_n;
873
874 if (!hda->need_i915_power)
875 return;
876
877 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
878 switch (cdclk_freq) {
879 case 337500:
880 bclk_m = 16;
881 bclk_n = 225;
882 break;
883
884 case 450000:
885 default: /* default CDCLK 450MHz */
886 bclk_m = 4;
887 bclk_n = 75;
888 break;
889
890 case 540000:
891 bclk_m = 4;
892 bclk_n = 90;
893 break;
894
895 case 675000:
896 bclk_m = 8;
897 bclk_n = 225;
898 break;
899 }
900
901 azx_writew(chip, HSW_EM4, bclk_m);
902 azx_writew(chip, HSW_EM5, bclk_n);
903 }
904
905 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
906 /*
907 * power management
908 */
909 static int azx_suspend(struct device *dev)
910 {
911 struct snd_card *card = dev_get_drvdata(dev);
912 struct azx *chip;
913 struct hda_intel *hda;
914 struct hdac_bus *bus;
915
916 if (!card)
917 return 0;
918
919 chip = card->private_data;
920 hda = container_of(chip, struct hda_intel, chip);
921 if (chip->disabled || hda->init_failed || !chip->running)
922 return 0;
923
924 bus = azx_bus(chip);
925 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
926 azx_clear_irq_pending(chip);
927 azx_stop_chip(chip);
928 azx_enter_link_reset(chip);
929 if (bus->irq >= 0) {
930 free_irq(bus->irq, chip);
931 bus->irq = -1;
932 }
933
934 if (chip->msi)
935 pci_disable_msi(chip->pci);
936 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
937 && hda->need_i915_power)
938 snd_hdac_display_power(bus, false);
939
940 trace_azx_suspend(chip);
941 return 0;
942 }
943
944 static int azx_resume(struct device *dev)
945 {
946 struct pci_dev *pci = to_pci_dev(dev);
947 struct snd_card *card = dev_get_drvdata(dev);
948 struct azx *chip;
949 struct hda_intel *hda;
950 struct hdac_bus *bus;
951
952 if (!card)
953 return 0;
954
955 chip = card->private_data;
956 hda = container_of(chip, struct hda_intel, chip);
957 bus = azx_bus(chip);
958 if (chip->disabled || hda->init_failed || !chip->running)
959 return 0;
960
961 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
962 snd_hdac_display_power(bus, true);
963 if (hda->need_i915_power)
964 haswell_set_bclk(hda);
965 }
966
967 if (chip->msi)
968 if (pci_enable_msi(pci) < 0)
969 chip->msi = 0;
970 if (azx_acquire_irq(chip, 1) < 0)
971 return -EIO;
972 azx_init_pci(chip);
973
974 hda_intel_init_chip(chip, true);
975
976 /* power down again for link-controlled chips */
977 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
978 !hda->need_i915_power)
979 snd_hdac_display_power(bus, false);
980
981 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
982
983 trace_azx_resume(chip);
984 return 0;
985 }
986 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
987
988 #ifdef CONFIG_PM_SLEEP
989 /* put codec down to D3 at hibernation for Intel SKL+;
990 * otherwise BIOS may still access the codec and screw up the driver
991 */
992 static int azx_freeze_noirq(struct device *dev)
993 {
994 struct pci_dev *pci = to_pci_dev(dev);
995
996 if (IS_SKL_PLUS(pci))
997 pci_set_power_state(pci, PCI_D3hot);
998
999 return 0;
1000 }
1001
1002 static int azx_thaw_noirq(struct device *dev)
1003 {
1004 struct pci_dev *pci = to_pci_dev(dev);
1005
1006 if (IS_SKL_PLUS(pci))
1007 pci_set_power_state(pci, PCI_D0);
1008
1009 return 0;
1010 }
1011 #endif /* CONFIG_PM_SLEEP */
1012
1013 #ifdef CONFIG_PM
1014 static int azx_runtime_suspend(struct device *dev)
1015 {
1016 struct snd_card *card = dev_get_drvdata(dev);
1017 struct azx *chip;
1018 struct hda_intel *hda;
1019
1020 if (!card)
1021 return 0;
1022
1023 chip = card->private_data;
1024 hda = container_of(chip, struct hda_intel, chip);
1025 if (chip->disabled || hda->init_failed)
1026 return 0;
1027
1028 if (!azx_has_pm_runtime(chip))
1029 return 0;
1030
1031 /* enable controller wake up event */
1032 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1033 STATESTS_INT_MASK);
1034
1035 azx_stop_chip(chip);
1036 azx_enter_link_reset(chip);
1037 azx_clear_irq_pending(chip);
1038 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1039 && hda->need_i915_power)
1040 snd_hdac_display_power(azx_bus(chip), false);
1041
1042 trace_azx_runtime_suspend(chip);
1043 return 0;
1044 }
1045
1046 static int azx_runtime_resume(struct device *dev)
1047 {
1048 struct snd_card *card = dev_get_drvdata(dev);
1049 struct azx *chip;
1050 struct hda_intel *hda;
1051 struct hdac_bus *bus;
1052 struct hda_codec *codec;
1053 int status;
1054
1055 if (!card)
1056 return 0;
1057
1058 chip = card->private_data;
1059 hda = container_of(chip, struct hda_intel, chip);
1060 bus = azx_bus(chip);
1061 if (chip->disabled || hda->init_failed)
1062 return 0;
1063
1064 if (!azx_has_pm_runtime(chip))
1065 return 0;
1066
1067 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1068 snd_hdac_display_power(bus, true);
1069 if (hda->need_i915_power)
1070 haswell_set_bclk(hda);
1071 }
1072
1073 /* Read STATESTS before controller reset */
1074 status = azx_readw(chip, STATESTS);
1075
1076 azx_init_pci(chip);
1077 hda_intel_init_chip(chip, true);
1078
1079 if (status) {
1080 list_for_each_codec(codec, &chip->bus)
1081 if (status & (1 << codec->addr))
1082 schedule_delayed_work(&codec->jackpoll_work,
1083 codec->jackpoll_interval);
1084 }
1085
1086 /* disable controller Wake Up event*/
1087 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1088 ~STATESTS_INT_MASK);
1089
1090 /* power down again for link-controlled chips */
1091 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1092 !hda->need_i915_power)
1093 snd_hdac_display_power(bus, false);
1094
1095 trace_azx_runtime_resume(chip);
1096 return 0;
1097 }
1098
1099 static int azx_runtime_idle(struct device *dev)
1100 {
1101 struct snd_card *card = dev_get_drvdata(dev);
1102 struct azx *chip;
1103 struct hda_intel *hda;
1104
1105 if (!card)
1106 return 0;
1107
1108 chip = card->private_data;
1109 hda = container_of(chip, struct hda_intel, chip);
1110 if (chip->disabled || hda->init_failed)
1111 return 0;
1112
1113 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1114 azx_bus(chip)->codec_powered || !chip->running)
1115 return -EBUSY;
1116
1117 return 0;
1118 }
1119
1120 static const struct dev_pm_ops azx_pm = {
1121 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1122 #ifdef CONFIG_PM_SLEEP
1123 .freeze_noirq = azx_freeze_noirq,
1124 .thaw_noirq = azx_thaw_noirq,
1125 #endif
1126 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1127 };
1128
1129 #define AZX_PM_OPS &azx_pm
1130 #else
1131 #define AZX_PM_OPS NULL
1132 #endif /* CONFIG_PM */
1133
1134
1135 static int azx_probe_continue(struct azx *chip);
1136
1137 #ifdef SUPPORT_VGA_SWITCHEROO
1138 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1139
1140 static void azx_vs_set_state(struct pci_dev *pci,
1141 enum vga_switcheroo_state state)
1142 {
1143 struct snd_card *card = pci_get_drvdata(pci);
1144 struct azx *chip = card->private_data;
1145 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1146 bool disabled;
1147
1148 wait_for_completion(&hda->probe_wait);
1149 if (hda->init_failed)
1150 return;
1151
1152 disabled = (state == VGA_SWITCHEROO_OFF);
1153 if (chip->disabled == disabled)
1154 return;
1155
1156 if (!hda->probe_continued) {
1157 chip->disabled = disabled;
1158 if (!disabled) {
1159 dev_info(chip->card->dev,
1160 "Start delayed initialization\n");
1161 if (azx_probe_continue(chip) < 0) {
1162 dev_err(chip->card->dev, "initialization error\n");
1163 hda->init_failed = true;
1164 }
1165 }
1166 } else {
1167 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1168 disabled ? "Disabling" : "Enabling");
1169 if (disabled) {
1170 pm_runtime_put_sync_suspend(card->dev);
1171 azx_suspend(card->dev);
1172 /* when we get suspended by vga_switcheroo we end up in D3cold,
1173 * however we have no ACPI handle, so pci/acpi can't put us there,
1174 * put ourselves there */
1175 pci->current_state = PCI_D3cold;
1176 chip->disabled = true;
1177 if (snd_hda_lock_devices(&chip->bus))
1178 dev_warn(chip->card->dev,
1179 "Cannot lock devices!\n");
1180 } else {
1181 snd_hda_unlock_devices(&chip->bus);
1182 pm_runtime_get_noresume(card->dev);
1183 chip->disabled = false;
1184 azx_resume(card->dev);
1185 }
1186 }
1187 }
1188
1189 static bool azx_vs_can_switch(struct pci_dev *pci)
1190 {
1191 struct snd_card *card = pci_get_drvdata(pci);
1192 struct azx *chip = card->private_data;
1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1194
1195 wait_for_completion(&hda->probe_wait);
1196 if (hda->init_failed)
1197 return false;
1198 if (chip->disabled || !hda->probe_continued)
1199 return true;
1200 if (snd_hda_lock_devices(&chip->bus))
1201 return false;
1202 snd_hda_unlock_devices(&chip->bus);
1203 return true;
1204 }
1205
1206 static void init_vga_switcheroo(struct azx *chip)
1207 {
1208 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1209 struct pci_dev *p = get_bound_vga(chip->pci);
1210 if (p) {
1211 dev_info(chip->card->dev,
1212 "Handle vga_switcheroo audio client\n");
1213 hda->use_vga_switcheroo = 1;
1214 pci_dev_put(p);
1215 }
1216 }
1217
1218 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1219 .set_gpu_state = azx_vs_set_state,
1220 .can_switch = azx_vs_can_switch,
1221 };
1222
1223 static int register_vga_switcheroo(struct azx *chip)
1224 {
1225 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1226 int err;
1227
1228 if (!hda->use_vga_switcheroo)
1229 return 0;
1230 /* FIXME: currently only handling DIS controller
1231 * is there any machine with two switchable HDMI audio controllers?
1232 */
1233 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1234 VGA_SWITCHEROO_DIS);
1235 if (err < 0)
1236 return err;
1237 hda->vga_switcheroo_registered = 1;
1238
1239 /* register as an optimus hdmi audio power domain */
1240 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1241 &hda->hdmi_pm_domain);
1242 return 0;
1243 }
1244 #else
1245 #define init_vga_switcheroo(chip) /* NOP */
1246 #define register_vga_switcheroo(chip) 0
1247 #define check_hdmi_disabled(pci) false
1248 #endif /* SUPPORT_VGA_SWITCHER */
1249
1250 /*
1251 * destructor
1252 */
1253 static int azx_free(struct azx *chip)
1254 {
1255 struct pci_dev *pci = chip->pci;
1256 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1257 struct hdac_bus *bus = azx_bus(chip);
1258
1259 if (azx_has_pm_runtime(chip) && chip->running)
1260 pm_runtime_get_noresume(&pci->dev);
1261
1262 azx_del_card_list(chip);
1263
1264 hda->init_failed = 1; /* to be sure */
1265 complete_all(&hda->probe_wait);
1266
1267 if (use_vga_switcheroo(hda)) {
1268 if (chip->disabled && hda->probe_continued)
1269 snd_hda_unlock_devices(&chip->bus);
1270 if (hda->vga_switcheroo_registered) {
1271 vga_switcheroo_unregister_client(chip->pci);
1272 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1273 }
1274 }
1275
1276 if (bus->chip_init) {
1277 azx_clear_irq_pending(chip);
1278 azx_stop_all_streams(chip);
1279 azx_stop_chip(chip);
1280 }
1281
1282 if (bus->irq >= 0)
1283 free_irq(bus->irq, (void*)chip);
1284 if (chip->msi)
1285 pci_disable_msi(chip->pci);
1286 iounmap(bus->remap_addr);
1287
1288 azx_free_stream_pages(chip);
1289 azx_free_streams(chip);
1290 snd_hdac_bus_exit(bus);
1291
1292 if (chip->region_requested)
1293 pci_release_regions(chip->pci);
1294
1295 pci_disable_device(chip->pci);
1296 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1297 release_firmware(chip->fw);
1298 #endif
1299
1300 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1301 if (hda->need_i915_power)
1302 snd_hdac_display_power(bus, false);
1303 snd_hdac_i915_exit(bus);
1304 }
1305 kfree(hda);
1306
1307 return 0;
1308 }
1309
1310 static int azx_dev_disconnect(struct snd_device *device)
1311 {
1312 struct azx *chip = device->device_data;
1313
1314 chip->bus.shutdown = 1;
1315 return 0;
1316 }
1317
1318 static int azx_dev_free(struct snd_device *device)
1319 {
1320 return azx_free(device->device_data);
1321 }
1322
1323 #ifdef SUPPORT_VGA_SWITCHEROO
1324 /*
1325 * Check of disabled HDMI controller by vga_switcheroo
1326 */
1327 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1328 {
1329 struct pci_dev *p;
1330
1331 /* check only discrete GPU */
1332 switch (pci->vendor) {
1333 case PCI_VENDOR_ID_ATI:
1334 case PCI_VENDOR_ID_AMD:
1335 case PCI_VENDOR_ID_NVIDIA:
1336 if (pci->devfn == 1) {
1337 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1338 pci->bus->number, 0);
1339 if (p) {
1340 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1341 return p;
1342 pci_dev_put(p);
1343 }
1344 }
1345 break;
1346 }
1347 return NULL;
1348 }
1349
1350 static bool check_hdmi_disabled(struct pci_dev *pci)
1351 {
1352 bool vga_inactive = false;
1353 struct pci_dev *p = get_bound_vga(pci);
1354
1355 if (p) {
1356 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1357 vga_inactive = true;
1358 pci_dev_put(p);
1359 }
1360 return vga_inactive;
1361 }
1362 #endif /* SUPPORT_VGA_SWITCHEROO */
1363
1364 /*
1365 * white/black-listing for position_fix
1366 */
1367 static struct snd_pci_quirk position_fix_list[] = {
1368 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1369 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1370 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1371 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1372 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1373 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1374 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1375 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1376 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1377 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1378 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1379 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1380 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1381 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1382 {}
1383 };
1384
1385 static int check_position_fix(struct azx *chip, int fix)
1386 {
1387 const struct snd_pci_quirk *q;
1388
1389 switch (fix) {
1390 case POS_FIX_AUTO:
1391 case POS_FIX_LPIB:
1392 case POS_FIX_POSBUF:
1393 case POS_FIX_VIACOMBO:
1394 case POS_FIX_COMBO:
1395 return fix;
1396 }
1397
1398 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1399 if (q) {
1400 dev_info(chip->card->dev,
1401 "position_fix set to %d for device %04x:%04x\n",
1402 q->value, q->subvendor, q->subdevice);
1403 return q->value;
1404 }
1405
1406 /* Check VIA/ATI HD Audio Controller exist */
1407 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1408 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1409 return POS_FIX_VIACOMBO;
1410 }
1411 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1412 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1413 return POS_FIX_LPIB;
1414 }
1415 return POS_FIX_AUTO;
1416 }
1417
1418 static void assign_position_fix(struct azx *chip, int fix)
1419 {
1420 static azx_get_pos_callback_t callbacks[] = {
1421 [POS_FIX_AUTO] = NULL,
1422 [POS_FIX_LPIB] = azx_get_pos_lpib,
1423 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1424 [POS_FIX_VIACOMBO] = azx_via_get_position,
1425 [POS_FIX_COMBO] = azx_get_pos_lpib,
1426 };
1427
1428 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1429
1430 /* combo mode uses LPIB only for playback */
1431 if (fix == POS_FIX_COMBO)
1432 chip->get_position[1] = NULL;
1433
1434 if (fix == POS_FIX_POSBUF &&
1435 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1436 chip->get_delay[0] = chip->get_delay[1] =
1437 azx_get_delay_from_lpib;
1438 }
1439
1440 }
1441
1442 /*
1443 * black-lists for probe_mask
1444 */
1445 static struct snd_pci_quirk probe_mask_list[] = {
1446 /* Thinkpad often breaks the controller communication when accessing
1447 * to the non-working (or non-existing) modem codec slot.
1448 */
1449 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1450 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1451 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1452 /* broken BIOS */
1453 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1454 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1455 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1456 /* forced codec slots */
1457 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1458 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1459 /* WinFast VP200 H (Teradici) user reported broken communication */
1460 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1461 {}
1462 };
1463
1464 #define AZX_FORCE_CODEC_MASK 0x100
1465
1466 static void check_probe_mask(struct azx *chip, int dev)
1467 {
1468 const struct snd_pci_quirk *q;
1469
1470 chip->codec_probe_mask = probe_mask[dev];
1471 if (chip->codec_probe_mask == -1) {
1472 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1473 if (q) {
1474 dev_info(chip->card->dev,
1475 "probe_mask set to 0x%x for device %04x:%04x\n",
1476 q->value, q->subvendor, q->subdevice);
1477 chip->codec_probe_mask = q->value;
1478 }
1479 }
1480
1481 /* check forced option */
1482 if (chip->codec_probe_mask != -1 &&
1483 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1484 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1485 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1486 (int)azx_bus(chip)->codec_mask);
1487 }
1488 }
1489
1490 /*
1491 * white/black-list for enable_msi
1492 */
1493 static struct snd_pci_quirk msi_black_list[] = {
1494 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1495 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1496 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1497 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1498 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1499 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1500 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1501 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1502 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1503 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1504 {}
1505 };
1506
1507 static void check_msi(struct azx *chip)
1508 {
1509 const struct snd_pci_quirk *q;
1510
1511 if (enable_msi >= 0) {
1512 chip->msi = !!enable_msi;
1513 return;
1514 }
1515 chip->msi = 1; /* enable MSI as default */
1516 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1517 if (q) {
1518 dev_info(chip->card->dev,
1519 "msi for device %04x:%04x set to %d\n",
1520 q->subvendor, q->subdevice, q->value);
1521 chip->msi = q->value;
1522 return;
1523 }
1524
1525 /* NVidia chipsets seem to cause troubles with MSI */
1526 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1527 dev_info(chip->card->dev, "Disabling MSI\n");
1528 chip->msi = 0;
1529 }
1530 }
1531
1532 /* check the snoop mode availability */
1533 static void azx_check_snoop_available(struct azx *chip)
1534 {
1535 int snoop = hda_snoop;
1536
1537 if (snoop >= 0) {
1538 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1539 snoop ? "snoop" : "non-snoop");
1540 chip->snoop = snoop;
1541 return;
1542 }
1543
1544 snoop = true;
1545 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1546 chip->driver_type == AZX_DRIVER_VIA) {
1547 /* force to non-snoop mode for a new VIA controller
1548 * when BIOS is set
1549 */
1550 u8 val;
1551 pci_read_config_byte(chip->pci, 0x42, &val);
1552 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1553 chip->pci->revision == 0x20))
1554 snoop = false;
1555 }
1556
1557 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1558 snoop = false;
1559
1560 chip->snoop = snoop;
1561 if (!snoop)
1562 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1563 }
1564
1565 static void azx_probe_work(struct work_struct *work)
1566 {
1567 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1568 azx_probe_continue(&hda->chip);
1569 }
1570
1571 /*
1572 * constructor
1573 */
1574 static const struct hdac_io_ops pci_hda_io_ops;
1575 static const struct hda_controller_ops pci_hda_ops;
1576
1577 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1578 int dev, unsigned int driver_caps,
1579 struct azx **rchip)
1580 {
1581 static struct snd_device_ops ops = {
1582 .dev_disconnect = azx_dev_disconnect,
1583 .dev_free = azx_dev_free,
1584 };
1585 struct hda_intel *hda;
1586 struct azx *chip;
1587 int err;
1588
1589 *rchip = NULL;
1590
1591 err = pci_enable_device(pci);
1592 if (err < 0)
1593 return err;
1594
1595 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1596 if (!hda) {
1597 pci_disable_device(pci);
1598 return -ENOMEM;
1599 }
1600
1601 chip = &hda->chip;
1602 mutex_init(&chip->open_mutex);
1603 chip->card = card;
1604 chip->pci = pci;
1605 chip->ops = &pci_hda_ops;
1606 chip->driver_caps = driver_caps;
1607 chip->driver_type = driver_caps & 0xff;
1608 check_msi(chip);
1609 chip->dev_index = dev;
1610 chip->jackpoll_ms = jackpoll_ms;
1611 INIT_LIST_HEAD(&chip->pcm_list);
1612 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1613 INIT_LIST_HEAD(&hda->list);
1614 init_vga_switcheroo(chip);
1615 init_completion(&hda->probe_wait);
1616
1617 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1618
1619 check_probe_mask(chip, dev);
1620
1621 chip->single_cmd = single_cmd;
1622 azx_check_snoop_available(chip);
1623
1624 if (bdl_pos_adj[dev] < 0) {
1625 switch (chip->driver_type) {
1626 case AZX_DRIVER_ICH:
1627 case AZX_DRIVER_PCH:
1628 bdl_pos_adj[dev] = 1;
1629 break;
1630 default:
1631 bdl_pos_adj[dev] = 32;
1632 break;
1633 }
1634 }
1635 chip->bdl_pos_adj = bdl_pos_adj;
1636
1637 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1638 if (err < 0) {
1639 kfree(hda);
1640 pci_disable_device(pci);
1641 return err;
1642 }
1643
1644 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1645 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1646 chip->bus.needs_damn_long_delay = 1;
1647 }
1648
1649 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1650 if (err < 0) {
1651 dev_err(card->dev, "Error creating device [card]!\n");
1652 azx_free(chip);
1653 return err;
1654 }
1655
1656 /* continue probing in work context as may trigger request module */
1657 INIT_WORK(&hda->probe_work, azx_probe_work);
1658
1659 *rchip = chip;
1660
1661 return 0;
1662 }
1663
1664 static int azx_first_init(struct azx *chip)
1665 {
1666 int dev = chip->dev_index;
1667 struct pci_dev *pci = chip->pci;
1668 struct snd_card *card = chip->card;
1669 struct hdac_bus *bus = azx_bus(chip);
1670 int err;
1671 unsigned short gcap;
1672 unsigned int dma_bits = 64;
1673
1674 #if BITS_PER_LONG != 64
1675 /* Fix up base address on ULI M5461 */
1676 if (chip->driver_type == AZX_DRIVER_ULI) {
1677 u16 tmp3;
1678 pci_read_config_word(pci, 0x40, &tmp3);
1679 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1680 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1681 }
1682 #endif
1683
1684 err = pci_request_regions(pci, "ICH HD audio");
1685 if (err < 0)
1686 return err;
1687 chip->region_requested = 1;
1688
1689 bus->addr = pci_resource_start(pci, 0);
1690 bus->remap_addr = pci_ioremap_bar(pci, 0);
1691 if (bus->remap_addr == NULL) {
1692 dev_err(card->dev, "ioremap error\n");
1693 return -ENXIO;
1694 }
1695
1696 if (chip->msi) {
1697 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1698 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1699 pci->no_64bit_msi = true;
1700 }
1701 if (pci_enable_msi(pci) < 0)
1702 chip->msi = 0;
1703 }
1704
1705 if (azx_acquire_irq(chip, 0) < 0)
1706 return -EBUSY;
1707
1708 pci_set_master(pci);
1709 synchronize_irq(bus->irq);
1710
1711 gcap = azx_readw(chip, GCAP);
1712 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1713
1714 /* AMD devices support 40 or 48bit DMA, take the safe one */
1715 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1716 dma_bits = 40;
1717
1718 /* disable SB600 64bit support for safety */
1719 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1720 struct pci_dev *p_smbus;
1721 dma_bits = 40;
1722 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1723 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1724 NULL);
1725 if (p_smbus) {
1726 if (p_smbus->revision < 0x30)
1727 gcap &= ~AZX_GCAP_64OK;
1728 pci_dev_put(p_smbus);
1729 }
1730 }
1731
1732 /* NVidia hardware normally only supports up to 40 bits of DMA */
1733 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1734 dma_bits = 40;
1735
1736 /* disable 64bit DMA address on some devices */
1737 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1738 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1739 gcap &= ~AZX_GCAP_64OK;
1740 }
1741
1742 /* disable buffer size rounding to 128-byte multiples if supported */
1743 if (align_buffer_size >= 0)
1744 chip->align_buffer_size = !!align_buffer_size;
1745 else {
1746 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1747 chip->align_buffer_size = 0;
1748 else
1749 chip->align_buffer_size = 1;
1750 }
1751
1752 /* allow 64bit DMA address if supported by H/W */
1753 if (!(gcap & AZX_GCAP_64OK))
1754 dma_bits = 32;
1755 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1756 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1757 } else {
1758 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1759 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1760 }
1761
1762 /* read number of streams from GCAP register instead of using
1763 * hardcoded value
1764 */
1765 chip->capture_streams = (gcap >> 8) & 0x0f;
1766 chip->playback_streams = (gcap >> 12) & 0x0f;
1767 if (!chip->playback_streams && !chip->capture_streams) {
1768 /* gcap didn't give any info, switching to old method */
1769
1770 switch (chip->driver_type) {
1771 case AZX_DRIVER_ULI:
1772 chip->playback_streams = ULI_NUM_PLAYBACK;
1773 chip->capture_streams = ULI_NUM_CAPTURE;
1774 break;
1775 case AZX_DRIVER_ATIHDMI:
1776 case AZX_DRIVER_ATIHDMI_NS:
1777 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1778 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1779 break;
1780 case AZX_DRIVER_GENERIC:
1781 default:
1782 chip->playback_streams = ICH6_NUM_PLAYBACK;
1783 chip->capture_streams = ICH6_NUM_CAPTURE;
1784 break;
1785 }
1786 }
1787 chip->capture_index_offset = 0;
1788 chip->playback_index_offset = chip->capture_streams;
1789 chip->num_streams = chip->playback_streams + chip->capture_streams;
1790
1791 /* initialize streams */
1792 err = azx_init_streams(chip);
1793 if (err < 0)
1794 return err;
1795
1796 err = azx_alloc_stream_pages(chip);
1797 if (err < 0)
1798 return err;
1799
1800 /* initialize chip */
1801 azx_init_pci(chip);
1802
1803 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1804 struct hda_intel *hda;
1805
1806 hda = container_of(chip, struct hda_intel, chip);
1807 haswell_set_bclk(hda);
1808 }
1809
1810 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1811
1812 /* codec detection */
1813 if (!azx_bus(chip)->codec_mask) {
1814 dev_err(card->dev, "no codecs found!\n");
1815 return -ENODEV;
1816 }
1817
1818 strcpy(card->driver, "HDA-Intel");
1819 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1820 sizeof(card->shortname));
1821 snprintf(card->longname, sizeof(card->longname),
1822 "%s at 0x%lx irq %i",
1823 card->shortname, bus->addr, bus->irq);
1824
1825 return 0;
1826 }
1827
1828 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1829 /* callback from request_firmware_nowait() */
1830 static void azx_firmware_cb(const struct firmware *fw, void *context)
1831 {
1832 struct snd_card *card = context;
1833 struct azx *chip = card->private_data;
1834 struct pci_dev *pci = chip->pci;
1835
1836 if (!fw) {
1837 dev_err(card->dev, "Cannot load firmware, aborting\n");
1838 goto error;
1839 }
1840
1841 chip->fw = fw;
1842 if (!chip->disabled) {
1843 /* continue probing */
1844 if (azx_probe_continue(chip))
1845 goto error;
1846 }
1847 return; /* OK */
1848
1849 error:
1850 snd_card_free(card);
1851 pci_set_drvdata(pci, NULL);
1852 }
1853 #endif
1854
1855 /*
1856 * HDA controller ops.
1857 */
1858
1859 /* PCI register access. */
1860 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1861 {
1862 writel(value, addr);
1863 }
1864
1865 static u32 pci_azx_readl(u32 __iomem *addr)
1866 {
1867 return readl(addr);
1868 }
1869
1870 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1871 {
1872 writew(value, addr);
1873 }
1874
1875 static u16 pci_azx_readw(u16 __iomem *addr)
1876 {
1877 return readw(addr);
1878 }
1879
1880 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1881 {
1882 writeb(value, addr);
1883 }
1884
1885 static u8 pci_azx_readb(u8 __iomem *addr)
1886 {
1887 return readb(addr);
1888 }
1889
1890 static int disable_msi_reset_irq(struct azx *chip)
1891 {
1892 struct hdac_bus *bus = azx_bus(chip);
1893 int err;
1894
1895 free_irq(bus->irq, chip);
1896 bus->irq = -1;
1897 pci_disable_msi(chip->pci);
1898 chip->msi = 0;
1899 err = azx_acquire_irq(chip, 1);
1900 if (err < 0)
1901 return err;
1902
1903 return 0;
1904 }
1905
1906 /* DMA page allocation helpers. */
1907 static int dma_alloc_pages(struct hdac_bus *bus,
1908 int type,
1909 size_t size,
1910 struct snd_dma_buffer *buf)
1911 {
1912 struct azx *chip = bus_to_azx(bus);
1913 int err;
1914
1915 err = snd_dma_alloc_pages(type,
1916 bus->dev,
1917 size, buf);
1918 if (err < 0)
1919 return err;
1920 mark_pages_wc(chip, buf, true);
1921 return 0;
1922 }
1923
1924 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1925 {
1926 struct azx *chip = bus_to_azx(bus);
1927
1928 mark_pages_wc(chip, buf, false);
1929 snd_dma_free_pages(buf);
1930 }
1931
1932 static int substream_alloc_pages(struct azx *chip,
1933 struct snd_pcm_substream *substream,
1934 size_t size)
1935 {
1936 struct azx_dev *azx_dev = get_azx_dev(substream);
1937 int ret;
1938
1939 mark_runtime_wc(chip, azx_dev, substream, false);
1940 ret = snd_pcm_lib_malloc_pages(substream, size);
1941 if (ret < 0)
1942 return ret;
1943 mark_runtime_wc(chip, azx_dev, substream, true);
1944 return 0;
1945 }
1946
1947 static int substream_free_pages(struct azx *chip,
1948 struct snd_pcm_substream *substream)
1949 {
1950 struct azx_dev *azx_dev = get_azx_dev(substream);
1951 mark_runtime_wc(chip, azx_dev, substream, false);
1952 return snd_pcm_lib_free_pages(substream);
1953 }
1954
1955 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1956 struct vm_area_struct *area)
1957 {
1958 #ifdef CONFIG_X86
1959 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1960 struct azx *chip = apcm->chip;
1961 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1962 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1963 #endif
1964 }
1965
1966 static const struct hdac_io_ops pci_hda_io_ops = {
1967 .reg_writel = pci_azx_writel,
1968 .reg_readl = pci_azx_readl,
1969 .reg_writew = pci_azx_writew,
1970 .reg_readw = pci_azx_readw,
1971 .reg_writeb = pci_azx_writeb,
1972 .reg_readb = pci_azx_readb,
1973 .dma_alloc_pages = dma_alloc_pages,
1974 .dma_free_pages = dma_free_pages,
1975 };
1976
1977 static const struct hda_controller_ops pci_hda_ops = {
1978 .disable_msi_reset_irq = disable_msi_reset_irq,
1979 .substream_alloc_pages = substream_alloc_pages,
1980 .substream_free_pages = substream_free_pages,
1981 .pcm_mmap_prepare = pcm_mmap_prepare,
1982 .position_check = azx_position_check,
1983 .link_power = azx_intel_link_power,
1984 };
1985
1986 static int azx_probe(struct pci_dev *pci,
1987 const struct pci_device_id *pci_id)
1988 {
1989 static int dev;
1990 struct snd_card *card;
1991 struct hda_intel *hda;
1992 struct azx *chip;
1993 bool schedule_probe;
1994 int err;
1995
1996 if (dev >= SNDRV_CARDS)
1997 return -ENODEV;
1998 if (!enable[dev]) {
1999 dev++;
2000 return -ENOENT;
2001 }
2002
2003 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2004 0, &card);
2005 if (err < 0) {
2006 dev_err(&pci->dev, "Error creating card!\n");
2007 return err;
2008 }
2009
2010 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2011 if (err < 0)
2012 goto out_free;
2013 card->private_data = chip;
2014 hda = container_of(chip, struct hda_intel, chip);
2015
2016 pci_set_drvdata(pci, card);
2017
2018 err = register_vga_switcheroo(chip);
2019 if (err < 0) {
2020 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2021 goto out_free;
2022 }
2023
2024 if (check_hdmi_disabled(pci)) {
2025 dev_info(card->dev, "VGA controller is disabled\n");
2026 dev_info(card->dev, "Delaying initialization\n");
2027 chip->disabled = true;
2028 }
2029
2030 schedule_probe = !chip->disabled;
2031
2032 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2033 if (patch[dev] && *patch[dev]) {
2034 dev_info(card->dev, "Applying patch firmware '%s'\n",
2035 patch[dev]);
2036 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2037 &pci->dev, GFP_KERNEL, card,
2038 azx_firmware_cb);
2039 if (err < 0)
2040 goto out_free;
2041 schedule_probe = false; /* continued in azx_firmware_cb() */
2042 }
2043 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2044
2045 #ifndef CONFIG_SND_HDA_I915
2046 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2047 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2048 #endif
2049
2050 if (schedule_probe)
2051 schedule_work(&hda->probe_work);
2052
2053 dev++;
2054 if (chip->disabled)
2055 complete_all(&hda->probe_wait);
2056 return 0;
2057
2058 out_free:
2059 snd_card_free(card);
2060 return err;
2061 }
2062
2063 #ifdef CONFIG_PM
2064 /* On some boards setting power_save to a non 0 value leads to clicking /
2065 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2066 * figure out how to avoid these sounds, but that is not always feasible.
2067 * So we keep a list of devices where we disable powersaving as its known
2068 * to causes problems on these devices.
2069 */
2070 static struct snd_pci_quirk power_save_blacklist[] = {
2071 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2072 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2073 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2074 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2075 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2076 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2077 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2078 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2079 {}
2080 };
2081 #endif /* CONFIG_PM */
2082
2083 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2084 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2085 [AZX_DRIVER_NVIDIA] = 8,
2086 [AZX_DRIVER_TERA] = 1,
2087 };
2088
2089 static int azx_probe_continue(struct azx *chip)
2090 {
2091 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2092 struct hdac_bus *bus = azx_bus(chip);
2093 struct pci_dev *pci = chip->pci;
2094 int dev = chip->dev_index;
2095 int val;
2096 int err;
2097
2098 hda->probe_continued = 1;
2099
2100 /* Request display power well for the HDA controller or codec. For
2101 * Haswell/Broadwell, both the display HDA controller and codec need
2102 * this power. For other platforms, like Baytrail/Braswell, only the
2103 * display codec needs the power and it can be released after probe.
2104 */
2105 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2106 /* HSW/BDW controllers need this power */
2107 if (CONTROLLER_IN_GPU(pci))
2108 hda->need_i915_power = 1;
2109
2110 err = snd_hdac_i915_init(bus);
2111 if (err < 0) {
2112 /* if the controller is bound only with HDMI/DP
2113 * (for HSW and BDW), we need to abort the probe;
2114 * for other chips, still continue probing as other
2115 * codecs can be on the same link.
2116 */
2117 if (CONTROLLER_IN_GPU(pci)) {
2118 dev_err(chip->card->dev,
2119 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2120 goto out_free;
2121 } else
2122 goto skip_i915;
2123 }
2124
2125 err = snd_hdac_display_power(bus, true);
2126 if (err < 0) {
2127 dev_err(chip->card->dev,
2128 "Cannot turn on display power on i915\n");
2129 goto i915_power_fail;
2130 }
2131 }
2132
2133 skip_i915:
2134 err = azx_first_init(chip);
2135 if (err < 0)
2136 goto out_free;
2137
2138 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2139 chip->beep_mode = beep_mode[dev];
2140 #endif
2141
2142 /* create codec instances */
2143 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2144 if (err < 0)
2145 goto out_free;
2146
2147 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2148 if (chip->fw) {
2149 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2150 chip->fw->data);
2151 if (err < 0)
2152 goto out_free;
2153 #ifndef CONFIG_PM
2154 release_firmware(chip->fw); /* no longer needed */
2155 chip->fw = NULL;
2156 #endif
2157 }
2158 #endif
2159 if ((probe_only[dev] & 1) == 0) {
2160 err = azx_codec_configure(chip);
2161 if (err < 0)
2162 goto out_free;
2163 }
2164
2165 err = snd_card_register(chip->card);
2166 if (err < 0)
2167 goto out_free;
2168
2169 chip->running = 1;
2170 azx_add_card_list(chip);
2171
2172 val = power_save;
2173 #ifdef CONFIG_PM
2174 if (pm_blacklist) {
2175 const struct snd_pci_quirk *q;
2176
2177 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2178 if (q && val) {
2179 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2180 q->subvendor, q->subdevice);
2181 val = 0;
2182 }
2183 }
2184 #endif /* CONFIG_PM */
2185 snd_hda_set_power_save(&chip->bus, val * 1000);
2186 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2187 pm_runtime_put_noidle(&pci->dev);
2188
2189 out_free:
2190 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2191 && !hda->need_i915_power)
2192 snd_hdac_display_power(bus, false);
2193
2194 i915_power_fail:
2195 if (err < 0)
2196 hda->init_failed = 1;
2197 complete_all(&hda->probe_wait);
2198 return err;
2199 }
2200
2201 static void azx_remove(struct pci_dev *pci)
2202 {
2203 struct snd_card *card = pci_get_drvdata(pci);
2204 struct azx *chip;
2205 struct hda_intel *hda;
2206
2207 if (card) {
2208 /* cancel the pending probing work */
2209 chip = card->private_data;
2210 hda = container_of(chip, struct hda_intel, chip);
2211 /* FIXME: below is an ugly workaround.
2212 * Both device_release_driver() and driver_probe_device()
2213 * take *both* the device's and its parent's lock before
2214 * calling the remove() and probe() callbacks. The codec
2215 * probe takes the locks of both the codec itself and its
2216 * parent, i.e. the PCI controller dev. Meanwhile, when
2217 * the PCI controller is unbound, it takes its lock, too
2218 * ==> ouch, a deadlock!
2219 * As a workaround, we unlock temporarily here the controller
2220 * device during cancel_work_sync() call.
2221 */
2222 device_unlock(&pci->dev);
2223 cancel_work_sync(&hda->probe_work);
2224 device_lock(&pci->dev);
2225
2226 snd_card_free(card);
2227 }
2228 }
2229
2230 static void azx_shutdown(struct pci_dev *pci)
2231 {
2232 struct snd_card *card = pci_get_drvdata(pci);
2233 struct azx *chip;
2234
2235 if (!card)
2236 return;
2237 chip = card->private_data;
2238 if (chip && chip->running)
2239 azx_stop_chip(chip);
2240 }
2241
2242 /* PCI IDs */
2243 static const struct pci_device_id azx_ids[] = {
2244 /* CPT */
2245 { PCI_DEVICE(0x8086, 0x1c20),
2246 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2247 /* PBG */
2248 { PCI_DEVICE(0x8086, 0x1d20),
2249 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2250 /* Panther Point */
2251 { PCI_DEVICE(0x8086, 0x1e20),
2252 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2253 /* Lynx Point */
2254 { PCI_DEVICE(0x8086, 0x8c20),
2255 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2256 /* 9 Series */
2257 { PCI_DEVICE(0x8086, 0x8ca0),
2258 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2259 /* Wellsburg */
2260 { PCI_DEVICE(0x8086, 0x8d20),
2261 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2262 { PCI_DEVICE(0x8086, 0x8d21),
2263 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2264 /* Lewisburg */
2265 { PCI_DEVICE(0x8086, 0xa1f0),
2266 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2267 { PCI_DEVICE(0x8086, 0xa270),
2268 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2269 /* Lynx Point-LP */
2270 { PCI_DEVICE(0x8086, 0x9c20),
2271 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2272 /* Lynx Point-LP */
2273 { PCI_DEVICE(0x8086, 0x9c21),
2274 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2275 /* Wildcat Point-LP */
2276 { PCI_DEVICE(0x8086, 0x9ca0),
2277 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2278 /* Sunrise Point */
2279 { PCI_DEVICE(0x8086, 0xa170),
2280 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2281 /* Sunrise Point-LP */
2282 { PCI_DEVICE(0x8086, 0x9d70),
2283 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2284 /* Kabylake */
2285 { PCI_DEVICE(0x8086, 0xa171),
2286 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2287 /* Kabylake-LP */
2288 { PCI_DEVICE(0x8086, 0x9d71),
2289 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2290 /* Kabylake-H */
2291 { PCI_DEVICE(0x8086, 0xa2f0),
2292 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2293 /* Broxton-P(Apollolake) */
2294 { PCI_DEVICE(0x8086, 0x5a98),
2295 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2296 /* Broxton-T */
2297 { PCI_DEVICE(0x8086, 0x1a98),
2298 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2299 /* Haswell */
2300 { PCI_DEVICE(0x8086, 0x0a0c),
2301 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2302 { PCI_DEVICE(0x8086, 0x0c0c),
2303 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2304 { PCI_DEVICE(0x8086, 0x0d0c),
2305 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2306 /* Broadwell */
2307 { PCI_DEVICE(0x8086, 0x160c),
2308 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2309 /* 5 Series/3400 */
2310 { PCI_DEVICE(0x8086, 0x3b56),
2311 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2312 /* Poulsbo */
2313 { PCI_DEVICE(0x8086, 0x811b),
2314 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2315 /* Oaktrail */
2316 { PCI_DEVICE(0x8086, 0x080a),
2317 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2318 /* BayTrail */
2319 { PCI_DEVICE(0x8086, 0x0f04),
2320 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2321 /* Braswell */
2322 { PCI_DEVICE(0x8086, 0x2284),
2323 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2324 /* ICH6 */
2325 { PCI_DEVICE(0x8086, 0x2668),
2326 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2327 /* ICH7 */
2328 { PCI_DEVICE(0x8086, 0x27d8),
2329 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2330 /* ESB2 */
2331 { PCI_DEVICE(0x8086, 0x269a),
2332 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2333 /* ICH8 */
2334 { PCI_DEVICE(0x8086, 0x284b),
2335 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2336 /* ICH9 */
2337 { PCI_DEVICE(0x8086, 0x293e),
2338 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2339 /* ICH9 */
2340 { PCI_DEVICE(0x8086, 0x293f),
2341 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2342 /* ICH10 */
2343 { PCI_DEVICE(0x8086, 0x3a3e),
2344 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2345 /* ICH10 */
2346 { PCI_DEVICE(0x8086, 0x3a6e),
2347 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2348 /* Generic Intel */
2349 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2350 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2351 .class_mask = 0xffffff,
2352 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2353 /* ATI SB 450/600/700/800/900 */
2354 { PCI_DEVICE(0x1002, 0x437b),
2355 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2356 { PCI_DEVICE(0x1002, 0x4383),
2357 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2358 /* AMD Hudson */
2359 { PCI_DEVICE(0x1022, 0x780d),
2360 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2361 /* AMD Raven */
2362 { PCI_DEVICE(0x1022, 0x15e3),
2363 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2364 AZX_DCAPS_PM_RUNTIME },
2365 /* ATI HDMI */
2366 { PCI_DEVICE(0x1002, 0x0002),
2367 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2368 { PCI_DEVICE(0x1002, 0x1308),
2369 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2370 { PCI_DEVICE(0x1002, 0x157a),
2371 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2372 { PCI_DEVICE(0x1002, 0x15b3),
2373 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2374 { PCI_DEVICE(0x1002, 0x793b),
2375 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2376 { PCI_DEVICE(0x1002, 0x7919),
2377 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2378 { PCI_DEVICE(0x1002, 0x960f),
2379 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2380 { PCI_DEVICE(0x1002, 0x970f),
2381 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2382 { PCI_DEVICE(0x1002, 0x9840),
2383 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2384 { PCI_DEVICE(0x1002, 0xaa00),
2385 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2386 { PCI_DEVICE(0x1002, 0xaa08),
2387 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2388 { PCI_DEVICE(0x1002, 0xaa10),
2389 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2390 { PCI_DEVICE(0x1002, 0xaa18),
2391 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2392 { PCI_DEVICE(0x1002, 0xaa20),
2393 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2394 { PCI_DEVICE(0x1002, 0xaa28),
2395 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2396 { PCI_DEVICE(0x1002, 0xaa30),
2397 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2398 { PCI_DEVICE(0x1002, 0xaa38),
2399 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2400 { PCI_DEVICE(0x1002, 0xaa40),
2401 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2402 { PCI_DEVICE(0x1002, 0xaa48),
2403 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2404 { PCI_DEVICE(0x1002, 0xaa50),
2405 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2406 { PCI_DEVICE(0x1002, 0xaa58),
2407 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2408 { PCI_DEVICE(0x1002, 0xaa60),
2409 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2410 { PCI_DEVICE(0x1002, 0xaa68),
2411 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2412 { PCI_DEVICE(0x1002, 0xaa80),
2413 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2414 { PCI_DEVICE(0x1002, 0xaa88),
2415 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2416 { PCI_DEVICE(0x1002, 0xaa90),
2417 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2418 { PCI_DEVICE(0x1002, 0xaa98),
2419 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2420 { PCI_DEVICE(0x1002, 0x9902),
2421 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2422 { PCI_DEVICE(0x1002, 0xaaa0),
2423 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2424 { PCI_DEVICE(0x1002, 0xaaa8),
2425 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2426 { PCI_DEVICE(0x1002, 0xaab0),
2427 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2428 { PCI_DEVICE(0x1002, 0xaac0),
2429 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2430 { PCI_DEVICE(0x1002, 0xaac8),
2431 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2432 { PCI_DEVICE(0x1002, 0xaad8),
2433 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2434 { PCI_DEVICE(0x1002, 0xaae8),
2435 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2436 { PCI_DEVICE(0x1002, 0xaae0),
2437 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2438 { PCI_DEVICE(0x1002, 0xaaf0),
2439 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2440 /* VIA VT8251/VT8237A */
2441 { PCI_DEVICE(0x1106, 0x3288),
2442 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2443 /* VIA GFX VT7122/VX900 */
2444 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2445 /* VIA GFX VT6122/VX11 */
2446 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2447 /* SIS966 */
2448 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2449 /* ULI M5461 */
2450 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2451 /* NVIDIA MCP */
2452 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2453 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2454 .class_mask = 0xffffff,
2455 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2456 /* Teradici */
2457 { PCI_DEVICE(0x6549, 0x1200),
2458 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2459 { PCI_DEVICE(0x6549, 0x2200),
2460 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2461 /* Creative X-Fi (CA0110-IBG) */
2462 /* CTHDA chips */
2463 { PCI_DEVICE(0x1102, 0x0010),
2464 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2465 { PCI_DEVICE(0x1102, 0x0012),
2466 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2467 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2468 /* the following entry conflicts with snd-ctxfi driver,
2469 * as ctxfi driver mutates from HD-audio to native mode with
2470 * a special command sequence.
2471 */
2472 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2473 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2474 .class_mask = 0xffffff,
2475 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2476 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2477 #else
2478 /* this entry seems still valid -- i.e. without emu20kx chip */
2479 { PCI_DEVICE(0x1102, 0x0009),
2480 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2481 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2482 #endif
2483 /* CM8888 */
2484 { PCI_DEVICE(0x13f6, 0x5011),
2485 .driver_data = AZX_DRIVER_CMEDIA |
2486 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2487 /* Vortex86MX */
2488 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2489 /* VMware HDAudio */
2490 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2491 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2492 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2493 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2494 .class_mask = 0xffffff,
2495 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2497 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2498 .class_mask = 0xffffff,
2499 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { 0, }
2501 };
2502 MODULE_DEVICE_TABLE(pci, azx_ids);
2503
2504 /* pci_driver definition */
2505 static struct pci_driver azx_driver = {
2506 .name = KBUILD_MODNAME,
2507 .id_table = azx_ids,
2508 .probe = azx_probe,
2509 .remove = azx_remove,
2510 .shutdown = azx_shutdown,
2511 .driver = {
2512 .pm = AZX_PM_OPS,
2513 },
2514 };
2515
2516 module_pci_driver(azx_driver);
Linux with added FPC-III support