dm thin metadata: fix __udivdi3 undefined on 32-bit
[linux/fpc-iii.git] / sound / soc / codecs / adau17x1.c
blob0b9e13eb0a0a58d318ae1aaf4104f808545112a1
1 /*
2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
8 */
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/regmap.h>
24 #include "sigmadsp.h"
25 #include "adau17x1.h"
27 static const char * const adau17x1_capture_mixer_boost_text[] = {
28 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
31 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
32 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
34 static const char * const adau17x1_mic_bias_mode_text[] = {
35 "Normal operation", "High performance",
38 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
39 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
41 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
43 static const struct snd_kcontrol_new adau17x1_controls[] = {
44 SOC_DOUBLE_R_TLV("Digital Capture Volume",
45 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
46 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
47 0, 0xff, 1, adau17x1_digital_tlv),
48 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
49 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
51 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
52 5, 1, 0),
53 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
54 2, 1, 0),
56 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
58 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
61 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
62 struct snd_kcontrol *kcontrol, int event)
64 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
65 struct adau *adau = snd_soc_codec_get_drvdata(codec);
66 int ret;
68 if (SND_SOC_DAPM_EVENT_ON(event)) {
69 adau->pll_regs[5] = 1;
70 } else {
71 adau->pll_regs[5] = 0;
72 /* Bypass the PLL when disabled, otherwise registers will become
73 * inaccessible. */
74 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
75 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
78 /* The PLL register is 6 bytes long and can only be written at once. */
79 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
80 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
82 if (SND_SOC_DAPM_EVENT_ON(event)) {
83 mdelay(5);
84 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
89 return 0;
92 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
93 struct snd_kcontrol *kcontrol, int event)
95 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
96 struct adau *adau = snd_soc_codec_get_drvdata(codec);
99 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to
100 * avoid losing SNR (workaround from ADI). This must be done after
101 * the ADC(s) have been enabled. According to the data sheet, it is
102 * normally illegal to set this bit when the sampling rate is 96 kHz,
103 * but according to ADI it is acceptable for this workaround.
105 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
106 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
107 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
108 ADAU17X1_CONVERTER0_ADOSR, 0);
110 return 0;
113 static const char * const adau17x1_mono_stereo_text[] = {
114 "Stereo",
115 "Mono Left Channel (L+R)",
116 "Mono Right Channel (L+R)",
117 "Mono (L+R)",
120 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
121 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
123 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
124 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
126 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
127 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
128 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
130 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
132 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
134 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
135 0, 0, NULL, 0),
136 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
137 1, 0, NULL, 0),
139 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
140 &adau17x1_dac_mode_mux),
141 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
142 &adau17x1_dac_mode_mux),
144 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
145 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
146 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
147 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
148 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
151 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
152 { "Left Decimator", NULL, "SYSCLK" },
153 { "Right Decimator", NULL, "SYSCLK" },
154 { "Left DAC", NULL, "SYSCLK" },
155 { "Right DAC", NULL, "SYSCLK" },
156 { "Capture", NULL, "SYSCLK" },
157 { "Playback", NULL, "SYSCLK" },
159 { "Left DAC", NULL, "Left DAC Mode Mux" },
160 { "Right DAC", NULL, "Right DAC Mode Mux" },
162 { "Capture", NULL, "AIFCLK" },
163 { "Playback", NULL, "AIFCLK" },
166 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
167 "SYSCLK", NULL, "PLL",
171 * The MUX register for the Capture and Playback MUXs selects either DSP as
172 * source/destination or one of the TDM slots. The TDM slot is selected via
173 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
174 * directly to the DAI interface with this control.
176 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
177 struct snd_ctl_elem_value *ucontrol)
179 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
180 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
181 struct adau *adau = snd_soc_codec_get_drvdata(codec);
182 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
183 struct snd_soc_dapm_update update;
184 unsigned int stream = e->shift_l;
185 unsigned int val, change;
186 int reg;
188 if (ucontrol->value.enumerated.item[0] >= e->items)
189 return -EINVAL;
191 switch (ucontrol->value.enumerated.item[0]) {
192 case 0:
193 val = 0;
194 adau->dsp_bypass[stream] = false;
195 break;
196 default:
197 val = (adau->tdm_slot[stream] * 2) + 1;
198 adau->dsp_bypass[stream] = true;
199 break;
202 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
203 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
204 else
205 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
207 change = snd_soc_test_bits(codec, reg, 0xff, val);
208 if (change) {
209 update.kcontrol = kcontrol;
210 update.mask = 0xff;
211 update.reg = reg;
212 update.val = val;
214 snd_soc_dapm_mux_update_power(dapm, kcontrol,
215 ucontrol->value.enumerated.item[0], e, &update);
218 return change;
221 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
222 struct snd_ctl_elem_value *ucontrol)
224 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
225 struct adau *adau = snd_soc_codec_get_drvdata(codec);
226 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
227 unsigned int stream = e->shift_l;
228 unsigned int reg, val;
229 int ret;
231 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
232 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
233 else
234 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
236 ret = regmap_read(adau->regmap, reg, &val);
237 if (ret)
238 return ret;
240 if (val != 0)
241 val = 1;
242 ucontrol->value.enumerated.item[0] = val;
244 return 0;
247 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
248 const struct snd_kcontrol_new _name = \
249 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
250 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
251 ARRAY_SIZE(_text), _text), \
252 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
254 static const char * const adau17x1_dac_mux_text[] = {
255 "DSP",
256 "AIFIN",
259 static const char * const adau17x1_capture_mux_text[] = {
260 "DSP",
261 "Decimator",
264 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
265 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
267 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
268 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
270 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
271 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
272 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
274 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
275 &adau17x1_dac_mux),
276 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
277 &adau17x1_capture_mux),
280 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
281 { "DAC Playback Mux", "DSP", "DSP" },
282 { "DAC Playback Mux", "AIFIN", "Playback" },
284 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
285 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
286 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
287 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
288 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
289 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
291 { "Capture Mux", "DSP", "DSP" },
292 { "Capture Mux", "Decimator", "Left Decimator" },
293 { "Capture Mux", "Decimator", "Right Decimator" },
295 { "Capture", NULL, "Capture Mux" },
297 { "DSP", NULL, "DSP Siggen" },
299 { "DSP", NULL, "Left Decimator" },
300 { "DSP", NULL, "Right Decimator" },
303 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
304 { "Left DAC Mode Mux", "Stereo", "Playback" },
305 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
306 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
307 { "Right DAC Mode Mux", "Stereo", "Playback" },
308 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
309 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
310 { "Capture", NULL, "Left Decimator" },
311 { "Capture", NULL, "Right Decimator" },
314 bool adau17x1_has_dsp(struct adau *adau)
316 switch (adau->type) {
317 case ADAU1761:
318 case ADAU1381:
319 case ADAU1781:
320 return true;
321 default:
322 return false;
325 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
327 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
328 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
330 struct snd_soc_codec *codec = dai->codec;
331 struct adau *adau = snd_soc_codec_get_drvdata(codec);
332 unsigned int val, div, dsp_div;
333 unsigned int freq;
334 int ret;
336 if (adau->clk_src == ADAU17X1_CLK_SRC_PLL)
337 freq = adau->pll_freq;
338 else
339 freq = adau->sysclk;
341 if (freq % params_rate(params) != 0)
342 return -EINVAL;
344 switch (freq / params_rate(params)) {
345 case 1024: /* fs */
346 div = 0;
347 dsp_div = 1;
348 break;
349 case 6144: /* fs / 6 */
350 div = 1;
351 dsp_div = 6;
352 break;
353 case 4096: /* fs / 4 */
354 div = 2;
355 dsp_div = 5;
356 break;
357 case 3072: /* fs / 3 */
358 div = 3;
359 dsp_div = 4;
360 break;
361 case 2048: /* fs / 2 */
362 div = 4;
363 dsp_div = 3;
364 break;
365 case 1536: /* fs / 1.5 */
366 div = 5;
367 dsp_div = 2;
368 break;
369 case 512: /* fs / 0.5 */
370 div = 6;
371 dsp_div = 0;
372 break;
373 default:
374 return -EINVAL;
377 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
378 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
379 if (adau17x1_has_dsp(adau)) {
380 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
381 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
384 if (adau->sigmadsp) {
385 ret = adau17x1_setup_firmware(adau, params_rate(params));
386 if (ret < 0)
387 return ret;
390 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
391 return 0;
393 switch (params_width(params)) {
394 case 16:
395 val = ADAU17X1_SERIAL_PORT1_DELAY16;
396 break;
397 case 24:
398 val = ADAU17X1_SERIAL_PORT1_DELAY8;
399 break;
400 case 32:
401 val = ADAU17X1_SERIAL_PORT1_DELAY0;
402 break;
403 default:
404 return -EINVAL;
407 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
408 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
411 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
412 int source, unsigned int freq_in, unsigned int freq_out)
414 struct snd_soc_codec *codec = dai->codec;
415 struct adau *adau = snd_soc_codec_get_drvdata(codec);
416 unsigned int r, n, m, i, j;
417 unsigned int div;
418 int ret;
420 if (freq_in < 8000000 || freq_in > 27000000)
421 return -EINVAL;
423 if (!freq_out) {
424 r = 0;
425 n = 0;
426 m = 0;
427 div = 0;
428 } else {
429 if (freq_out % freq_in != 0) {
430 div = DIV_ROUND_UP(freq_in, 13500000);
431 freq_in /= div;
432 r = freq_out / freq_in;
433 i = freq_out % freq_in;
434 j = gcd(i, freq_in);
435 n = i / j;
436 m = freq_in / j;
437 div--;
438 } else {
439 r = freq_out / freq_in;
440 n = 0;
441 m = 0;
442 div = 0;
444 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
445 return -EINVAL;
448 adau->pll_regs[0] = m >> 8;
449 adau->pll_regs[1] = m & 0xff;
450 adau->pll_regs[2] = n >> 8;
451 adau->pll_regs[3] = n & 0xff;
452 adau->pll_regs[4] = (r << 3) | (div << 1);
453 if (m != 0)
454 adau->pll_regs[4] |= 1; /* Fractional mode */
456 /* The PLL register is 6 bytes long and can only be written at once. */
457 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
458 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
459 if (ret)
460 return ret;
462 adau->pll_freq = freq_out;
464 return 0;
467 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
468 int clk_id, unsigned int freq, int dir)
470 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec);
471 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
473 switch (clk_id) {
474 case ADAU17X1_CLK_SRC_MCLK:
475 case ADAU17X1_CLK_SRC_PLL:
476 break;
477 default:
478 return -EINVAL;
481 adau->sysclk = freq;
483 if (adau->clk_src != clk_id) {
484 if (clk_id == ADAU17X1_CLK_SRC_PLL) {
485 snd_soc_dapm_add_routes(dapm,
486 &adau17x1_dapm_pll_route, 1);
487 } else {
488 snd_soc_dapm_del_routes(dapm,
489 &adau17x1_dapm_pll_route, 1);
493 adau->clk_src = clk_id;
495 return 0;
498 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
499 unsigned int fmt)
501 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
502 unsigned int ctrl0, ctrl1;
503 int lrclk_pol;
505 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
506 case SND_SOC_DAIFMT_CBM_CFM:
507 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
508 adau->master = true;
509 break;
510 case SND_SOC_DAIFMT_CBS_CFS:
511 ctrl0 = 0;
512 adau->master = false;
513 break;
514 default:
515 return -EINVAL;
518 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
519 case SND_SOC_DAIFMT_I2S:
520 lrclk_pol = 0;
521 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
522 break;
523 case SND_SOC_DAIFMT_LEFT_J:
524 case SND_SOC_DAIFMT_RIGHT_J:
525 lrclk_pol = 1;
526 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
527 break;
528 case SND_SOC_DAIFMT_DSP_A:
529 lrclk_pol = 1;
530 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
531 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
532 break;
533 case SND_SOC_DAIFMT_DSP_B:
534 lrclk_pol = 1;
535 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
536 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
537 break;
538 default:
539 return -EINVAL;
542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543 case SND_SOC_DAIFMT_NB_NF:
544 break;
545 case SND_SOC_DAIFMT_IB_NF:
546 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
547 break;
548 case SND_SOC_DAIFMT_NB_IF:
549 lrclk_pol = !lrclk_pol;
550 break;
551 case SND_SOC_DAIFMT_IB_IF:
552 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
553 lrclk_pol = !lrclk_pol;
554 break;
555 default:
556 return -EINVAL;
559 if (lrclk_pol)
560 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
562 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
563 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
565 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
567 return 0;
570 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
571 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
573 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
574 unsigned int ser_ctrl0, ser_ctrl1;
575 unsigned int conv_ctrl0, conv_ctrl1;
577 /* I2S mode */
578 if (slots == 0) {
579 slots = 2;
580 rx_mask = 3;
581 tx_mask = 3;
582 slot_width = 32;
585 switch (slots) {
586 case 2:
587 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
588 break;
589 case 4:
590 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
591 break;
592 case 8:
593 if (adau->type == ADAU1361)
594 return -EINVAL;
596 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
597 break;
598 default:
599 return -EINVAL;
602 switch (slot_width * slots) {
603 case 32:
604 if (adau->type == ADAU1761)
605 return -EINVAL;
607 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
608 break;
609 case 64:
610 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
611 break;
612 case 48:
613 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
614 break;
615 case 128:
616 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
617 break;
618 case 256:
619 if (adau->type == ADAU1361)
620 return -EINVAL;
622 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
623 break;
624 default:
625 return -EINVAL;
628 switch (rx_mask) {
629 case 0x03:
630 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
631 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
632 break;
633 case 0x0c:
634 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
635 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
636 break;
637 case 0x30:
638 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
639 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
640 break;
641 case 0xc0:
642 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
643 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
644 break;
645 default:
646 return -EINVAL;
649 switch (tx_mask) {
650 case 0x03:
651 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
652 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
653 break;
654 case 0x0c:
655 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
656 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
657 break;
658 case 0x30:
659 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
660 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
661 break;
662 case 0xc0:
663 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
664 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
665 break;
666 default:
667 return -EINVAL;
670 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
671 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
672 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
673 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
674 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
675 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
676 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
677 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
679 if (!adau17x1_has_dsp(adau))
680 return 0;
682 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
683 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
684 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
687 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
688 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
689 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
692 return 0;
695 static int adau17x1_startup(struct snd_pcm_substream *substream,
696 struct snd_soc_dai *dai)
698 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
700 if (adau->sigmadsp)
701 return sigmadsp_restrict_params(adau->sigmadsp, substream);
703 return 0;
706 const struct snd_soc_dai_ops adau17x1_dai_ops = {
707 .hw_params = adau17x1_hw_params,
708 .set_sysclk = adau17x1_set_dai_sysclk,
709 .set_fmt = adau17x1_set_dai_fmt,
710 .set_pll = adau17x1_set_dai_pll,
711 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
712 .startup = adau17x1_startup,
714 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
716 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
717 enum adau17x1_micbias_voltage micbias)
719 struct adau *adau = snd_soc_codec_get_drvdata(codec);
721 switch (micbias) {
722 case ADAU17X1_MICBIAS_0_90_AVDD:
723 case ADAU17X1_MICBIAS_0_65_AVDD:
724 break;
725 default:
726 return -EINVAL;
729 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
731 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
733 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
735 /* SigmaDSP parameter memory */
736 if (reg < 0x400)
737 return true;
739 return false;
741 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
743 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
745 /* SigmaDSP parameter memory */
746 if (reg < 0x400)
747 return true;
749 switch (reg) {
750 case ADAU17X1_CLOCK_CONTROL:
751 case ADAU17X1_PLL_CONTROL:
752 case ADAU17X1_REC_POWER_MGMT:
753 case ADAU17X1_MICBIAS:
754 case ADAU17X1_SERIAL_PORT0:
755 case ADAU17X1_SERIAL_PORT1:
756 case ADAU17X1_CONVERTER0:
757 case ADAU17X1_CONVERTER1:
758 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
759 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
760 case ADAU17X1_ADC_CONTROL:
761 case ADAU17X1_PLAY_POWER_MGMT:
762 case ADAU17X1_DAC_CONTROL0:
763 case ADAU17X1_DAC_CONTROL1:
764 case ADAU17X1_DAC_CONTROL2:
765 case ADAU17X1_SERIAL_PORT_PAD:
766 case ADAU17X1_CONTROL_PORT_PAD0:
767 case ADAU17X1_CONTROL_PORT_PAD1:
768 case ADAU17X1_DSP_SAMPLING_RATE:
769 case ADAU17X1_SERIAL_INPUT_ROUTE:
770 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
771 case ADAU17X1_DSP_ENABLE:
772 case ADAU17X1_DSP_RUN:
773 case ADAU17X1_SERIAL_SAMPLING_RATE:
774 return true;
775 default:
776 break;
778 return false;
780 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
782 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
784 /* SigmaDSP parameter and program memory */
785 if (reg < 0x4000)
786 return true;
788 switch (reg) {
789 /* The PLL register is 6 bytes long */
790 case ADAU17X1_PLL_CONTROL:
791 case ADAU17X1_PLL_CONTROL + 1:
792 case ADAU17X1_PLL_CONTROL + 2:
793 case ADAU17X1_PLL_CONTROL + 3:
794 case ADAU17X1_PLL_CONTROL + 4:
795 case ADAU17X1_PLL_CONTROL + 5:
796 return true;
797 default:
798 break;
801 return false;
803 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
805 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
807 int ret;
808 int dspsr;
810 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
811 if (ret)
812 return ret;
814 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
815 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
817 ret = sigmadsp_setup(adau->sigmadsp, rate);
818 if (ret) {
819 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
820 return ret;
822 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
824 return 0;
826 EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);
828 int adau17x1_add_widgets(struct snd_soc_codec *codec)
830 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
831 struct adau *adau = snd_soc_codec_get_drvdata(codec);
832 int ret;
834 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
835 ARRAY_SIZE(adau17x1_controls));
836 if (ret)
837 return ret;
838 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
839 ARRAY_SIZE(adau17x1_dapm_widgets));
840 if (ret)
841 return ret;
843 if (adau17x1_has_dsp(adau)) {
844 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
845 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
846 if (ret)
847 return ret;
849 if (!adau->sigmadsp)
850 return 0;
852 ret = sigmadsp_attach(adau->sigmadsp, &codec->component);
853 if (ret) {
854 dev_err(codec->dev, "Failed to attach firmware: %d\n",
855 ret);
856 return ret;
860 return 0;
862 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
864 int adau17x1_add_routes(struct snd_soc_codec *codec)
866 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
867 struct adau *adau = snd_soc_codec_get_drvdata(codec);
868 int ret;
870 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
871 ARRAY_SIZE(adau17x1_dapm_routes));
872 if (ret)
873 return ret;
875 if (adau17x1_has_dsp(adau)) {
876 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
877 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
878 } else {
879 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
880 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
882 return ret;
884 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
886 int adau17x1_resume(struct snd_soc_codec *codec)
888 struct adau *adau = snd_soc_codec_get_drvdata(codec);
890 if (adau->switch_mode)
891 adau->switch_mode(codec->dev);
893 regcache_sync(adau->regmap);
895 return 0;
897 EXPORT_SYMBOL_GPL(adau17x1_resume);
899 int adau17x1_probe(struct device *dev, struct regmap *regmap,
900 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
901 const char *firmware_name)
903 struct adau *adau;
905 if (IS_ERR(regmap))
906 return PTR_ERR(regmap);
908 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
909 if (!adau)
910 return -ENOMEM;
912 adau->regmap = regmap;
913 adau->switch_mode = switch_mode;
914 adau->type = type;
916 dev_set_drvdata(dev, adau);
918 if (firmware_name) {
919 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL,
920 firmware_name);
921 if (IS_ERR(adau->sigmadsp)) {
922 dev_warn(dev, "Could not find firmware file: %ld\n",
923 PTR_ERR(adau->sigmadsp));
924 adau->sigmadsp = NULL;
928 if (switch_mode)
929 switch_mode(dev);
931 return 0;
933 EXPORT_SYMBOL_GPL(adau17x1_probe);
935 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
936 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
937 MODULE_LICENSE("GPL");