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[PATCH] V4L: Makes needlessly global code static
[linux/fpc-iii.git] / drivers / scsi / sata_mv.c
blobab7432a5778e278a7ece69777d253911b365646e
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
90 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
91
92 CRQB_FLAG_READ = (1 << 0),
93 CRQB_TAG_SHIFT = 1,
94 CRQB_CMD_ADDR_SHIFT = 8,
95 CRQB_CMD_CS = (0x2 << 11),
96 CRQB_CMD_LAST = (1 << 15),
97
98 CRPB_FLAG_STATUS_SHIFT = 8,
99
100 EPRD_FLAG_END_OF_TBL = (1 << 31),
101
102 /* PCI interface registers */
103
104 PCI_COMMAND_OFS = 0xc00,
105
106 PCI_MAIN_CMD_STS_OFS = 0xd30,
107 STOP_PCI_MASTER = (1 << 2),
108 PCI_MASTER_EMPTY = (1 << 3),
109 GLOB_SFT_RST = (1 << 4),
110
111 MV_PCI_MODE = 0xd00,
112 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
113 MV_PCI_DISC_TIMER = 0xd04,
114 MV_PCI_MSI_TRIGGER = 0xc38,
115 MV_PCI_SERR_MASK = 0xc28,
116 MV_PCI_XBAR_TMOUT = 0x1d04,
117 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
118 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
119 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
120 MV_PCI_ERR_COMMAND = 0x1d50,
121
122 PCI_IRQ_CAUSE_OFS = 0x1d58,
123 PCI_IRQ_MASK_OFS = 0x1d5c,
124 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
125
126 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
127 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
128 PORT0_ERR = (1 << 0), /* shift by port # */
129 PORT0_DONE = (1 << 1), /* shift by port # */
130 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
131 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
132 PCI_ERR = (1 << 18),
133 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
134 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
135 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
136 GPIO_INT = (1 << 22),
137 SELF_INT = (1 << 23),
138 TWSI_INT = (1 << 24),
139 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
140 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
141 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
142 HC_MAIN_RSVD),
143
144 /* SATAHC registers */
145 HC_CFG_OFS = 0,
146
147 HC_IRQ_CAUSE_OFS = 0x14,
148 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
149 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
150 DEV_IRQ = (1 << 8), /* shift by port # */
151
152 /* Shadow block registers */
153 SHD_BLK_OFS = 0x100,
154 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
155
156 /* SATA registers */
157 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
158 SATA_ACTIVE_OFS = 0x350,
159 PHY_MODE3 = 0x310,
160 PHY_MODE4 = 0x314,
161 PHY_MODE2 = 0x330,
162 MV5_PHY_MODE = 0x74,
163 MV5_LT_MODE = 0x30,
164 MV5_PHY_CTL = 0x0C,
165 SATA_INTERFACE_CTL = 0x050,
166
167 MV_M2_PREAMP_MASK = 0x7e0,
168
169 /* Port registers */
170 EDMA_CFG_OFS = 0,
171 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
172 EDMA_CFG_NCQ = (1 << 5),
173 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
174 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
175 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
176
177 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
178 EDMA_ERR_IRQ_MASK_OFS = 0xc,
179 EDMA_ERR_D_PAR = (1 << 0),
180 EDMA_ERR_PRD_PAR = (1 << 1),
181 EDMA_ERR_DEV = (1 << 2),
182 EDMA_ERR_DEV_DCON = (1 << 3),
183 EDMA_ERR_DEV_CON = (1 << 4),
184 EDMA_ERR_SERR = (1 << 5),
185 EDMA_ERR_SELF_DIS = (1 << 7),
186 EDMA_ERR_BIST_ASYNC = (1 << 8),
187 EDMA_ERR_CRBQ_PAR = (1 << 9),
188 EDMA_ERR_CRPB_PAR = (1 << 10),
189 EDMA_ERR_INTRL_PAR = (1 << 11),
190 EDMA_ERR_IORDY = (1 << 12),
191 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
192 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
193 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
194 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
195 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
196 EDMA_ERR_TRANS_PROTO = (1 << 31),
197 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
198 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
199 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
200 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
201 EDMA_ERR_LNK_DATA_RX |
202 EDMA_ERR_LNK_DATA_TX |
203 EDMA_ERR_TRANS_PROTO),
204
205 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
206 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
207
208 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
209 EDMA_REQ_Q_PTR_SHIFT = 5,
210
211 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
212 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
213 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
214 EDMA_RSP_Q_PTR_SHIFT = 3,
215
216 EDMA_CMD_OFS = 0x28,
217 EDMA_EN = (1 << 0),
218 EDMA_DS = (1 << 1),
219 ATA_RST = (1 << 2),
220
221 EDMA_IORDY_TMOUT = 0x34,
222 EDMA_ARB_CFG = 0x38,
223
224 /* Host private flags (hp_flags) */
225 MV_HP_FLAG_MSI = (1 << 0),
226 MV_HP_ERRATA_50XXB0 = (1 << 1),
227 MV_HP_ERRATA_50XXB2 = (1 << 2),
228 MV_HP_ERRATA_60X1B2 = (1 << 3),
229 MV_HP_ERRATA_60X1C0 = (1 << 4),
230 MV_HP_50XX = (1 << 5),
231
232 /* Port private flags (pp_flags) */
233 MV_PP_FLAG_EDMA_EN = (1 << 0),
234 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
235 };
236
237 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
238 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
239
240 enum {
241 /* Our DMA boundary is determined by an ePRD being unable to handle
242 * anything larger than 64KB
243 */
244 MV_DMA_BOUNDARY = 0xffffU,
245
246 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
247
248 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
249 };
250
251 enum chip_type {
252 chip_504x,
253 chip_508x,
254 chip_5080,
255 chip_604x,
256 chip_608x,
257 };
258
259 /* Command ReQuest Block: 32B */
260 struct mv_crqb {
261 u32 sg_addr;
262 u32 sg_addr_hi;
263 u16 ctrl_flags;
264 u16 ata_cmd[11];
265 };
266
267 /* Command ResPonse Block: 8B */
268 struct mv_crpb {
269 u16 id;
270 u16 flags;
271 u32 tmstmp;
272 };
273
274 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
275 struct mv_sg {
276 u32 addr;
277 u32 flags_size;
278 u32 addr_hi;
279 u32 reserved;
280 };
281
282 struct mv_port_priv {
283 struct mv_crqb *crqb;
284 dma_addr_t crqb_dma;
285 struct mv_crpb *crpb;
286 dma_addr_t crpb_dma;
287 struct mv_sg *sg_tbl;
288 dma_addr_t sg_tbl_dma;
289
290 unsigned req_producer; /* cp of req_in_ptr */
291 unsigned rsp_consumer; /* cp of rsp_out_ptr */
292 u32 pp_flags;
293 };
294
295 struct mv_port_signal {
296 u32 amps;
297 u32 pre;
298 };
299
300 struct mv_host_priv;
301 struct mv_hw_ops {
302 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
303 unsigned int port);
304 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
305 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
306 void __iomem *mmio);
307 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
308 unsigned int n_hc);
309 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
310 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
311 };
312
313 struct mv_host_priv {
314 u32 hp_flags;
315 struct mv_port_signal signal[8];
316 const struct mv_hw_ops *ops;
317 };
318
319 static void mv_irq_clear(struct ata_port *ap);
320 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
321 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
322 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
323 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
324 static void mv_phy_reset(struct ata_port *ap);
325 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
326 static void mv_host_stop(struct ata_host_set *host_set);
327 static int mv_port_start(struct ata_port *ap);
328 static void mv_port_stop(struct ata_port *ap);
329 static void mv_qc_prep(struct ata_queued_cmd *qc);
330 static int mv_qc_issue(struct ata_queued_cmd *qc);
331 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
332 struct pt_regs *regs);
333 static void mv_eng_timeout(struct ata_port *ap);
334 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
335
336 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
337 unsigned int port);
338 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
339 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
340 void __iomem *mmio);
341 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
342 unsigned int n_hc);
343 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
344 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
345
346 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
347 unsigned int port);
348 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
349 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
350 void __iomem *mmio);
351 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
352 unsigned int n_hc);
353 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
354 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
355 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
356 unsigned int port_no);
357 static void mv_stop_and_reset(struct ata_port *ap);
358
359 static struct scsi_host_template mv_sht = {
360 .module = THIS_MODULE,
361 .name = DRV_NAME,
362 .ioctl = ata_scsi_ioctl,
363 .queuecommand = ata_scsi_queuecmd,
364 .eh_strategy_handler = ata_scsi_error,
365 .can_queue = MV_USE_Q_DEPTH,
366 .this_id = ATA_SHT_THIS_ID,
367 .sg_tablesize = MV_MAX_SG_CT / 2,
368 .max_sectors = ATA_MAX_SECTORS,
369 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
370 .emulated = ATA_SHT_EMULATED,
371 .use_clustering = ATA_SHT_USE_CLUSTERING,
372 .proc_name = DRV_NAME,
373 .dma_boundary = MV_DMA_BOUNDARY,
374 .slave_configure = ata_scsi_slave_config,
375 .bios_param = ata_std_bios_param,
376 .ordered_flush = 1,
377 };
378
379 static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
387
388 .phy_reset = mv_phy_reset,
389
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
392
393 .eng_timeout = mv_eng_timeout,
394
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
397
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
400
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
404 };
405
406 static const struct ata_port_operations mv6_ops = {
407 .port_disable = ata_port_disable,
408
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
414
415 .phy_reset = mv_phy_reset,
416
417 .qc_prep = mv_qc_prep,
418 .qc_issue = mv_qc_issue,
419
420 .eng_timeout = mv_eng_timeout,
421
422 .irq_handler = mv_interrupt,
423 .irq_clear = mv_irq_clear,
424
425 .scr_read = mv_scr_read,
426 .scr_write = mv_scr_write,
427
428 .port_start = mv_port_start,
429 .port_stop = mv_port_stop,
430 .host_stop = mv_host_stop,
431 };
432
433 static struct ata_port_info mv_port_info[] = {
434 { /* chip_504x */
435 .sht = &mv_sht,
436 .host_flags = MV_COMMON_FLAGS,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .udma_mask = 0x7f, /* udma0-6 */
439 .port_ops = &mv5_ops,
440 },
441 { /* chip_508x */
442 .sht = &mv_sht,
443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
444 .pio_mask = 0x1f, /* pio0-4 */
445 .udma_mask = 0x7f, /* udma0-6 */
446 .port_ops = &mv5_ops,
447 },
448 { /* chip_5080 */
449 .sht = &mv_sht,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
454 },
455 { /* chip_604x */
456 .sht = &mv_sht,
457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .udma_mask = 0x7f, /* udma0-6 */
460 .port_ops = &mv6_ops,
461 },
462 { /* chip_608x */
463 .sht = &mv_sht,
464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
465 MV_FLAG_DUAL_HC),
466 .pio_mask = 0x1f, /* pio0-4 */
467 .udma_mask = 0x7f, /* udma0-6 */
468 .port_ops = &mv6_ops,
469 },
470 };
471
472 static const struct pci_device_id mv_pci_tbl[] = {
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
477
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
482
483 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
484 {} /* terminate list */
485 };
486
487 static struct pci_driver mv_pci_driver = {
488 .name = DRV_NAME,
489 .id_table = mv_pci_tbl,
490 .probe = mv_init_one,
491 .remove = ata_pci_remove_one,
492 };
493
494 static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
501 };
502
503 static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
510 };
511
512 /*
513 * Functions
514 */
515
516 static inline void writelfl(unsigned long data, void __iomem *addr)
517 {
518 writel(data, addr);
519 (void) readl(addr); /* flush to avoid PCI posted write */
520 }
521
522 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
523 {
524 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
525 }
526
527 static inline unsigned int mv_hc_from_port(unsigned int port)
528 {
529 return port >> MV_PORT_HC_SHIFT;
530 }
531
532 static inline unsigned int mv_hardport_from_port(unsigned int port)
533 {
534 return port & MV_PORT_MASK;
535 }
536
537 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
538 unsigned int port)
539 {
540 return mv_hc_base(base, mv_hc_from_port(port));
541 }
542
543 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
544 {
545 return mv_hc_base_from_port(base, port) +
546 MV_SATAHC_ARBTR_REG_SZ +
547 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
548 }
549
550 static inline void __iomem *mv_ap_base(struct ata_port *ap)
551 {
552 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
553 }
554
555 static inline int mv_get_hc_count(unsigned long host_flags)
556 {
557 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
558 }
559
560 static void mv_irq_clear(struct ata_port *ap)
561 {
562 }
563
564 /**
565 * mv_start_dma - Enable eDMA engine
566 * @base: port base address
567 * @pp: port private data
568 *
569 * Verify the local cache of the eDMA state is accurate with an
570 * assert.
571 *
572 * LOCKING:
573 * Inherited from caller.
574 */
575 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
576 {
577 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
578 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
579 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
580 }
581 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
582 }
583
584 /**
585 * mv_stop_dma - Disable eDMA engine
586 * @ap: ATA channel to manipulate
587 *
588 * Verify the local cache of the eDMA state is accurate with an
589 * assert.
590 *
591 * LOCKING:
592 * Inherited from caller.
593 */
594 static void mv_stop_dma(struct ata_port *ap)
595 {
596 void __iomem *port_mmio = mv_ap_base(ap);
597 struct mv_port_priv *pp = ap->private_data;
598 u32 reg;
599 int i;
600
601 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
602 /* Disable EDMA if active. The disable bit auto clears.
603 */
604 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
605 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
606 } else {
607 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
608 }
609
610 /* now properly wait for the eDMA to stop */
611 for (i = 1000; i > 0; i--) {
612 reg = readl(port_mmio + EDMA_CMD_OFS);
613 if (!(EDMA_EN & reg)) {
614 break;
615 }
616 udelay(100);
617 }
618
619 if (EDMA_EN & reg) {
620 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
621 /* FIXME: Consider doing a reset here to recover */
622 }
623 }
624
625 #ifdef ATA_DEBUG
626 static void mv_dump_mem(void __iomem *start, unsigned bytes)
627 {
628 int b, w;
629 for (b = 0; b < bytes; ) {
630 DPRINTK("%p: ", start + b);
631 for (w = 0; b < bytes && w < 4; w++) {
632 printk("%08x ",readl(start + b));
633 b += sizeof(u32);
634 }
635 printk("\n");
636 }
637 }
638 #endif
639
640 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
641 {
642 #ifdef ATA_DEBUG
643 int b, w;
644 u32 dw;
645 for (b = 0; b < bytes; ) {
646 DPRINTK("%02x: ", b);
647 for (w = 0; b < bytes && w < 4; w++) {
648 (void) pci_read_config_dword(pdev,b,&dw);
649 printk("%08x ",dw);
650 b += sizeof(u32);
651 }
652 printk("\n");
653 }
654 #endif
655 }
656 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
657 struct pci_dev *pdev)
658 {
659 #ifdef ATA_DEBUG
660 void __iomem *hc_base = mv_hc_base(mmio_base,
661 port >> MV_PORT_HC_SHIFT);
662 void __iomem *port_base;
663 int start_port, num_ports, p, start_hc, num_hcs, hc;
664
665 if (0 > port) {
666 start_hc = start_port = 0;
667 num_ports = 8; /* shld be benign for 4 port devs */
668 num_hcs = 2;
669 } else {
670 start_hc = port >> MV_PORT_HC_SHIFT;
671 start_port = port;
672 num_ports = num_hcs = 1;
673 }
674 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
675 num_ports > 1 ? num_ports - 1 : start_port);
676
677 if (NULL != pdev) {
678 DPRINTK("PCI config space regs:\n");
679 mv_dump_pci_cfg(pdev, 0x68);
680 }
681 DPRINTK("PCI regs:\n");
682 mv_dump_mem(mmio_base+0xc00, 0x3c);
683 mv_dump_mem(mmio_base+0xd00, 0x34);
684 mv_dump_mem(mmio_base+0xf00, 0x4);
685 mv_dump_mem(mmio_base+0x1d00, 0x6c);
686 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
687 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
688 DPRINTK("HC regs (HC %i):\n", hc);
689 mv_dump_mem(hc_base, 0x1c);
690 }
691 for (p = start_port; p < start_port + num_ports; p++) {
692 port_base = mv_port_base(mmio_base, p);
693 DPRINTK("EDMA regs (port %i):\n",p);
694 mv_dump_mem(port_base, 0x54);
695 DPRINTK("SATA regs (port %i):\n",p);
696 mv_dump_mem(port_base+0x300, 0x60);
697 }
698 #endif
699 }
700
701 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
702 {
703 unsigned int ofs;
704
705 switch (sc_reg_in) {
706 case SCR_STATUS:
707 case SCR_CONTROL:
708 case SCR_ERROR:
709 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
710 break;
711 case SCR_ACTIVE:
712 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
713 break;
714 default:
715 ofs = 0xffffffffU;
716 break;
717 }
718 return ofs;
719 }
720
721 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
722 {
723 unsigned int ofs = mv_scr_offset(sc_reg_in);
724
725 if (0xffffffffU != ofs) {
726 return readl(mv_ap_base(ap) + ofs);
727 } else {
728 return (u32) ofs;
729 }
730 }
731
732 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
733 {
734 unsigned int ofs = mv_scr_offset(sc_reg_in);
735
736 if (0xffffffffU != ofs) {
737 writelfl(val, mv_ap_base(ap) + ofs);
738 }
739 }
740
741 /**
742 * mv_host_stop - Host specific cleanup/stop routine.
743 * @host_set: host data structure
744 *
745 * Disable ints, cleanup host memory, call general purpose
746 * host_stop.
747 *
748 * LOCKING:
749 * Inherited from caller.
750 */
751 static void mv_host_stop(struct ata_host_set *host_set)
752 {
753 struct mv_host_priv *hpriv = host_set->private_data;
754 struct pci_dev *pdev = to_pci_dev(host_set->dev);
755
756 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
757 pci_disable_msi(pdev);
758 } else {
759 pci_intx(pdev, 0);
760 }
761 kfree(hpriv);
762 ata_host_stop(host_set);
763 }
764
765 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
766 {
767 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
768 }
769
770 /**
771 * mv_port_start - Port specific init/start routine.
772 * @ap: ATA channel to manipulate
773 *
774 * Allocate and point to DMA memory, init port private memory,
775 * zero indices.
776 *
777 * LOCKING:
778 * Inherited from caller.
779 */
780 static int mv_port_start(struct ata_port *ap)
781 {
782 struct device *dev = ap->host_set->dev;
783 struct mv_port_priv *pp;
784 void __iomem *port_mmio = mv_ap_base(ap);
785 void *mem;
786 dma_addr_t mem_dma;
787 int rc = -ENOMEM;
788
789 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
790 if (!pp)
791 goto err_out;
792 memset(pp, 0, sizeof(*pp));
793
794 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
795 GFP_KERNEL);
796 if (!mem)
797 goto err_out_pp;
798 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
799
800 rc = ata_pad_alloc(ap, dev);
801 if (rc)
802 goto err_out_priv;
803
804 /* First item in chunk of DMA memory:
805 * 32-slot command request table (CRQB), 32 bytes each in size
806 */
807 pp->crqb = mem;
808 pp->crqb_dma = mem_dma;
809 mem += MV_CRQB_Q_SZ;
810 mem_dma += MV_CRQB_Q_SZ;
811
812 /* Second item:
813 * 32-slot command response table (CRPB), 8 bytes each in size
814 */
815 pp->crpb = mem;
816 pp->crpb_dma = mem_dma;
817 mem += MV_CRPB_Q_SZ;
818 mem_dma += MV_CRPB_Q_SZ;
819
820 /* Third item:
821 * Table of scatter-gather descriptors (ePRD), 16 bytes each
822 */
823 pp->sg_tbl = mem;
824 pp->sg_tbl_dma = mem_dma;
825
826 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
827 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
828
829 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
830 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
831 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
832
833 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
834 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835
836 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
837 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
838 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
839
840 pp->req_producer = pp->rsp_consumer = 0;
841
842 /* Don't turn on EDMA here...do it before DMA commands only. Else
843 * we'll be unable to send non-data, PIO, etc due to restricted access
844 * to shadow regs.
845 */
846 ap->private_data = pp;
847 return 0;
848
849 err_out_priv:
850 mv_priv_free(pp, dev);
851 err_out_pp:
852 kfree(pp);
853 err_out:
854 return rc;
855 }
856
857 /**
858 * mv_port_stop - Port specific cleanup/stop routine.
859 * @ap: ATA channel to manipulate
860 *
861 * Stop DMA, cleanup port memory.
862 *
863 * LOCKING:
864 * This routine uses the host_set lock to protect the DMA stop.
865 */
866 static void mv_port_stop(struct ata_port *ap)
867 {
868 struct device *dev = ap->host_set->dev;
869 struct mv_port_priv *pp = ap->private_data;
870 unsigned long flags;
871
872 spin_lock_irqsave(&ap->host_set->lock, flags);
873 mv_stop_dma(ap);
874 spin_unlock_irqrestore(&ap->host_set->lock, flags);
875
876 ap->private_data = NULL;
877 ata_pad_free(ap, dev);
878 mv_priv_free(pp, dev);
879 kfree(pp);
880 }
881
882 /**
883 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
884 * @qc: queued command whose SG list to source from
885 *
886 * Populate the SG list and mark the last entry.
887 *
888 * LOCKING:
889 * Inherited from caller.
890 */
891 static void mv_fill_sg(struct ata_queued_cmd *qc)
892 {
893 struct mv_port_priv *pp = qc->ap->private_data;
894 unsigned int i = 0;
895 struct scatterlist *sg;
896
897 ata_for_each_sg(sg, qc) {
898 dma_addr_t addr;
899 u32 sg_len, len, offset;
900
901 addr = sg_dma_address(sg);
902 sg_len = sg_dma_len(sg);
903
904 while (sg_len) {
905 offset = addr & MV_DMA_BOUNDARY;
906 len = sg_len;
907 if ((offset + sg_len) > 0x10000)
908 len = 0x10000 - offset;
909
910 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
911 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
912 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
913
914 sg_len -= len;
915 addr += len;
916
917 if (!sg_len && ata_sg_is_last(sg, qc))
918 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
919
920 i++;
921 }
922 }
923 }
924
925 static inline unsigned mv_inc_q_index(unsigned *index)
926 {
927 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
928 return *index;
929 }
930
931 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
932 {
933 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
934 (last ? CRQB_CMD_LAST : 0);
935 }
936
937 /**
938 * mv_qc_prep - Host specific command preparation.
939 * @qc: queued command to prepare
940 *
941 * This routine simply redirects to the general purpose routine
942 * if command is not DMA. Else, it handles prep of the CRQB
943 * (command request block), does some sanity checking, and calls
944 * the SG load routine.
945 *
946 * LOCKING:
947 * Inherited from caller.
948 */
949 static void mv_qc_prep(struct ata_queued_cmd *qc)
950 {
951 struct ata_port *ap = qc->ap;
952 struct mv_port_priv *pp = ap->private_data;
953 u16 *cw;
954 struct ata_taskfile *tf;
955 u16 flags = 0;
956
957 if (ATA_PROT_DMA != qc->tf.protocol) {
958 return;
959 }
960
961 /* the req producer index should be the same as we remember it */
962 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
963 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
964 pp->req_producer);
965
966 /* Fill in command request block
967 */
968 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
969 flags |= CRQB_FLAG_READ;
970 }
971 assert(MV_MAX_Q_DEPTH > qc->tag);
972 flags |= qc->tag << CRQB_TAG_SHIFT;
973
974 pp->crqb[pp->req_producer].sg_addr =
975 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
976 pp->crqb[pp->req_producer].sg_addr_hi =
977 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
978 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
979
980 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
981 tf = &qc->tf;
982
983 /* Sadly, the CRQB cannot accomodate all registers--there are
984 * only 11 bytes...so we must pick and choose required
985 * registers based on the command. So, we drop feature and
986 * hob_feature for [RW] DMA commands, but they are needed for
987 * NCQ. NCQ will drop hob_nsect.
988 */
989 switch (tf->command) {
990 case ATA_CMD_READ:
991 case ATA_CMD_READ_EXT:
992 case ATA_CMD_WRITE:
993 case ATA_CMD_WRITE_EXT:
994 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
995 break;
996 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
997 case ATA_CMD_FPDMA_READ:
998 case ATA_CMD_FPDMA_WRITE:
999 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1000 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1001 break;
1002 #endif /* FIXME: remove this line when NCQ added */
1003 default:
1004 /* The only other commands EDMA supports in non-queued and
1005 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1006 * of which are defined/used by Linux. If we get here, this
1007 * driver needs work.
1008 *
1009 * FIXME: modify libata to give qc_prep a return value and
1010 * return error here.
1011 */
1012 BUG_ON(tf->command);
1013 break;
1014 }
1015 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1016 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1017 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1018 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1019 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1020 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1021 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1022 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1023 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1024
1025 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1026 return;
1027 }
1028 mv_fill_sg(qc);
1029 }
1030
1031 /**
1032 * mv_qc_issue - Initiate a command to the host
1033 * @qc: queued command to start
1034 *
1035 * This routine simply redirects to the general purpose routine
1036 * if command is not DMA. Else, it sanity checks our local
1037 * caches of the request producer/consumer indices then enables
1038 * DMA and bumps the request producer index.
1039 *
1040 * LOCKING:
1041 * Inherited from caller.
1042 */
1043 static int mv_qc_issue(struct ata_queued_cmd *qc)
1044 {
1045 void __iomem *port_mmio = mv_ap_base(qc->ap);
1046 struct mv_port_priv *pp = qc->ap->private_data;
1047 u32 in_ptr;
1048
1049 if (ATA_PROT_DMA != qc->tf.protocol) {
1050 /* We're about to send a non-EDMA capable command to the
1051 * port. Turn off EDMA so there won't be problems accessing
1052 * shadow block, etc registers.
1053 */
1054 mv_stop_dma(qc->ap);
1055 return ata_qc_issue_prot(qc);
1056 }
1057
1058 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1059
1060 /* the req producer index should be the same as we remember it */
1061 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1062 pp->req_producer);
1063 /* until we do queuing, the queue should be empty at this point */
1064 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1065 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1066 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1067
1068 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1069
1070 mv_start_dma(port_mmio, pp);
1071
1072 /* and write the request in pointer to kick the EDMA to life */
1073 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1074 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1075 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1076
1077 return 0;
1078 }
1079
1080 /**
1081 * mv_get_crpb_status - get status from most recently completed cmd
1082 * @ap: ATA channel to manipulate
1083 *
1084 * This routine is for use when the port is in DMA mode, when it
1085 * will be using the CRPB (command response block) method of
1086 * returning command completion information. We assert indices
1087 * are good, grab status, and bump the response consumer index to
1088 * prove that we're up to date.
1089 *
1090 * LOCKING:
1091 * Inherited from caller.
1092 */
1093 static u8 mv_get_crpb_status(struct ata_port *ap)
1094 {
1095 void __iomem *port_mmio = mv_ap_base(ap);
1096 struct mv_port_priv *pp = ap->private_data;
1097 u32 out_ptr;
1098
1099 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1100
1101 /* the response consumer index should be the same as we remember it */
1102 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1103 pp->rsp_consumer);
1104
1105 /* increment our consumer index... */
1106 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1107
1108 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1109 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1110 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1111 pp->rsp_consumer);
1112
1113 /* write out our inc'd consumer index so EDMA knows we're caught up */
1114 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1115 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1116 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1117
1118 /* Return ATA status register for completed CRPB */
1119 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1120 }
1121
1122 /**
1123 * mv_err_intr - Handle error interrupts on the port
1124 * @ap: ATA channel to manipulate
1125 *
1126 * In most cases, just clear the interrupt and move on. However,
1127 * some cases require an eDMA reset, which is done right before
1128 * the COMRESET in mv_phy_reset(). The SERR case requires a
1129 * clear of pending errors in the SATA SERROR register. Finally,
1130 * if the port disabled DMA, update our cached copy to match.
1131 *
1132 * LOCKING:
1133 * Inherited from caller.
1134 */
1135 static void mv_err_intr(struct ata_port *ap)
1136 {
1137 void __iomem *port_mmio = mv_ap_base(ap);
1138 u32 edma_err_cause, serr = 0;
1139
1140 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1141
1142 if (EDMA_ERR_SERR & edma_err_cause) {
1143 serr = scr_read(ap, SCR_ERROR);
1144 scr_write_flush(ap, SCR_ERROR, serr);
1145 }
1146 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1147 struct mv_port_priv *pp = ap->private_data;
1148 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1149 }
1150 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1151 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1152
1153 /* Clear EDMA now that SERR cleanup done */
1154 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1155
1156 /* check for fatal here and recover if needed */
1157 if (EDMA_ERR_FATAL & edma_err_cause) {
1158 mv_stop_and_reset(ap);
1159 }
1160 }
1161
1162 /**
1163 * mv_host_intr - Handle all interrupts on the given host controller
1164 * @host_set: host specific structure
1165 * @relevant: port error bits relevant to this host controller
1166 * @hc: which host controller we're to look at
1167 *
1168 * Read then write clear the HC interrupt status then walk each
1169 * port connected to the HC and see if it needs servicing. Port
1170 * success ints are reported in the HC interrupt status reg, the
1171 * port error ints are reported in the higher level main
1172 * interrupt status register and thus are passed in via the
1173 * 'relevant' argument.
1174 *
1175 * LOCKING:
1176 * Inherited from caller.
1177 */
1178 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1179 unsigned int hc)
1180 {
1181 void __iomem *mmio = host_set->mmio_base;
1182 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1183 struct ata_port *ap;
1184 struct ata_queued_cmd *qc;
1185 u32 hc_irq_cause;
1186 int shift, port, port0, hard_port, handled;
1187 unsigned int err_mask;
1188 u8 ata_status = 0;
1189
1190 if (hc == 0) {
1191 port0 = 0;
1192 } else {
1193 port0 = MV_PORTS_PER_HC;
1194 }
1195
1196 /* we'll need the HC success int register in most cases */
1197 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1198 if (hc_irq_cause) {
1199 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1200 }
1201
1202 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1203 hc,relevant,hc_irq_cause);
1204
1205 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1206 ap = host_set->ports[port];
1207 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1208 handled = 0; /* ensure ata_status is set if handled++ */
1209
1210 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1211 /* new CRPB on the queue; just one at a time until NCQ
1212 */
1213 ata_status = mv_get_crpb_status(ap);
1214 handled++;
1215 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1216 /* received ATA IRQ; read the status reg to clear INTRQ
1217 */
1218 ata_status = readb((void __iomem *)
1219 ap->ioaddr.status_addr);
1220 handled++;
1221 }
1222
1223 if (ap &&
1224 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1225 continue;
1226
1227 err_mask = ac_err_mask(ata_status);
1228
1229 shift = port << 1; /* (port * 2) */
1230 if (port >= MV_PORTS_PER_HC) {
1231 shift++; /* skip bit 8 in the HC Main IRQ reg */
1232 }
1233 if ((PORT0_ERR << shift) & relevant) {
1234 mv_err_intr(ap);
1235 err_mask |= AC_ERR_OTHER;
1236 handled++;
1237 }
1238
1239 if (handled && ap) {
1240 qc = ata_qc_from_tag(ap, ap->active_tag);
1241 if (NULL != qc) {
1242 VPRINTK("port %u IRQ found for qc, "
1243 "ata_status 0x%x\n", port,ata_status);
1244 /* mark qc status appropriately */
1245 if (!(qc->tf.ctl & ATA_NIEN))
1246 ata_qc_complete(qc, err_mask);
1247 }
1248 }
1249 }
1250 VPRINTK("EXIT\n");
1251 }
1252
1253 /**
1254 * mv_interrupt -
1255 * @irq: unused
1256 * @dev_instance: private data; in this case the host structure
1257 * @regs: unused
1258 *
1259 * Read the read only register to determine if any host
1260 * controllers have pending interrupts. If so, call lower level
1261 * routine to handle. Also check for PCI errors which are only
1262 * reported here.
1263 *
1264 * LOCKING:
1265 * This routine holds the host_set lock while processing pending
1266 * interrupts.
1267 */
1268 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1269 struct pt_regs *regs)
1270 {
1271 struct ata_host_set *host_set = dev_instance;
1272 unsigned int hc, handled = 0, n_hcs;
1273 void __iomem *mmio = host_set->mmio_base;
1274 u32 irq_stat;
1275
1276 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1277
1278 /* check the cases where we either have nothing pending or have read
1279 * a bogus register value which can indicate HW removal or PCI fault
1280 */
1281 if (!irq_stat || (0xffffffffU == irq_stat)) {
1282 return IRQ_NONE;
1283 }
1284
1285 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1286 spin_lock(&host_set->lock);
1287
1288 for (hc = 0; hc < n_hcs; hc++) {
1289 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1290 if (relevant) {
1291 mv_host_intr(host_set, relevant, hc);
1292 handled++;
1293 }
1294 }
1295 if (PCI_ERR & irq_stat) {
1296 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1297 readl(mmio + PCI_IRQ_CAUSE_OFS));
1298
1299 DPRINTK("All regs @ PCI error\n");
1300 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1301
1302 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1303 handled++;
1304 }
1305 spin_unlock(&host_set->lock);
1306
1307 return IRQ_RETVAL(handled);
1308 }
1309
1310 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1311 {
1312 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1313 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1314
1315 return hc_mmio + ofs;
1316 }
1317
1318 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1319 {
1320 unsigned int ofs;
1321
1322 switch (sc_reg_in) {
1323 case SCR_STATUS:
1324 case SCR_ERROR:
1325 case SCR_CONTROL:
1326 ofs = sc_reg_in * sizeof(u32);
1327 break;
1328 default:
1329 ofs = 0xffffffffU;
1330 break;
1331 }
1332 return ofs;
1333 }
1334
1335 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1336 {
1337 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1338 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1339
1340 if (ofs != 0xffffffffU)
1341 return readl(mmio + ofs);
1342 else
1343 return (u32) ofs;
1344 }
1345
1346 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1347 {
1348 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1349 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1350
1351 if (ofs != 0xffffffffU)
1352 writelfl(val, mmio + ofs);
1353 }
1354
1355 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1356 {
1357 u8 rev_id;
1358 int early_5080;
1359
1360 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1361
1362 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1363
1364 if (!early_5080) {
1365 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1366 tmp |= (1 << 0);
1367 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1368 }
1369
1370 mv_reset_pci_bus(pdev, mmio);
1371 }
1372
1373 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1374 {
1375 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1376 }
1377
1378 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1379 void __iomem *mmio)
1380 {
1381 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1382 u32 tmp;
1383
1384 tmp = readl(phy_mmio + MV5_PHY_MODE);
1385
1386 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1387 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1388 }
1389
1390 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1391 {
1392 u32 tmp;
1393
1394 writel(0, mmio + MV_GPIO_PORT_CTL);
1395
1396 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1397
1398 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1399 tmp |= ~(1 << 0);
1400 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1401 }
1402
1403 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1404 unsigned int port)
1405 {
1406 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1407 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1408 u32 tmp;
1409 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1410
1411 if (fix_apm_sq) {
1412 tmp = readl(phy_mmio + MV5_LT_MODE);
1413 tmp |= (1 << 19);
1414 writel(tmp, phy_mmio + MV5_LT_MODE);
1415
1416 tmp = readl(phy_mmio + MV5_PHY_CTL);
1417 tmp &= ~0x3;
1418 tmp |= 0x1;
1419 writel(tmp, phy_mmio + MV5_PHY_CTL);
1420 }
1421
1422 tmp = readl(phy_mmio + MV5_PHY_MODE);
1423 tmp &= ~mask;
1424 tmp |= hpriv->signal[port].pre;
1425 tmp |= hpriv->signal[port].amps;
1426 writel(tmp, phy_mmio + MV5_PHY_MODE);
1427 }
1428
1429
1430 #undef ZERO
1431 #define ZERO(reg) writel(0, port_mmio + (reg))
1432 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1433 unsigned int port)
1434 {
1435 void __iomem *port_mmio = mv_port_base(mmio, port);
1436
1437 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1438
1439 mv_channel_reset(hpriv, mmio, port);
1440
1441 ZERO(0x028); /* command */
1442 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1443 ZERO(0x004); /* timer */
1444 ZERO(0x008); /* irq err cause */
1445 ZERO(0x00c); /* irq err mask */
1446 ZERO(0x010); /* rq bah */
1447 ZERO(0x014); /* rq inp */
1448 ZERO(0x018); /* rq outp */
1449 ZERO(0x01c); /* respq bah */
1450 ZERO(0x024); /* respq outp */
1451 ZERO(0x020); /* respq inp */
1452 ZERO(0x02c); /* test control */
1453 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1454 }
1455 #undef ZERO
1456
1457 #define ZERO(reg) writel(0, hc_mmio + (reg))
1458 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1459 unsigned int hc)
1460 {
1461 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1462 u32 tmp;
1463
1464 ZERO(0x00c);
1465 ZERO(0x010);
1466 ZERO(0x014);
1467 ZERO(0x018);
1468
1469 tmp = readl(hc_mmio + 0x20);
1470 tmp &= 0x1c1c1c1c;
1471 tmp |= 0x03030303;
1472 writel(tmp, hc_mmio + 0x20);
1473 }
1474 #undef ZERO
1475
1476 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1477 unsigned int n_hc)
1478 {
1479 unsigned int hc, port;
1480
1481 for (hc = 0; hc < n_hc; hc++) {
1482 for (port = 0; port < MV_PORTS_PER_HC; port++)
1483 mv5_reset_hc_port(hpriv, mmio,
1484 (hc * MV_PORTS_PER_HC) + port);
1485
1486 mv5_reset_one_hc(hpriv, mmio, hc);
1487 }
1488
1489 return 0;
1490 }
1491
1492 #undef ZERO
1493 #define ZERO(reg) writel(0, mmio + (reg))
1494 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1495 {
1496 u32 tmp;
1497
1498 tmp = readl(mmio + MV_PCI_MODE);
1499 tmp &= 0xff00ffff;
1500 writel(tmp, mmio + MV_PCI_MODE);
1501
1502 ZERO(MV_PCI_DISC_TIMER);
1503 ZERO(MV_PCI_MSI_TRIGGER);
1504 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1505 ZERO(HC_MAIN_IRQ_MASK_OFS);
1506 ZERO(MV_PCI_SERR_MASK);
1507 ZERO(PCI_IRQ_CAUSE_OFS);
1508 ZERO(PCI_IRQ_MASK_OFS);
1509 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1510 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1511 ZERO(MV_PCI_ERR_ATTRIBUTE);
1512 ZERO(MV_PCI_ERR_COMMAND);
1513 }
1514 #undef ZERO
1515
1516 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1517 {
1518 u32 tmp;
1519
1520 mv5_reset_flash(hpriv, mmio);
1521
1522 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1523 tmp &= 0x3;
1524 tmp |= (1 << 5) | (1 << 6);
1525 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1526 }
1527
1528 /**
1529 * mv6_reset_hc - Perform the 6xxx global soft reset
1530 * @mmio: base address of the HBA
1531 *
1532 * This routine only applies to 6xxx parts.
1533 *
1534 * LOCKING:
1535 * Inherited from caller.
1536 */
1537 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1538 unsigned int n_hc)
1539 {
1540 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1541 int i, rc = 0;
1542 u32 t;
1543
1544 /* Following procedure defined in PCI "main command and status
1545 * register" table.
1546 */
1547 t = readl(reg);
1548 writel(t | STOP_PCI_MASTER, reg);
1549
1550 for (i = 0; i < 1000; i++) {
1551 udelay(1);
1552 t = readl(reg);
1553 if (PCI_MASTER_EMPTY & t) {
1554 break;
1555 }
1556 }
1557 if (!(PCI_MASTER_EMPTY & t)) {
1558 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1559 rc = 1;
1560 goto done;
1561 }
1562
1563 /* set reset */
1564 i = 5;
1565 do {
1566 writel(t | GLOB_SFT_RST, reg);
1567 t = readl(reg);
1568 udelay(1);
1569 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1570
1571 if (!(GLOB_SFT_RST & t)) {
1572 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1573 rc = 1;
1574 goto done;
1575 }
1576
1577 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1578 i = 5;
1579 do {
1580 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1581 t = readl(reg);
1582 udelay(1);
1583 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1584
1585 if (GLOB_SFT_RST & t) {
1586 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1587 rc = 1;
1588 }
1589 done:
1590 return rc;
1591 }
1592
1593 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1594 void __iomem *mmio)
1595 {
1596 void __iomem *port_mmio;
1597 u32 tmp;
1598
1599 tmp = readl(mmio + MV_RESET_CFG);
1600 if ((tmp & (1 << 0)) == 0) {
1601 hpriv->signal[idx].amps = 0x7 << 8;
1602 hpriv->signal[idx].pre = 0x1 << 5;
1603 return;
1604 }
1605
1606 port_mmio = mv_port_base(mmio, idx);
1607 tmp = readl(port_mmio + PHY_MODE2);
1608
1609 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1610 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1611 }
1612
1613 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1614 {
1615 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1616 }
1617
1618 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1619 unsigned int port)
1620 {
1621 void __iomem *port_mmio = mv_port_base(mmio, port);
1622
1623 u32 hp_flags = hpriv->hp_flags;
1624 int fix_phy_mode2 =
1625 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1626 int fix_phy_mode4 =
1627 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1628 u32 m2, tmp;
1629
1630 if (fix_phy_mode2) {
1631 m2 = readl(port_mmio + PHY_MODE2);
1632 m2 &= ~(1 << 16);
1633 m2 |= (1 << 31);
1634 writel(m2, port_mmio + PHY_MODE2);
1635
1636 udelay(200);
1637
1638 m2 = readl(port_mmio + PHY_MODE2);
1639 m2 &= ~((1 << 16) | (1 << 31));
1640 writel(m2, port_mmio + PHY_MODE2);
1641
1642 udelay(200);
1643 }
1644
1645 /* who knows what this magic does */
1646 tmp = readl(port_mmio + PHY_MODE3);
1647 tmp &= ~0x7F800000;
1648 tmp |= 0x2A800000;
1649 writel(tmp, port_mmio + PHY_MODE3);
1650
1651 if (fix_phy_mode4) {
1652 u32 m4;
1653
1654 m4 = readl(port_mmio + PHY_MODE4);
1655
1656 if (hp_flags & MV_HP_ERRATA_60X1B2)
1657 tmp = readl(port_mmio + 0x310);
1658
1659 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1660
1661 writel(m4, port_mmio + PHY_MODE4);
1662
1663 if (hp_flags & MV_HP_ERRATA_60X1B2)
1664 writel(tmp, port_mmio + 0x310);
1665 }
1666
1667 /* Revert values of pre-emphasis and signal amps to the saved ones */
1668 m2 = readl(port_mmio + PHY_MODE2);
1669
1670 m2 &= ~MV_M2_PREAMP_MASK;
1671 m2 |= hpriv->signal[port].amps;
1672 m2 |= hpriv->signal[port].pre;
1673 m2 &= ~(1 << 16);
1674
1675 writel(m2, port_mmio + PHY_MODE2);
1676 }
1677
1678 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1679 unsigned int port_no)
1680 {
1681 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1682
1683 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1684
1685 if (IS_60XX(hpriv)) {
1686 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1687 ifctl |= (1 << 12) | (1 << 7);
1688 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1689 }
1690
1691 udelay(25); /* allow reset propagation */
1692
1693 /* Spec never mentions clearing the bit. Marvell's driver does
1694 * clear the bit, however.
1695 */
1696 writelfl(0, port_mmio + EDMA_CMD_OFS);
1697
1698 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1699
1700 if (IS_50XX(hpriv))
1701 mdelay(1);
1702 }
1703
1704 static void mv_stop_and_reset(struct ata_port *ap)
1705 {
1706 struct mv_host_priv *hpriv = ap->host_set->private_data;
1707 void __iomem *mmio = ap->host_set->mmio_base;
1708
1709 mv_stop_dma(ap);
1710
1711 mv_channel_reset(hpriv, mmio, ap->port_no);
1712
1713 __mv_phy_reset(ap, 0);
1714 }
1715
1716 static inline void __msleep(unsigned int msec, int can_sleep)
1717 {
1718 if (can_sleep)
1719 msleep(msec);
1720 else
1721 mdelay(msec);
1722 }
1723
1724 /**
1725 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1726 * @ap: ATA channel to manipulate
1727 *
1728 * Part of this is taken from __sata_phy_reset and modified to
1729 * not sleep since this routine gets called from interrupt level.
1730 *
1731 * LOCKING:
1732 * Inherited from caller. This is coded to safe to call at
1733 * interrupt level, i.e. it does not sleep.
1734 */
1735 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1736 {
1737 struct mv_port_priv *pp = ap->private_data;
1738 struct mv_host_priv *hpriv = ap->host_set->private_data;
1739 void __iomem *port_mmio = mv_ap_base(ap);
1740 struct ata_taskfile tf;
1741 struct ata_device *dev = &ap->device[0];
1742 unsigned long timeout;
1743 int retry = 5;
1744 u32 sstatus;
1745
1746 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1747
1748 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1749 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1750 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1751
1752 /* Issue COMRESET via SControl */
1753 comreset_retry:
1754 scr_write_flush(ap, SCR_CONTROL, 0x301);
1755 __msleep(1, can_sleep);
1756
1757 scr_write_flush(ap, SCR_CONTROL, 0x300);
1758 __msleep(20, can_sleep);
1759
1760 timeout = jiffies + msecs_to_jiffies(200);
1761 do {
1762 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1763 if ((sstatus == 3) || (sstatus == 0))
1764 break;
1765
1766 __msleep(1, can_sleep);
1767 } while (time_before(jiffies, timeout));
1768
1769 /* work around errata */
1770 if (IS_60XX(hpriv) &&
1771 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1772 (retry-- > 0))
1773 goto comreset_retry;
1774
1775 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1776 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1777 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1778
1779 if (sata_dev_present(ap)) {
1780 ata_port_probe(ap);
1781 } else {
1782 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1783 ap->id, scr_read(ap, SCR_STATUS));
1784 ata_port_disable(ap);
1785 return;
1786 }
1787 ap->cbl = ATA_CBL_SATA;
1788
1789 /* even after SStatus reflects that device is ready,
1790 * it seems to take a while for link to be fully
1791 * established (and thus Status no longer 0x80/0x7F),
1792 * so we poll a bit for that, here.
1793 */
1794 retry = 20;
1795 while (1) {
1796 u8 drv_stat = ata_check_status(ap);
1797 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1798 break;
1799 __msleep(500, can_sleep);
1800 if (retry-- <= 0)
1801 break;
1802 }
1803
1804 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1805 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1806 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1807 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1808
1809 dev->class = ata_dev_classify(&tf);
1810 if (!ata_dev_present(dev)) {
1811 VPRINTK("Port disabled post-sig: No device present.\n");
1812 ata_port_disable(ap);
1813 }
1814
1815 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1816
1817 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1818
1819 VPRINTK("EXIT\n");
1820 }
1821
1822 static void mv_phy_reset(struct ata_port *ap)
1823 {
1824 __mv_phy_reset(ap, 1);
1825 }
1826
1827 /**
1828 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1829 * @ap: ATA channel to manipulate
1830 *
1831 * Intent is to clear all pending error conditions, reset the
1832 * chip/bus, fail the command, and move on.
1833 *
1834 * LOCKING:
1835 * This routine holds the host_set lock while failing the command.
1836 */
1837 static void mv_eng_timeout(struct ata_port *ap)
1838 {
1839 struct ata_queued_cmd *qc;
1840 unsigned long flags;
1841
1842 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1843 DPRINTK("All regs @ start of eng_timeout\n");
1844 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1845 to_pci_dev(ap->host_set->dev));
1846
1847 qc = ata_qc_from_tag(ap, ap->active_tag);
1848 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1849 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1850 &qc->scsicmd->cmnd);
1851
1852 mv_err_intr(ap);
1853 mv_stop_and_reset(ap);
1854
1855 if (!qc) {
1856 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1857 ap->id);
1858 } else {
1859 /* hack alert! We cannot use the supplied completion
1860 * function from inside the ->eh_strategy_handler() thread.
1861 * libata is the only user of ->eh_strategy_handler() in
1862 * any kernel, so the default scsi_done() assumes it is
1863 * not being called from the SCSI EH.
1864 */
1865 spin_lock_irqsave(&ap->host_set->lock, flags);
1866 qc->scsidone = scsi_finish_command;
1867 ata_qc_complete(qc, AC_ERR_OTHER);
1868 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1869 }
1870 }
1871
1872 /**
1873 * mv_port_init - Perform some early initialization on a single port.
1874 * @port: libata data structure storing shadow register addresses
1875 * @port_mmio: base address of the port
1876 *
1877 * Initialize shadow register mmio addresses, clear outstanding
1878 * interrupts on the port, and unmask interrupts for the future
1879 * start of the port.
1880 *
1881 * LOCKING:
1882 * Inherited from caller.
1883 */
1884 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1885 {
1886 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1887 unsigned serr_ofs;
1888
1889 /* PIO related setup
1890 */
1891 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1892 port->error_addr =
1893 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1894 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1895 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1896 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1897 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1898 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1899 port->status_addr =
1900 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1901 /* special case: control/altstatus doesn't have ATA_REG_ address */
1902 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1903
1904 /* unused: */
1905 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1906
1907 /* Clear any currently outstanding port interrupt conditions */
1908 serr_ofs = mv_scr_offset(SCR_ERROR);
1909 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1910 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1911
1912 /* unmask all EDMA error interrupts */
1913 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1914
1915 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1916 readl(port_mmio + EDMA_CFG_OFS),
1917 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1918 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1919 }
1920
1921 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1922 unsigned int board_idx)
1923 {
1924 u8 rev_id;
1925 u32 hp_flags = hpriv->hp_flags;
1926
1927 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1928
1929 switch(board_idx) {
1930 case chip_5080:
1931 hpriv->ops = &mv5xxx_ops;
1932 hp_flags |= MV_HP_50XX;
1933
1934 switch (rev_id) {
1935 case 0x1:
1936 hp_flags |= MV_HP_ERRATA_50XXB0;
1937 break;
1938 case 0x3:
1939 hp_flags |= MV_HP_ERRATA_50XXB2;
1940 break;
1941 default:
1942 dev_printk(KERN_WARNING, &pdev->dev,
1943 "Applying 50XXB2 workarounds to unknown rev\n");
1944 hp_flags |= MV_HP_ERRATA_50XXB2;
1945 break;
1946 }
1947 break;
1948
1949 case chip_504x:
1950 case chip_508x:
1951 hpriv->ops = &mv5xxx_ops;
1952 hp_flags |= MV_HP_50XX;
1953
1954 switch (rev_id) {
1955 case 0x0:
1956 hp_flags |= MV_HP_ERRATA_50XXB0;
1957 break;
1958 case 0x3:
1959 hp_flags |= MV_HP_ERRATA_50XXB2;
1960 break;
1961 default:
1962 dev_printk(KERN_WARNING, &pdev->dev,
1963 "Applying B2 workarounds to unknown rev\n");
1964 hp_flags |= MV_HP_ERRATA_50XXB2;
1965 break;
1966 }
1967 break;
1968
1969 case chip_604x:
1970 case chip_608x:
1971 hpriv->ops = &mv6xxx_ops;
1972
1973 switch (rev_id) {
1974 case 0x7:
1975 hp_flags |= MV_HP_ERRATA_60X1B2;
1976 break;
1977 case 0x9:
1978 hp_flags |= MV_HP_ERRATA_60X1C0;
1979 break;
1980 default:
1981 dev_printk(KERN_WARNING, &pdev->dev,
1982 "Applying B2 workarounds to unknown rev\n");
1983 hp_flags |= MV_HP_ERRATA_60X1B2;
1984 break;
1985 }
1986 break;
1987
1988 default:
1989 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1990 return 1;
1991 }
1992
1993 hpriv->hp_flags = hp_flags;
1994
1995 return 0;
1996 }
1997
1998 /**
1999 * mv_init_host - Perform some early initialization of the host.
2000 * @pdev: host PCI device
2001 * @probe_ent: early data struct representing the host
2002 *
2003 * If possible, do an early global reset of the host. Then do
2004 * our port init and clear/unmask all/relevant host interrupts.
2005 *
2006 * LOCKING:
2007 * Inherited from caller.
2008 */
2009 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2010 unsigned int board_idx)
2011 {
2012 int rc = 0, n_hc, port, hc;
2013 void __iomem *mmio = probe_ent->mmio_base;
2014 struct mv_host_priv *hpriv = probe_ent->private_data;
2015
2016 /* global interrupt mask */
2017 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2018
2019 rc = mv_chip_id(pdev, hpriv, board_idx);
2020 if (rc)
2021 goto done;
2022
2023 n_hc = mv_get_hc_count(probe_ent->host_flags);
2024 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2025
2026 for (port = 0; port < probe_ent->n_ports; port++)
2027 hpriv->ops->read_preamp(hpriv, port, mmio);
2028
2029 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2030 if (rc)
2031 goto done;
2032
2033 hpriv->ops->reset_flash(hpriv, mmio);
2034 hpriv->ops->reset_bus(pdev, mmio);
2035 hpriv->ops->enable_leds(hpriv, mmio);
2036
2037 for (port = 0; port < probe_ent->n_ports; port++) {
2038 if (IS_60XX(hpriv)) {
2039 void __iomem *port_mmio = mv_port_base(mmio, port);
2040
2041 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2042 ifctl |= (1 << 12);
2043 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2044 }
2045
2046 hpriv->ops->phy_errata(hpriv, mmio, port);
2047 }
2048
2049 for (port = 0; port < probe_ent->n_ports; port++) {
2050 void __iomem *port_mmio = mv_port_base(mmio, port);
2051 mv_port_init(&probe_ent->port[port], port_mmio);
2052 }
2053
2054 for (hc = 0; hc < n_hc; hc++) {
2055 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2056
2057 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2058 "(before clear)=0x%08x\n", hc,
2059 readl(hc_mmio + HC_CFG_OFS),
2060 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2061
2062 /* Clear any currently outstanding hc interrupt conditions */
2063 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2064 }
2065
2066 /* Clear any currently outstanding host interrupt conditions */
2067 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2068
2069 /* and unmask interrupt generation for host regs */
2070 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2071 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2072
2073 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2074 "PCI int cause/mask=0x%08x/0x%08x\n",
2075 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2076 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2077 readl(mmio + PCI_IRQ_CAUSE_OFS),
2078 readl(mmio + PCI_IRQ_MASK_OFS));
2079
2080 done:
2081 return rc;
2082 }
2083
2084 /**
2085 * mv_print_info - Dump key info to kernel log for perusal.
2086 * @probe_ent: early data struct representing the host
2087 *
2088 * FIXME: complete this.
2089 *
2090 * LOCKING:
2091 * Inherited from caller.
2092 */
2093 static void mv_print_info(struct ata_probe_ent *probe_ent)
2094 {
2095 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2096 struct mv_host_priv *hpriv = probe_ent->private_data;
2097 u8 rev_id, scc;
2098 const char *scc_s;
2099
2100 /* Use this to determine the HW stepping of the chip so we know
2101 * what errata to workaround
2102 */
2103 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2104
2105 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2106 if (scc == 0)
2107 scc_s = "SCSI";
2108 else if (scc == 0x01)
2109 scc_s = "RAID";
2110 else
2111 scc_s = "unknown";
2112
2113 dev_printk(KERN_INFO, &pdev->dev,
2114 "%u slots %u ports %s mode IRQ via %s\n",
2115 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2116 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2117 }
2118
2119 /**
2120 * mv_init_one - handle a positive probe of a Marvell host
2121 * @pdev: PCI device found
2122 * @ent: PCI device ID entry for the matched host
2123 *
2124 * LOCKING:
2125 * Inherited from caller.
2126 */
2127 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2128 {
2129 static int printed_version = 0;
2130 struct ata_probe_ent *probe_ent = NULL;
2131 struct mv_host_priv *hpriv;
2132 unsigned int board_idx = (unsigned int)ent->driver_data;
2133 void __iomem *mmio_base;
2134 int pci_dev_busy = 0, rc;
2135
2136 if (!printed_version++)
2137 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2138
2139 rc = pci_enable_device(pdev);
2140 if (rc) {
2141 return rc;
2142 }
2143
2144 rc = pci_request_regions(pdev, DRV_NAME);
2145 if (rc) {
2146 pci_dev_busy = 1;
2147 goto err_out;
2148 }
2149
2150 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2151 if (probe_ent == NULL) {
2152 rc = -ENOMEM;
2153 goto err_out_regions;
2154 }
2155
2156 memset(probe_ent, 0, sizeof(*probe_ent));
2157 probe_ent->dev = pci_dev_to_dev(pdev);
2158 INIT_LIST_HEAD(&probe_ent->node);
2159
2160 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2161 if (mmio_base == NULL) {
2162 rc = -ENOMEM;
2163 goto err_out_free_ent;
2164 }
2165
2166 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2167 if (!hpriv) {
2168 rc = -ENOMEM;
2169 goto err_out_iounmap;
2170 }
2171 memset(hpriv, 0, sizeof(*hpriv));
2172
2173 probe_ent->sht = mv_port_info[board_idx].sht;
2174 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2175 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2176 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2177 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2178
2179 probe_ent->irq = pdev->irq;
2180 probe_ent->irq_flags = SA_SHIRQ;
2181 probe_ent->mmio_base = mmio_base;
2182 probe_ent->private_data = hpriv;
2183
2184 /* initialize adapter */
2185 rc = mv_init_host(pdev, probe_ent, board_idx);
2186 if (rc) {
2187 goto err_out_hpriv;
2188 }
2189
2190 /* Enable interrupts */
2191 if (pci_enable_msi(pdev) == 0) {
2192 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2193 } else {
2194 pci_intx(pdev, 1);
2195 }
2196
2197 mv_dump_pci_cfg(pdev, 0x68);
2198 mv_print_info(probe_ent);
2199
2200 if (ata_device_add(probe_ent) == 0) {
2201 rc = -ENODEV; /* No devices discovered */
2202 goto err_out_dev_add;
2203 }
2204
2205 kfree(probe_ent);
2206 return 0;
2207
2208 err_out_dev_add:
2209 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2210 pci_disable_msi(pdev);
2211 } else {
2212 pci_intx(pdev, 0);
2213 }
2214 err_out_hpriv:
2215 kfree(hpriv);
2216 err_out_iounmap:
2217 pci_iounmap(pdev, mmio_base);
2218 err_out_free_ent:
2219 kfree(probe_ent);
2220 err_out_regions:
2221 pci_release_regions(pdev);
2222 err_out:
2223 if (!pci_dev_busy) {
2224 pci_disable_device(pdev);
2225 }
2226
2227 return rc;
2228 }
2229
2230 static int __init mv_init(void)
2231 {
2232 return pci_module_init(&mv_pci_driver);
2233 }
2234
2235 static void __exit mv_exit(void)
2236 {
2237 pci_unregister_driver(&mv_pci_driver);
2238 }
2239
2240 MODULE_AUTHOR("Brett Russ");
2241 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2242 MODULE_LICENSE("GPL");
2243 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2244 MODULE_VERSION(DRV_VERSION);
2245
2246 module_init(mv_init);
2247 module_exit(mv_exit);
Linux with added FPC-III support