arch/arm/mm/cache-aurora-l2.h

   1 /*
   2  * AURORA shared L2 cache controller support
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Yehuda Yitschak <yehuday@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
  15 #define __ASM_ARM_HARDWARE_AURORA_L2_H
  16
  17 #define AURORA_SYNC_REG             0x700
  18 #define AURORA_RANGE_BASE_ADDR_REG  0x720
  19 #define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
  20 #define AURORA_INVAL_RANGE_REG      0x774
  21 #define AURORA_CLEAN_RANGE_REG      0x7b4
  22 #define AURORA_FLUSH_RANGE_REG      0x7f4
  23
  24 #define AURORA_ACR_REPLACEMENT_OFFSET       27
  25 #define AURORA_ACR_REPLACEMENT_MASK          \
  26         (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
  27 #define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
  28         (0 << AURORA_ACR_REPLACEMENT_OFFSET)
  29 #define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
  30         (1 << AURORA_ACR_REPLACEMENT_OFFSET)
  31 #define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
  32         (3 << AURORA_ACR_REPLACEMENT_OFFSET)
  33
  34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET    0
  35 #define AURORA_ACR_FORCE_WRITE_POLICY_MASK      \
  36         (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
  37 #define AURORA_ACR_FORCE_WRITE_POLICY_DIS       \
  38         (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
  39 #define AURORA_ACR_FORCE_WRITE_BACK_POLICY      \
  40         (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
  41 #define AURORA_ACR_FORCE_WRITE_THRO_POLICY      \
  42         (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
  43
  44 #define MAX_RANGE_SIZE          1024
  45
  46 #define AURORA_WAY_SIZE_SHIFT   2
  47
  48 #define AURORA_CTRL_FW          0x100
  49
  50 /* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
  51  * the distinction between a number coming from hardware and a number
  52  * coming from the device tree */
  53 #define AURORA_CACHE_ID        0x100
  54
  55 #endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */