arch/arm/plat-samsung/include/plat/cpu-freq-core.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2006-2009 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C CPU frequency scaling support - core support
   8  */
   9
  10 #include <plat/cpu-freq.h>
  11
  12 struct seq_file;
  13
  14 #define MAX_BANKS (8)
  15 #define S3C2412_MAX_IO  (8)
  16
  17 /**
  18  * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
  19  * @bankcon: The cached version of settings in this structure.
  20  * @tacp:
  21  * @tacs: Time from address valid to nCS asserted.
  22  * @tcos: Time from nCS asserted to nOE or nWE asserted.
  23  * @tacc: Time that nOE or nWE is asserted.
  24  * @tcoh: Time nCS is held after nOE or nWE are released.
  25  * @tcah: Time address is held for after
  26  * @nwait_en: Whether nWAIT is enabled for this bank.
  27  *
  28  * This structure represents the IO timings for a S3C2410 style IO bank
  29  * used by the CPU frequency support if it needs to change the settings
  30  * of the IO.
  31  */
  32 struct s3c2410_iobank_timing {
  33         unsigned long   bankcon;
  34         unsigned int    tacp;
  35         unsigned int    tacs;
  36         unsigned int    tcos;
  37         unsigned int    tacc;
  38         unsigned int    tcoh;           /* nCS hold after nOE/nWE */
  39         unsigned int    tcah;           /* Address hold after nCS */
  40         unsigned char   nwait_en;       /* nWait enabled for bank. */
  41 };
  42
  43 /**
  44  * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
  45  * @idcy: The idle cycle time between transactions.
  46  * @wstrd: nCS release to end of read cycle.
  47  * @wstwr: nCS release to end of write cycle.
  48  * @wstoen: nCS assertion to nOE assertion time.
  49  * @wstwen: nCS assertion to nWE assertion time.
  50  * @wstbrd: Burst ready delay.
  51  * @smbidcyr: Register cache for smbidcyr value.
  52  * @smbwstrd: Register cache for smbwstrd value.
  53  * @smbwstwr: Register cache for smbwstwr value.
  54  * @smbwstoen: Register cache for smbwstoen value.
  55  * @smbwstwen: Register cache for smbwstwen value.
  56  * @smbwstbrd: Register cache for smbwstbrd value.
  57  *
  58  * Timing information for a IO bank on an S3C2412 or similar system which
  59  * uses a PL093 block.
  60  */
  61 struct s3c2412_iobank_timing {
  62         unsigned int    idcy;
  63         unsigned int    wstrd;
  64         unsigned int    wstwr;
  65         unsigned int    wstoen;
  66         unsigned int    wstwen;
  67         unsigned int    wstbrd;
  68
  69         /* register cache */
  70         unsigned char   smbidcyr;
  71         unsigned char   smbwstrd;
  72         unsigned char   smbwstwr;
  73         unsigned char   smbwstoen;
  74         unsigned char   smbwstwen;
  75         unsigned char   smbwstbrd;
  76 };
  77
  78 union s3c_iobank {
  79         struct s3c2410_iobank_timing    *io_2410;
  80         struct s3c2412_iobank_timing    *io_2412;
  81 };
  82
  83 /**
  84  * struct s3c_iotimings - Chip IO timings holder
  85  * @bank: The timings for each IO bank.
  86  */
  87 struct s3c_iotimings {
  88         union s3c_iobank        bank[MAX_BANKS];
  89 };
  90
  91 /**
  92  * struct s3c_plltab - PLL table information.
  93  * @vals: List of PLL values.
  94  * @size: Size of the PLL table @vals.
  95  */
  96 struct s3c_plltab {
  97         struct s3c_pllval       *vals;
  98         int                      size;
  99 };
 100
 101 /**
 102  * struct s3c_cpufreq_config - current cpu frequency configuration
 103  * @freq: The current settings for the core clocks.
 104  * @max: Maxium settings, derived from core, board and user settings.
 105  * @pll: The PLL table entry for the current PLL settings.
 106  * @divs: The divisor settings for the core clocks.
 107  * @info: The current core driver information.
 108  * @board: The information for the board we are running on.
 109  * @lock_pll: Set if the PLL settings cannot be changed.
 110  *
 111  * This is for the core drivers that need to know information about
 112  * the current settings and values. It should not be needed by any
 113  * device drivers.
 114 */
 115 struct s3c_cpufreq_config {
 116         struct s3c_freq         freq;
 117         struct s3c_freq         max;
 118         struct clk              *mpll;
 119         struct cpufreq_frequency_table pll;
 120         struct s3c_clkdivs      divs;
 121         struct s3c_cpufreq_info *info;  /* for core, not drivers */
 122         struct s3c_cpufreq_board *board;
 123
 124         unsigned int    lock_pll:1;
 125 };
 126
 127 /**
 128  * struct s3c_cpufreq_info - Information for the CPU frequency driver.
 129  * @name: The name of this implementation.
 130  * @max: The maximum frequencies for the system.
 131  * @latency: Transition latency to give to cpufreq.
 132  * @locktime_m: The lock-time in uS for the MPLL.
 133  * @locktime_u: The lock-time in uS for the UPLL.
 134  * @locttime_bits: The number of bits each LOCKTIME field.
 135  * @need_pll: Set if this driver needs to change the PLL values to achieve
 136  *      any frequency changes. This is really only need by devices like the
 137  *      S3C2410 where there is no or limited divider between the PLL and the
 138  *      ARMCLK.
 139  * @get_iotiming: Get the current IO timing data, mainly for use at start.
 140  * @set_iotiming: Update the IO timings from the cached copies calculated
 141  *      from the @calc_iotiming entry when changing the frequency.
 142  * @calc_iotiming: Calculate and update the cached copies of the IO timings
 143  *      from the newly calculated frequencies.
 144  * @calc_freqtable: Calculate (fill in) the given frequency table from the
 145  *      current frequency configuration. If the table passed in is NULL,
 146  *      then the return is the number of elements to be filled for allocation
 147  *      of the table.
 148  * @set_refresh: Set the memory refresh configuration.
 149  * @set_fvco: Set the PLL frequencies.
 150  * @set_divs: Update the clock divisors.
 151  * @calc_divs: Calculate the clock divisors.
 152  */
 153 struct s3c_cpufreq_info {
 154         const char              *name;
 155         struct s3c_freq         max;
 156
 157         unsigned int            latency;
 158
 159         unsigned int            locktime_m;
 160         unsigned int            locktime_u;
 161         unsigned char           locktime_bits;
 162
 163         unsigned int            need_pll:1;
 164
 165         /* driver routines */
 166
 167         int             (*get_iotiming)(struct s3c_cpufreq_config *cfg,
 168                                         struct s3c_iotimings *timings);
 169
 170         void            (*set_iotiming)(struct s3c_cpufreq_config *cfg,
 171                                         struct s3c_iotimings *timings);
 172
 173         int             (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
 174                                          struct s3c_iotimings *timings);
 175
 176         int             (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
 177                                           struct cpufreq_frequency_table *t,
 178                                           size_t table_size);
 179
 180         void            (*debug_io_show)(struct seq_file *seq,
 181                                          struct s3c_cpufreq_config *cfg,
 182                                          union s3c_iobank *iob);
 183
 184         void            (*set_refresh)(struct s3c_cpufreq_config *cfg);
 185         void            (*set_fvco)(struct s3c_cpufreq_config *cfg);
 186         void            (*set_divs)(struct s3c_cpufreq_config *cfg);
 187         int             (*calc_divs)(struct s3c_cpufreq_config *cfg);
 188 };
 189
 190 extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
 191
 192 extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
 193                                unsigned int plls_no);
 194
 195 /* exports and utilities for debugfs */
 196 extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
 197 extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
 198
 199 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
 200 #define s3c_cpufreq_debugfs_call(x) x
 201 #else
 202 #define s3c_cpufreq_debugfs_call(x) NULL
 203 #endif
 204
 205 /* Useful utility functions. */
 206
 207 extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
 208
 209 /* S3C2410 and compatible exported functions */
 210
 211 extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
 212 extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
 213
 214 #ifdef CONFIG_S3C2410_IOTIMING
 215 extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
 216                                      struct s3c_cpufreq_config *cfg,
 217                                      union s3c_iobank *iob);
 218
 219 extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
 220                                  struct s3c_iotimings *iot);
 221
 222 extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
 223                                 struct s3c_iotimings *timings);
 224
 225 extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
 226                                  struct s3c_iotimings *iot);
 227 #else
 228 #define s3c2410_iotiming_debugfs NULL
 229 #define s3c2410_iotiming_calc NULL
 230 #define s3c2410_iotiming_get NULL
 231 #define s3c2410_iotiming_set NULL
 232 #endif /* CONFIG_S3C2410_IOTIMING */
 233
 234 /* S3C2412 compatible routines */
 235
 236 #ifdef CONFIG_S3C2412_IOTIMING
 237 extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
 238                                      struct s3c_cpufreq_config *cfg,
 239                                      union s3c_iobank *iob);
 240
 241 extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
 242                                 struct s3c_iotimings *timings);
 243
 244 extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
 245                                  struct s3c_iotimings *iot);
 246
 247 extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
 248                                  struct s3c_iotimings *iot);
 249 #else
 250 #define s3c2412_iotiming_debugfs NULL
 251 #define s3c2412_iotiming_calc NULL
 252 #define s3c2412_iotiming_get NULL
 253 #define s3c2412_iotiming_set NULL
 254 #endif /* CONFIG_S3C2412_IOTIMING */
 255
 256 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
 257 #define s3c_freq_dbg(x...) printk(KERN_INFO x)
 258 #else
 259 #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
 260 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
 261
 262 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
 263 #define s3c_freq_iodbg(x...) printk(KERN_INFO x)
 264 #else
 265 #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
 266 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
 267
 268 static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
 269                                       int index, size_t table_size,
 270                                       unsigned int freq)
 271 {
 272         if (index < 0)
 273                 return index;
 274
 275         if (table) {
 276                 if (index >= table_size)
 277                         return -ENOMEM;
 278
 279                 s3c_freq_dbg("%s: { %d = %u kHz }\n",
 280                              __func__, index, freq);
 281
 282                 table[index].driver_data = index;
 283                 table[index].frequency = freq;
 284         }
 285
 286         return index + 1;
 287 }