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Merge 5.0-rc6 into driver-core-next
[linux/fpc-iii.git] / drivers / media / dvb-frontends / drxd_hard.c
blob684d428efb0dc2741dbe043728805ec08253f9bd
1 /*
2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3 *
4 * Copyright (C) 2003-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/i2c.h>
27 #include <asm/div64.h>
28
29 #include <media/dvb_frontend.h>
30 #include "drxd.h"
31 #include "drxd_firm.h"
32
33 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
34 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
35
36 #define CHUNK_SIZE 48
37
38 #define DRX_I2C_RMW 0x10
39 #define DRX_I2C_BROADCAST 0x20
40 #define DRX_I2C_CLEARCRC 0x80
41 #define DRX_I2C_SINGLE_MASTER 0xC0
42 #define DRX_I2C_MODEFLAGS 0xC0
43 #define DRX_I2C_FLAGS 0xF0
44
45 #define DEFAULT_LOCK_TIMEOUT 1100
46
47 #define DRX_CHANNEL_AUTO 0
48 #define DRX_CHANNEL_HIGH 1
49 #define DRX_CHANNEL_LOW 2
50
51 #define DRX_LOCK_MPEG 1
52 #define DRX_LOCK_FEC 2
53 #define DRX_LOCK_DEMOD 4
54
55 /****************************************************************************/
56
57 enum CSCDState {
58 CSCD_INIT = 0,
59 CSCD_SET,
60 CSCD_SAVED
61 };
62
63 enum CDrxdState {
64 DRXD_UNINITIALIZED = 0,
65 DRXD_STOPPED,
66 DRXD_STARTED
67 };
68
69 enum AGC_CTRL_MODE {
70 AGC_CTRL_AUTO = 0,
71 AGC_CTRL_USER,
72 AGC_CTRL_OFF
73 };
74
75 enum OperationMode {
76 OM_Default,
77 OM_DVBT_Diversity_Front,
78 OM_DVBT_Diversity_End
79 };
80
81 struct SCfgAgc {
82 enum AGC_CTRL_MODE ctrlMode;
83 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
84 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
85 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
86 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
87 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
88
89 u16 R1;
90 u16 R2;
91 u16 R3;
92 };
93
94 struct SNoiseCal {
95 int cpOpt;
96 short cpNexpOfs;
97 short tdCal2k;
98 short tdCal8k;
99 };
100
101 enum app_env {
102 APPENV_STATIC = 0,
103 APPENV_PORTABLE = 1,
104 APPENV_MOBILE = 2
105 };
106
107 enum EIFFilter {
108 IFFILTER_SAW = 0,
109 IFFILTER_DISCRETE = 1
110 };
111
112 struct drxd_state {
113 struct dvb_frontend frontend;
114 struct dvb_frontend_ops ops;
115 struct dtv_frontend_properties props;
116
117 const struct firmware *fw;
118 struct device *dev;
119
120 struct i2c_adapter *i2c;
121 void *priv;
122 struct drxd_config config;
123
124 int i2c_access;
125 int init_done;
126 struct mutex mutex;
127
128 u8 chip_adr;
129 u16 hi_cfg_timing_div;
130 u16 hi_cfg_bridge_delay;
131 u16 hi_cfg_wakeup_key;
132 u16 hi_cfg_ctrl;
133
134 u16 intermediate_freq;
135 u16 osc_clock_freq;
136
137 enum CSCDState cscd_state;
138 enum CDrxdState drxd_state;
139
140 u16 sys_clock_freq;
141 s16 osc_clock_deviation;
142 u16 expected_sys_clock_freq;
143
144 u16 insert_rs_byte;
145 u16 enable_parallel;
146
147 int operation_mode;
148
149 struct SCfgAgc if_agc_cfg;
150 struct SCfgAgc rf_agc_cfg;
151
152 struct SNoiseCal noise_cal;
153
154 u32 fe_fs_add_incr;
155 u32 org_fe_fs_add_incr;
156 u16 current_fe_if_incr;
157
158 u16 m_FeAgRegAgPwd;
159 u16 m_FeAgRegAgAgcSio;
160
161 u16 m_EcOcRegOcModeLop;
162 u16 m_EcOcRegSncSncLvl;
163 u8 *m_InitAtomicRead;
164 u8 *m_HiI2cPatch;
165
166 u8 *m_ResetCEFR;
167 u8 *m_InitFE_1;
168 u8 *m_InitFE_2;
169 u8 *m_InitCP;
170 u8 *m_InitCE;
171 u8 *m_InitEQ;
172 u8 *m_InitSC;
173 u8 *m_InitEC;
174 u8 *m_ResetECRAM;
175 u8 *m_InitDiversityFront;
176 u8 *m_InitDiversityEnd;
177 u8 *m_DisableDiversity;
178 u8 *m_StartDiversityFront;
179 u8 *m_StartDiversityEnd;
180
181 u8 *m_DiversityDelay8MHZ;
182 u8 *m_DiversityDelay6MHZ;
183
184 u8 *microcode;
185 u32 microcode_length;
186
187 int type_A;
188 int PGA;
189 int diversity;
190 int tuner_mirrors;
191
192 enum app_env app_env_default;
193 enum app_env app_env_diversity;
194
195 };
196
197 /****************************************************************************/
198 /* I2C **********************************************************************/
199 /****************************************************************************/
200
201 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
202 {
203 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
204
205 if (i2c_transfer(adap, &msg, 1) != 1)
206 return -1;
207 return 0;
208 }
209
210 static int i2c_read(struct i2c_adapter *adap,
211 u8 adr, u8 *msg, int len, u8 *answ, int alen)
212 {
213 struct i2c_msg msgs[2] = {
214 {
215 .addr = adr, .flags = 0,
216 .buf = msg, .len = len
217 }, {
218 .addr = adr, .flags = I2C_M_RD,
219 .buf = answ, .len = alen
220 }
221 };
222 if (i2c_transfer(adap, msgs, 2) != 2)
223 return -1;
224 return 0;
225 }
226
227 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
228 {
229 u64 tmp64;
230
231 tmp64 = (u64)a * (u64)b;
232 do_div(tmp64, c);
233
234 return (u32) tmp64;
235 }
236
237 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
238 {
239 u8 adr = state->config.demod_address;
240 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
241 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
242 };
243 u8 mm2[2];
244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
245 return -1;
246 if (data)
247 *data = mm2[0] | (mm2[1] << 8);
248 return mm2[0] | (mm2[1] << 8);
249 }
250
251 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
252 {
253 u8 adr = state->config.demod_address;
254 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
255 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
256 };
257 u8 mm2[4];
258
259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
260 return -1;
261 if (data)
262 *data =
263 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
264 return 0;
265 }
266
267 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
268 {
269 u8 adr = state->config.demod_address;
270 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
271 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
272 data & 0xff, (data >> 8) & 0xff
273 };
274
275 if (i2c_write(state->i2c, adr, mm, 6) < 0)
276 return -1;
277 return 0;
278 }
279
280 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
281 {
282 u8 adr = state->config.demod_address;
283 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
284 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
285 data & 0xff, (data >> 8) & 0xff,
286 (data >> 16) & 0xff, (data >> 24) & 0xff
287 };
288
289 if (i2c_write(state->i2c, adr, mm, 8) < 0)
290 return -1;
291 return 0;
292 }
293
294 static int write_chunk(struct drxd_state *state,
295 u32 reg, u8 *data, u32 len, u8 flags)
296 {
297 u8 adr = state->config.demod_address;
298 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
299 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
300 };
301 int i;
302
303 for (i = 0; i < len; i++)
304 mm[4 + i] = data[i];
305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
306 printk(KERN_ERR "error in write_chunk\n");
307 return -1;
308 }
309 return 0;
310 }
311
312 static int WriteBlock(struct drxd_state *state,
313 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
314 {
315 while (BlockSize > 0) {
316 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
317
318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
319 return -1;
320 pBlock += Chunk;
321 Address += (Chunk >> 1);
322 BlockSize -= Chunk;
323 }
324 return 0;
325 }
326
327 static int WriteTable(struct drxd_state *state, u8 * pTable)
328 {
329 int status = 0;
330
331 if (!pTable)
332 return 0;
333
334 while (!status) {
335 u16 Length;
336 u32 Address = pTable[0] | (pTable[1] << 8) |
337 (pTable[2] << 16) | (pTable[3] << 24);
338
339 if (Address == 0xFFFFFFFF)
340 break;
341 pTable += sizeof(u32);
342
343 Length = pTable[0] | (pTable[1] << 8);
344 pTable += sizeof(u16);
345 if (!Length)
346 break;
347 status = WriteBlock(state, Address, Length * 2, pTable, 0);
348 pTable += (Length * 2);
349 }
350 return status;
351 }
352
353 /****************************************************************************/
354 /****************************************************************************/
355 /****************************************************************************/
356
357 static int ResetCEFR(struct drxd_state *state)
358 {
359 return WriteTable(state, state->m_ResetCEFR);
360 }
361
362 static int InitCP(struct drxd_state *state)
363 {
364 return WriteTable(state, state->m_InitCP);
365 }
366
367 static int InitCE(struct drxd_state *state)
368 {
369 int status;
370 enum app_env AppEnv = state->app_env_default;
371
372 do {
373 status = WriteTable(state, state->m_InitCE);
374 if (status < 0)
375 break;
376
377 if (state->operation_mode == OM_DVBT_Diversity_Front ||
378 state->operation_mode == OM_DVBT_Diversity_End) {
379 AppEnv = state->app_env_diversity;
380 }
381 if (AppEnv == APPENV_STATIC) {
382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
383 if (status < 0)
384 break;
385 } else if (AppEnv == APPENV_PORTABLE) {
386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
387 if (status < 0)
388 break;
389 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
391 if (status < 0)
392 break;
393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
395 if (status < 0)
396 break;
397 }
398
399 /* start ce */
400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
401 if (status < 0)
402 break;
403 } while (0);
404 return status;
405 }
406
407 static int StopOC(struct drxd_state *state)
408 {
409 int status = 0;
410 u16 ocSyncLvl = 0;
411 u16 ocModeLop = state->m_EcOcRegOcModeLop;
412 u16 dtoIncLop = 0;
413 u16 dtoIncHip = 0;
414
415 do {
416 /* Store output configuration */
417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
418 if (status < 0)
419 break;
420 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
421 state->m_EcOcRegSncSncLvl = ocSyncLvl;
422 /* m_EcOcRegOcModeLop = ocModeLop; */
423
424 /* Flush FIFO (byte-boundary) at fixed rate */
425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
426 if (status < 0)
427 break;
428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
429 if (status < 0)
430 break;
431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
432 if (status < 0)
433 break;
434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
435 if (status < 0)
436 break;
437 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
438 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
440 if (status < 0)
441 break;
442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
443 if (status < 0)
444 break;
445
446 msleep(1);
447 /* Output pins to '0' */
448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
449 if (status < 0)
450 break;
451
452 /* Force the OC out of sync */
453 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
455 if (status < 0)
456 break;
457 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
458 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
459 ocModeLop |= 0x2; /* Magically-out-of-sync */
460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
461 if (status < 0)
462 break;
463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
464 if (status < 0)
465 break;
466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
467 if (status < 0)
468 break;
469 } while (0);
470
471 return status;
472 }
473
474 static int StartOC(struct drxd_state *state)
475 {
476 int status = 0;
477
478 do {
479 /* Stop OC */
480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
481 if (status < 0)
482 break;
483
484 /* Restore output configuration */
485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
486 if (status < 0)
487 break;
488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
489 if (status < 0)
490 break;
491
492 /* Output pins active again */
493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
494 if (status < 0)
495 break;
496
497 /* Start OC */
498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
499 if (status < 0)
500 break;
501 } while (0);
502 return status;
503 }
504
505 static int InitEQ(struct drxd_state *state)
506 {
507 return WriteTable(state, state->m_InitEQ);
508 }
509
510 static int InitEC(struct drxd_state *state)
511 {
512 return WriteTable(state, state->m_InitEC);
513 }
514
515 static int InitSC(struct drxd_state *state)
516 {
517 return WriteTable(state, state->m_InitSC);
518 }
519
520 static int InitAtomicRead(struct drxd_state *state)
521 {
522 return WriteTable(state, state->m_InitAtomicRead);
523 }
524
525 static int CorrectSysClockDeviation(struct drxd_state *state);
526
527 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
528 {
529 u16 ScRaRamLock = 0;
530 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
531 SC_RA_RAM_LOCK_FEC__M |
532 SC_RA_RAM_LOCK_DEMOD__M);
533 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
534 SC_RA_RAM_LOCK_DEMOD__M);
535 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
536
537 int status;
538
539 *pLockStatus = 0;
540
541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
542 if (status < 0) {
543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
544 return status;
545 }
546
547 if (state->drxd_state != DRXD_STARTED)
548 return 0;
549
550 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
551 *pLockStatus |= DRX_LOCK_MPEG;
552 CorrectSysClockDeviation(state);
553 }
554
555 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
556 *pLockStatus |= DRX_LOCK_FEC;
557
558 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
559 *pLockStatus |= DRX_LOCK_DEMOD;
560 return 0;
561 }
562
563 /****************************************************************************/
564
565 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
566 {
567 int status;
568
569 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
570 return -1;
571
572 if (cfg->ctrlMode == AGC_CTRL_USER) {
573 do {
574 u16 FeAgRegPm1AgcWri;
575 u16 FeAgRegAgModeLop;
576
577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
578 if (status < 0)
579 break;
580 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
581 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
583 if (status < 0)
584 break;
585
586 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
587 FE_AG_REG_PM1_AGC_WRI__M);
588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
589 if (status < 0)
590 break;
591 } while (0);
592 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
593 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
594 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
595 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
596 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
597 )
598 return -1;
599 do {
600 u16 FeAgRegAgModeLop;
601 u16 FeAgRegEgcSetLvl;
602 u16 slope, offset;
603
604 /* == Mode == */
605
606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
607 if (status < 0)
608 break;
609 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
610 FeAgRegAgModeLop |=
611 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
613 if (status < 0)
614 break;
615
616 /* == Settle level == */
617
618 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
619 FE_AG_REG_EGC_SET_LVL__M);
620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
621 if (status < 0)
622 break;
623
624 /* == Min/Max == */
625
626 slope = (u16) ((cfg->maxOutputLevel -
627 cfg->minOutputLevel) / 2);
628 offset = (u16) ((cfg->maxOutputLevel +
629 cfg->minOutputLevel) / 2 - 511);
630
631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
632 if (status < 0)
633 break;
634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
635 if (status < 0)
636 break;
637
638 /* == Speed == */
639 {
640 const u16 maxRur = 8;
641 static const u16 slowIncrDecLUT[] = {
642 3, 4, 4, 5, 6 };
643 static const u16 fastIncrDecLUT[] = {
644 14, 15, 15, 16,
645 17, 18, 18, 19,
646 20, 21, 22, 23,
647 24, 26, 27, 28,
648 29, 31
649 };
650
651 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
652 (maxRur + 1);
653 u16 fineSpeed = (u16) (cfg->speed -
654 ((cfg->speed /
655 fineSteps) *
656 fineSteps));
657 u16 invRurCount = (u16) (cfg->speed /
658 fineSteps);
659 u16 rurCount;
660 if (invRurCount > maxRur) {
661 rurCount = 0;
662 fineSpeed += fineSteps;
663 } else {
664 rurCount = maxRur - invRurCount;
665 }
666
667 /*
668 fastInc = default *
669 (2^(fineSpeed/fineSteps))
670 => range[default...2*default>
671 slowInc = default *
672 (2^(fineSpeed/fineSteps))
673 */
674 {
675 u16 fastIncrDec =
676 fastIncrDecLUT[fineSpeed /
677 ((fineSteps /
678 (14 + 1)) + 1)];
679 u16 slowIncrDec =
680 slowIncrDecLUT[fineSpeed /
681 (fineSteps /
682 (3 + 1))];
683
684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
685 if (status < 0)
686 break;
687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
688 if (status < 0)
689 break;
690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
691 if (status < 0)
692 break;
693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
694 if (status < 0)
695 break;
696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
697 if (status < 0)
698 break;
699 }
700 }
701 } while (0);
702
703 } else {
704 /* No OFF mode for IF control */
705 return -1;
706 }
707 return status;
708 }
709
710 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
711 {
712 int status = 0;
713
714 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
715 return -1;
716
717 if (cfg->ctrlMode == AGC_CTRL_USER) {
718 do {
719 u16 AgModeLop = 0;
720 u16 level = (cfg->outputLevel);
721
722 if (level == DRXD_FE_CTRL_MAX)
723 level++;
724
725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
726 if (status < 0)
727 break;
728
729 /*==== Mode ====*/
730
731 /* Powerdown PD2, WRI source */
732 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
733 state->m_FeAgRegAgPwd |=
734 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
736 if (status < 0)
737 break;
738
739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
740 if (status < 0)
741 break;
742 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
743 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
744 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
745 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
747 if (status < 0)
748 break;
749
750 /* enable AGC2 pin */
751 {
752 u16 FeAgRegAgAgcSio = 0;
753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
754 if (status < 0)
755 break;
756 FeAgRegAgAgcSio &=
757 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
758 FeAgRegAgAgcSio |=
759 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
761 if (status < 0)
762 break;
763 }
764
765 } while (0);
766 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
767 u16 AgModeLop = 0;
768
769 do {
770 u16 level;
771 /* Automatic control */
772 /* Powerup PD2, AGC2 as output, TGC source */
773 (state->m_FeAgRegAgPwd) &=
774 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
775 (state->m_FeAgRegAgPwd) |=
776 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
778 if (status < 0)
779 break;
780
781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
782 if (status < 0)
783 break;
784 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
785 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
786 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
787 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
789 if (status < 0)
790 break;
791 /* Settle level */
792 level = (((cfg->settleLevel) >> 4) &
793 FE_AG_REG_TGC_SET_LVL__M);
794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
795 if (status < 0)
796 break;
797
798 /* Min/max: don't care */
799
800 /* Speed: TODO */
801
802 /* enable AGC2 pin */
803 {
804 u16 FeAgRegAgAgcSio = 0;
805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
806 if (status < 0)
807 break;
808 FeAgRegAgAgcSio &=
809 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
810 FeAgRegAgAgcSio |=
811 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
813 if (status < 0)
814 break;
815 }
816
817 } while (0);
818 } else {
819 u16 AgModeLop = 0;
820
821 do {
822 /* No RF AGC control */
823 /* Powerdown PD2, AGC2 as output, WRI source */
824 (state->m_FeAgRegAgPwd) &=
825 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
826 (state->m_FeAgRegAgPwd) |=
827 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
829 if (status < 0)
830 break;
831
832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
833 if (status < 0)
834 break;
835 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
836 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
837 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
838 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
840 if (status < 0)
841 break;
842
843 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
844 {
845 u16 FeAgRegAgAgcSio = 0;
846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
847 if (status < 0)
848 break;
849 FeAgRegAgAgcSio &=
850 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
851 FeAgRegAgAgcSio |=
852 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
854 if (status < 0)
855 break;
856 }
857 } while (0);
858 }
859 return status;
860 }
861
862 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
863 {
864 int status = 0;
865
866 *pValue = 0;
867 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
868 u16 Value;
869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
870 Value &= FE_AG_REG_GC1_AGC_DAT__M;
871 if (status >= 0) {
872 /* 3.3V
873 |
874 R1
875 |
876 Vin - R3 - * -- Vout
877 |
878 R2
879 |
880 GND
881 */
882 u32 R1 = state->if_agc_cfg.R1;
883 u32 R2 = state->if_agc_cfg.R2;
884 u32 R3 = state->if_agc_cfg.R3;
885
886 u32 Vmax, Rpar, Vmin, Vout;
887
888 if (R2 == 0 && (R1 == 0 || R3 == 0))
889 return 0;
890
891 Vmax = (3300 * R2) / (R1 + R2);
892 Rpar = (R2 * R3) / (R3 + R2);
893 Vmin = (3300 * Rpar) / (R1 + Rpar);
894 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
895
896 *pValue = Vout;
897 }
898 }
899 return status;
900 }
901
902 static int load_firmware(struct drxd_state *state, const char *fw_name)
903 {
904 const struct firmware *fw;
905
906 if (request_firmware(&fw, fw_name, state->dev) < 0) {
907 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
908 return -EIO;
909 }
910
911 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
912 if (!state->microcode) {
913 release_firmware(fw);
914 return -ENOMEM;
915 }
916
917 state->microcode_length = fw->size;
918 release_firmware(fw);
919 return 0;
920 }
921
922 static int DownloadMicrocode(struct drxd_state *state,
923 const u8 *pMCImage, u32 Length)
924 {
925 u8 *pSrc;
926 u32 Address;
927 u16 nBlocks;
928 u16 BlockSize;
929 u32 offset = 0;
930 int i, status = 0;
931
932 pSrc = (u8 *) pMCImage;
933 /* We're not using Flags */
934 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
935 pSrc += sizeof(u16);
936 offset += sizeof(u16);
937 nBlocks = (pSrc[0] << 8) | pSrc[1];
938 pSrc += sizeof(u16);
939 offset += sizeof(u16);
940
941 for (i = 0; i < nBlocks; i++) {
942 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
943 (pSrc[2] << 8) | pSrc[3];
944 pSrc += sizeof(u32);
945 offset += sizeof(u32);
946
947 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
948 pSrc += sizeof(u16);
949 offset += sizeof(u16);
950
951 /* We're not using Flags */
952 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
953 pSrc += sizeof(u16);
954 offset += sizeof(u16);
955
956 /* We're not using BlockCRC */
957 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
958 pSrc += sizeof(u16);
959 offset += sizeof(u16);
960
961 status = WriteBlock(state, Address, BlockSize,
962 pSrc, DRX_I2C_CLEARCRC);
963 if (status < 0)
964 break;
965 pSrc += BlockSize;
966 offset += BlockSize;
967 }
968
969 return status;
970 }
971
972 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
973 {
974 u32 nrRetries = 0;
975 int status;
976
977 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
978 if (status < 0)
979 return status;
980
981 do {
982 nrRetries += 1;
983 if (nrRetries > DRXD_MAX_RETRIES) {
984 status = -1;
985 break;
986 }
987 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
988 } while (status != 0);
989
990 if (status >= 0)
991 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
992 return status;
993 }
994
995 static int HI_CfgCommand(struct drxd_state *state)
996 {
997 int status = 0;
998
999 mutex_lock(&state->mutex);
1000 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1001 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1002 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1003 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1004 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1005
1006 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1007
1008 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1009 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1010 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1011 HI_RA_RAM_SRV_CMD_CONFIG, 0);
1012 else
1013 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
1014 mutex_unlock(&state->mutex);
1015 return status;
1016 }
1017
1018 static int InitHI(struct drxd_state *state)
1019 {
1020 state->hi_cfg_wakeup_key = (state->chip_adr);
1021 /* port/bridge/power down ctrl */
1022 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1023 return HI_CfgCommand(state);
1024 }
1025
1026 static int HI_ResetCommand(struct drxd_state *state)
1027 {
1028 int status;
1029
1030 mutex_lock(&state->mutex);
1031 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1032 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1033 if (status == 0)
1034 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1035 mutex_unlock(&state->mutex);
1036 msleep(1);
1037 return status;
1038 }
1039
1040 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1041 {
1042 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1043 if (bEnableBridge)
1044 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1045 else
1046 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1047
1048 return HI_CfgCommand(state);
1049 }
1050
1051 #define HI_TR_WRITE 0x9
1052 #define HI_TR_READ 0xA
1053 #define HI_TR_READ_WRITE 0xB
1054 #define HI_TR_BROADCAST 0x4
1055
1056 #if 0
1057 static int AtomicReadBlock(struct drxd_state *state,
1058 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1059 {
1060 int status;
1061 int i = 0;
1062
1063 /* Parameter check */
1064 if ((!pData) || ((DataSize & 1) != 0))
1065 return -1;
1066
1067 mutex_lock(&state->mutex);
1068
1069 do {
1070 /* Instruct HI to read n bytes */
1071 /* TODO use proper names forthese egisters */
1072 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1073 if (status < 0)
1074 break;
1075 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1076 if (status < 0)
1077 break;
1078 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1079 if (status < 0)
1080 break;
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1082 if (status < 0)
1083 break;
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1085 if (status < 0)
1086 break;
1087
1088 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1089 if (status < 0)
1090 break;
1091
1092 } while (0);
1093
1094 if (status >= 0) {
1095 for (i = 0; i < (DataSize / 2); i += 1) {
1096 u16 word;
1097
1098 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1099 &word, 0);
1100 if (status < 0)
1101 break;
1102 pData[2 * i] = (u8) (word & 0xFF);
1103 pData[(2 * i) + 1] = (u8) (word >> 8);
1104 }
1105 }
1106 mutex_unlock(&state->mutex);
1107 return status;
1108 }
1109
1110 static int AtomicReadReg32(struct drxd_state *state,
1111 u32 Addr, u32 *pData, u8 Flags)
1112 {
1113 u8 buf[sizeof(u32)];
1114 int status;
1115
1116 if (!pData)
1117 return -1;
1118 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1119 *pData = (((u32) buf[0]) << 0) +
1120 (((u32) buf[1]) << 8) +
1121 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1122 return status;
1123 }
1124 #endif
1125
1126 static int StopAllProcessors(struct drxd_state *state)
1127 {
1128 return Write16(state, HI_COMM_EXEC__A,
1129 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1130 }
1131
1132 static int EnableAndResetMB(struct drxd_state *state)
1133 {
1134 if (state->type_A) {
1135 /* disable? monitor bus observe @ EC_OC */
1136 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1137 }
1138
1139 /* do inverse broadcast, followed by explicit write to HI */
1140 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1141 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1142 return 0;
1143 }
1144
1145 static int InitCC(struct drxd_state *state)
1146 {
1147 if (state->osc_clock_freq == 0 ||
1148 state->osc_clock_freq > 20000 ||
1149 (state->osc_clock_freq % 4000) != 0) {
1150 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1151 return -1;
1152 }
1153
1154 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1155 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1156 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1157 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1158 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1159 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1160
1161 return 0;
1162 }
1163
1164 static int ResetECOD(struct drxd_state *state)
1165 {
1166 int status = 0;
1167
1168 if (state->type_A)
1169 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1170 else
1171 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1172
1173 if (!(status < 0))
1174 status = WriteTable(state, state->m_ResetECRAM);
1175 if (!(status < 0))
1176 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1177 return status;
1178 }
1179
1180 /* Configure PGA switch */
1181
1182 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1183 {
1184 int status;
1185 u16 AgModeLop = 0;
1186 u16 AgModeHip = 0;
1187 do {
1188 if (pgaSwitch) {
1189 /* PGA on */
1190 /* fine gain */
1191 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1192 if (status < 0)
1193 break;
1194 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1195 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1196 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1197 if (status < 0)
1198 break;
1199
1200 /* coarse gain */
1201 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1202 if (status < 0)
1203 break;
1204 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1205 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1206 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1207 if (status < 0)
1208 break;
1209
1210 /* enable fine and coarse gain, enable AAF,
1211 no ext resistor */
1212 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1213 if (status < 0)
1214 break;
1215 } else {
1216 /* PGA off, bypass */
1217
1218 /* fine gain */
1219 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1220 if (status < 0)
1221 break;
1222 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1223 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1224 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1225 if (status < 0)
1226 break;
1227
1228 /* coarse gain */
1229 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1230 if (status < 0)
1231 break;
1232 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1233 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1234 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1235 if (status < 0)
1236 break;
1237
1238 /* disable fine and coarse gain, enable AAF,
1239 no ext resistor */
1240 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1241 if (status < 0)
1242 break;
1243 }
1244 } while (0);
1245 return status;
1246 }
1247
1248 static int InitFE(struct drxd_state *state)
1249 {
1250 int status;
1251
1252 do {
1253 status = WriteTable(state, state->m_InitFE_1);
1254 if (status < 0)
1255 break;
1256
1257 if (state->type_A) {
1258 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1259 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1260 0);
1261 } else {
1262 if (state->PGA)
1263 status = SetCfgPga(state, 0);
1264 else
1265 status =
1266 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1267 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1268 0);
1269 }
1270
1271 if (status < 0)
1272 break;
1273 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1274 if (status < 0)
1275 break;
1276 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1277 if (status < 0)
1278 break;
1279
1280 status = WriteTable(state, state->m_InitFE_2);
1281 if (status < 0)
1282 break;
1283
1284 } while (0);
1285
1286 return status;
1287 }
1288
1289 static int InitFT(struct drxd_state *state)
1290 {
1291 /*
1292 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1293 SC stuff
1294 */
1295 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1296 }
1297
1298 static int SC_WaitForReady(struct drxd_state *state)
1299 {
1300 int i;
1301
1302 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1303 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1304 if (status == 0)
1305 return status;
1306 }
1307 return -1;
1308 }
1309
1310 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1311 {
1312 int status = 0, ret;
1313 u16 errCode;
1314
1315 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1316 SC_WaitForReady(state);
1317
1318 ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1319
1320 if (ret < 0 || errCode == 0xFFFF) {
1321 printk(KERN_ERR "Command Error\n");
1322 status = -1;
1323 }
1324
1325 return status;
1326 }
1327
1328 static int SC_ProcStartCommand(struct drxd_state *state,
1329 u16 subCmd, u16 param0, u16 param1)
1330 {
1331 int ret, status = 0;
1332 u16 scExec;
1333
1334 mutex_lock(&state->mutex);
1335 do {
1336 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1337 if (ret < 0 || scExec != 1) {
1338 status = -1;
1339 break;
1340 }
1341 SC_WaitForReady(state);
1342 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1343 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1344 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1345
1346 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1347 } while (0);
1348 mutex_unlock(&state->mutex);
1349 return status;
1350 }
1351
1352 static int SC_SetPrefParamCommand(struct drxd_state *state,
1353 u16 subCmd, u16 param0, u16 param1)
1354 {
1355 int status;
1356
1357 mutex_lock(&state->mutex);
1358 do {
1359 status = SC_WaitForReady(state);
1360 if (status < 0)
1361 break;
1362 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1363 if (status < 0)
1364 break;
1365 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1366 if (status < 0)
1367 break;
1368 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1369 if (status < 0)
1370 break;
1371
1372 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1373 if (status < 0)
1374 break;
1375 } while (0);
1376 mutex_unlock(&state->mutex);
1377 return status;
1378 }
1379
1380 #if 0
1381 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1382 {
1383 int status = 0;
1384
1385 mutex_lock(&state->mutex);
1386 do {
1387 status = SC_WaitForReady(state);
1388 if (status < 0)
1389 break;
1390 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1391 if (status < 0)
1392 break;
1393 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1394 if (status < 0)
1395 break;
1396 } while (0);
1397 mutex_unlock(&state->mutex);
1398 return status;
1399 }
1400 #endif
1401
1402 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1403 {
1404 int status;
1405
1406 do {
1407 u16 EcOcRegIprInvMpg = 0;
1408 u16 EcOcRegOcModeLop = 0;
1409 u16 EcOcRegOcModeHip = 0;
1410 u16 EcOcRegOcMpgSio = 0;
1411
1412 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1413
1414 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1415 if (bEnableOutput) {
1416 EcOcRegOcModeHip |=
1417 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1418 } else
1419 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1420 EcOcRegOcModeLop |=
1421 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1422 } else {
1423 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1424
1425 if (bEnableOutput)
1426 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1427 else
1428 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1429
1430 /* Don't Insert RS Byte */
1431 if (state->insert_rs_byte) {
1432 EcOcRegOcModeLop &=
1433 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1434 EcOcRegOcModeHip &=
1435 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1436 EcOcRegOcModeHip |=
1437 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1438 } else {
1439 EcOcRegOcModeLop |=
1440 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1441 EcOcRegOcModeHip &=
1442 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1443 EcOcRegOcModeHip |=
1444 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1445 }
1446
1447 /* Mode = Parallel */
1448 if (state->enable_parallel)
1449 EcOcRegOcModeLop &=
1450 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1451 else
1452 EcOcRegOcModeLop |=
1453 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1454 }
1455 /* Invert Data */
1456 /* EcOcRegIprInvMpg |= 0x00FF; */
1457 EcOcRegIprInvMpg &= (~(0x00FF));
1458
1459 /* Invert Error ( we don't use the pin ) */
1460 /* EcOcRegIprInvMpg |= 0x0100; */
1461 EcOcRegIprInvMpg &= (~(0x0100));
1462
1463 /* Invert Start ( we don't use the pin ) */
1464 /* EcOcRegIprInvMpg |= 0x0200; */
1465 EcOcRegIprInvMpg &= (~(0x0200));
1466
1467 /* Invert Valid ( we don't use the pin ) */
1468 /* EcOcRegIprInvMpg |= 0x0400; */
1469 EcOcRegIprInvMpg &= (~(0x0400));
1470
1471 /* Invert Clock */
1472 /* EcOcRegIprInvMpg |= 0x0800; */
1473 EcOcRegIprInvMpg &= (~(0x0800));
1474
1475 /* EcOcRegOcModeLop =0x05; */
1476 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1477 if (status < 0)
1478 break;
1479 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1480 if (status < 0)
1481 break;
1482 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1483 if (status < 0)
1484 break;
1485 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1486 if (status < 0)
1487 break;
1488 } while (0);
1489 return status;
1490 }
1491
1492 static int SetDeviceTypeId(struct drxd_state *state)
1493 {
1494 int status = 0;
1495 u16 deviceId = 0;
1496
1497 do {
1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1499 if (status < 0)
1500 break;
1501 /* TODO: why twice? */
1502 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1503 if (status < 0)
1504 break;
1505 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1506
1507 state->type_A = 0;
1508 state->PGA = 0;
1509 state->diversity = 0;
1510 if (deviceId == 0) { /* on A2 only 3975 available */
1511 state->type_A = 1;
1512 printk(KERN_INFO "DRX3975D-A2\n");
1513 } else {
1514 deviceId >>= 12;
1515 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1516 switch (deviceId) {
1517 case 4:
1518 state->diversity = 1;
1519 /* fall through */
1520 case 3:
1521 case 7:
1522 state->PGA = 1;
1523 break;
1524 case 6:
1525 state->diversity = 1;
1526 /* fall through */
1527 case 5:
1528 case 8:
1529 break;
1530 default:
1531 status = -1;
1532 break;
1533 }
1534 }
1535 } while (0);
1536
1537 if (status < 0)
1538 return status;
1539
1540 /* Init Table selection */
1541 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1542 state->m_InitSC = DRXD_InitSC;
1543 state->m_ResetECRAM = DRXD_ResetECRAM;
1544 if (state->type_A) {
1545 state->m_ResetCEFR = DRXD_ResetCEFR;
1546 state->m_InitFE_1 = DRXD_InitFEA2_1;
1547 state->m_InitFE_2 = DRXD_InitFEA2_2;
1548 state->m_InitCP = DRXD_InitCPA2;
1549 state->m_InitCE = DRXD_InitCEA2;
1550 state->m_InitEQ = DRXD_InitEQA2;
1551 state->m_InitEC = DRXD_InitECA2;
1552 if (load_firmware(state, DRX_FW_FILENAME_A2))
1553 return -EIO;
1554 } else {
1555 state->m_ResetCEFR = NULL;
1556 state->m_InitFE_1 = DRXD_InitFEB1_1;
1557 state->m_InitFE_2 = DRXD_InitFEB1_2;
1558 state->m_InitCP = DRXD_InitCPB1;
1559 state->m_InitCE = DRXD_InitCEB1;
1560 state->m_InitEQ = DRXD_InitEQB1;
1561 state->m_InitEC = DRXD_InitECB1;
1562 if (load_firmware(state, DRX_FW_FILENAME_B1))
1563 return -EIO;
1564 }
1565 if (state->diversity) {
1566 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1567 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1568 state->m_DisableDiversity = DRXD_DisableDiversity;
1569 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1570 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1571 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1572 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1573 } else {
1574 state->m_InitDiversityFront = NULL;
1575 state->m_InitDiversityEnd = NULL;
1576 state->m_DisableDiversity = NULL;
1577 state->m_StartDiversityFront = NULL;
1578 state->m_StartDiversityEnd = NULL;
1579 state->m_DiversityDelay8MHZ = NULL;
1580 state->m_DiversityDelay6MHZ = NULL;
1581 }
1582
1583 return status;
1584 }
1585
1586 static int CorrectSysClockDeviation(struct drxd_state *state)
1587 {
1588 int status;
1589 s32 incr = 0;
1590 s32 nomincr = 0;
1591 u32 bandwidth = 0;
1592 u32 sysClockInHz = 0;
1593 u32 sysClockFreq = 0; /* in kHz */
1594 s16 oscClockDeviation;
1595 s16 Diff;
1596
1597 do {
1598 /* Retrieve bandwidth and incr, sanity check */
1599
1600 /* These accesses should be AtomicReadReg32, but that
1601 causes trouble (at least for diversity */
1602 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1603 if (status < 0)
1604 break;
1605 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1606 if (status < 0)
1607 break;
1608
1609 if (state->type_A) {
1610 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1611 break;
1612 } else {
1613 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1614 break;
1615 }
1616
1617 switch (state->props.bandwidth_hz) {
1618 case 8000000:
1619 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1620 break;
1621 case 7000000:
1622 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1623 break;
1624 case 6000000:
1625 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1626 break;
1627 default:
1628 return -1;
1629 break;
1630 }
1631
1632 /* Compute new sysclock value
1633 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1634 incr += (1 << 23);
1635 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1636 sysClockFreq = (u32) (sysClockInHz / 1000);
1637 /* rounding */
1638 if ((sysClockInHz % 1000) > 500)
1639 sysClockFreq++;
1640
1641 /* Compute clock deviation in ppm */
1642 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1643 (s32)
1644 (state->expected_sys_clock_freq)) *
1645 1000000L) /
1646 (s32)
1647 (state->expected_sys_clock_freq));
1648
1649 Diff = oscClockDeviation - state->osc_clock_deviation;
1650 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1651 if (Diff >= -200 && Diff <= 200) {
1652 state->sys_clock_freq = (u16) sysClockFreq;
1653 if (oscClockDeviation != state->osc_clock_deviation) {
1654 if (state->config.osc_deviation) {
1655 state->config.osc_deviation(state->priv,
1656 oscClockDeviation,
1657 1);
1658 state->osc_clock_deviation =
1659 oscClockDeviation;
1660 }
1661 }
1662 /* switch OFF SRMM scan in SC */
1663 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1664 if (status < 0)
1665 break;
1666 /* overrule FE_IF internal value for
1667 proper re-locking */
1668 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1669 if (status < 0)
1670 break;
1671 state->cscd_state = CSCD_SAVED;
1672 }
1673 } while (0);
1674
1675 return status;
1676 }
1677
1678 static int DRX_Stop(struct drxd_state *state)
1679 {
1680 int status;
1681
1682 if (state->drxd_state != DRXD_STARTED)
1683 return 0;
1684
1685 do {
1686 if (state->cscd_state != CSCD_SAVED) {
1687 u32 lock;
1688 status = DRX_GetLockStatus(state, &lock);
1689 if (status < 0)
1690 break;
1691 }
1692
1693 status = StopOC(state);
1694 if (status < 0)
1695 break;
1696
1697 state->drxd_state = DRXD_STOPPED;
1698
1699 status = ConfigureMPEGOutput(state, 0);
1700 if (status < 0)
1701 break;
1702
1703 if (state->type_A) {
1704 /* Stop relevant processors off the device */
1705 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1706 if (status < 0)
1707 break;
1708
1709 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1710 if (status < 0)
1711 break;
1712 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1713 if (status < 0)
1714 break;
1715 } else {
1716 /* Stop all processors except HI & CC & FE */
1717 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1718 if (status < 0)
1719 break;
1720 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721 if (status < 0)
1722 break;
1723 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1724 if (status < 0)
1725 break;
1726 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1727 if (status < 0)
1728 break;
1729 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1730 if (status < 0)
1731 break;
1732 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1733 if (status < 0)
1734 break;
1735 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1736 if (status < 0)
1737 break;
1738 }
1739
1740 } while (0);
1741 return status;
1742 }
1743
1744 #if 0 /* Currently unused */
1745 static int SetOperationMode(struct drxd_state *state, int oMode)
1746 {
1747 int status;
1748
1749 do {
1750 if (state->drxd_state != DRXD_STOPPED) {
1751 status = -1;
1752 break;
1753 }
1754
1755 if (oMode == state->operation_mode) {
1756 status = 0;
1757 break;
1758 }
1759
1760 if (oMode != OM_Default && !state->diversity) {
1761 status = -1;
1762 break;
1763 }
1764
1765 switch (oMode) {
1766 case OM_DVBT_Diversity_Front:
1767 status = WriteTable(state, state->m_InitDiversityFront);
1768 break;
1769 case OM_DVBT_Diversity_End:
1770 status = WriteTable(state, state->m_InitDiversityEnd);
1771 break;
1772 case OM_Default:
1773 /* We need to check how to
1774 get DRXD out of diversity */
1775 default:
1776 status = WriteTable(state, state->m_DisableDiversity);
1777 break;
1778 }
1779 } while (0);
1780
1781 if (!status)
1782 state->operation_mode = oMode;
1783 return status;
1784 }
1785 #endif
1786
1787 static int StartDiversity(struct drxd_state *state)
1788 {
1789 int status = 0;
1790 u16 rcControl;
1791
1792 do {
1793 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1794 status = WriteTable(state, state->m_StartDiversityFront);
1795 if (status < 0)
1796 break;
1797 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1798 status = WriteTable(state, state->m_StartDiversityEnd);
1799 if (status < 0)
1800 break;
1801 if (state->props.bandwidth_hz == 8000000) {
1802 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1803 if (status < 0)
1804 break;
1805 } else {
1806 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1807 if (status < 0)
1808 break;
1809 }
1810
1811 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1812 if (status < 0)
1813 break;
1814 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1815 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1816 /* combining enabled */
1817 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1818 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1819 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1820 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1821 if (status < 0)
1822 break;
1823 }
1824 } while (0);
1825 return status;
1826 }
1827
1828 static int SetFrequencyShift(struct drxd_state *state,
1829 u32 offsetFreq, int channelMirrored)
1830 {
1831 int negativeShift = (state->tuner_mirrors == channelMirrored);
1832
1833 /* Handle all mirroring
1834 *
1835 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1836 * feFsRegAddInc to 28 bits below
1837 * (if the result before masking is more than 28 bits, this means
1838 * that the ADC is mirroring.
1839 * The masking is in fact the aliasing of the ADC)
1840 *
1841 */
1842
1843 /* Compute register value, unsigned computation */
1844 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1845 offsetFreq,
1846 1 << 28, state->sys_clock_freq);
1847 /* Remove integer part */
1848 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1849 if (negativeShift)
1850 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1851
1852 /* Save the frequency shift without tunerOffset compensation
1853 for CtrlGetChannel. */
1854 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1855 1 << 28, state->sys_clock_freq);
1856 /* Remove integer part */
1857 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1858 if (negativeShift)
1859 state->org_fe_fs_add_incr = ((1L << 28) -
1860 state->org_fe_fs_add_incr);
1861
1862 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1863 state->fe_fs_add_incr, 0);
1864 }
1865
1866 static int SetCfgNoiseCalibration(struct drxd_state *state,
1867 struct SNoiseCal *noiseCal)
1868 {
1869 u16 beOptEna;
1870 int status = 0;
1871
1872 do {
1873 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1874 if (status < 0)
1875 break;
1876 if (noiseCal->cpOpt) {
1877 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1878 } else {
1879 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1880 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1881 if (status < 0)
1882 break;
1883 }
1884 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1885 if (status < 0)
1886 break;
1887
1888 if (!state->type_A) {
1889 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1890 if (status < 0)
1891 break;
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1893 if (status < 0)
1894 break;
1895 }
1896 } while (0);
1897
1898 return status;
1899 }
1900
1901 static int DRX_Start(struct drxd_state *state, s32 off)
1902 {
1903 struct dtv_frontend_properties *p = &state->props;
1904 int status;
1905
1906 u16 transmissionParams = 0;
1907 u16 operationMode = 0;
1908 u16 qpskTdTpsPwr = 0;
1909 u16 qam16TdTpsPwr = 0;
1910 u16 qam64TdTpsPwr = 0;
1911 u32 feIfIncr = 0;
1912 u32 bandwidth = 0;
1913 int mirrorFreqSpect;
1914
1915 u16 qpskSnCeGain = 0;
1916 u16 qam16SnCeGain = 0;
1917 u16 qam64SnCeGain = 0;
1918 u16 qpskIsGainMan = 0;
1919 u16 qam16IsGainMan = 0;
1920 u16 qam64IsGainMan = 0;
1921 u16 qpskIsGainExp = 0;
1922 u16 qam16IsGainExp = 0;
1923 u16 qam64IsGainExp = 0;
1924 u16 bandwidthParam = 0;
1925
1926 if (off < 0)
1927 off = (off - 500) / 1000;
1928 else
1929 off = (off + 500) / 1000;
1930
1931 do {
1932 if (state->drxd_state != DRXD_STOPPED)
1933 return -1;
1934 status = ResetECOD(state);
1935 if (status < 0)
1936 break;
1937 if (state->type_A) {
1938 status = InitSC(state);
1939 if (status < 0)
1940 break;
1941 } else {
1942 status = InitFT(state);
1943 if (status < 0)
1944 break;
1945 status = InitCP(state);
1946 if (status < 0)
1947 break;
1948 status = InitCE(state);
1949 if (status < 0)
1950 break;
1951 status = InitEQ(state);
1952 if (status < 0)
1953 break;
1954 status = InitSC(state);
1955 if (status < 0)
1956 break;
1957 }
1958
1959 /* Restore current IF & RF AGC settings */
1960
1961 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1962 if (status < 0)
1963 break;
1964 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1965 if (status < 0)
1966 break;
1967
1968 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1969
1970 switch (p->transmission_mode) {
1971 default: /* Not set, detect it automatically */
1972 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1973 /* fall through - try first guess DRX_FFTMODE_8K */
1974 case TRANSMISSION_MODE_8K:
1975 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1976 if (state->type_A) {
1977 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1978 if (status < 0)
1979 break;
1980 qpskSnCeGain = 99;
1981 qam16SnCeGain = 83;
1982 qam64SnCeGain = 67;
1983 }
1984 break;
1985 case TRANSMISSION_MODE_2K:
1986 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1987 if (state->type_A) {
1988 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1989 if (status < 0)
1990 break;
1991 qpskSnCeGain = 97;
1992 qam16SnCeGain = 71;
1993 qam64SnCeGain = 65;
1994 }
1995 break;
1996 }
1997
1998 switch (p->guard_interval) {
1999 case GUARD_INTERVAL_1_4:
2000 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2001 break;
2002 case GUARD_INTERVAL_1_8:
2003 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2004 break;
2005 case GUARD_INTERVAL_1_16:
2006 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2007 break;
2008 case GUARD_INTERVAL_1_32:
2009 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2010 break;
2011 default: /* Not set, detect it automatically */
2012 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2013 /* try first guess 1/4 */
2014 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2015 break;
2016 }
2017
2018 switch (p->hierarchy) {
2019 case HIERARCHY_1:
2020 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2021 if (state->type_A) {
2022 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2023 if (status < 0)
2024 break;
2025 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2026 if (status < 0)
2027 break;
2028
2029 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2030 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2031 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2032
2033 qpskIsGainMan =
2034 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2035 qam16IsGainMan =
2036 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2037 qam64IsGainMan =
2038 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2039
2040 qpskIsGainExp =
2041 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2042 qam16IsGainExp =
2043 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2044 qam64IsGainExp =
2045 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2046 }
2047 break;
2048
2049 case HIERARCHY_2:
2050 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2051 if (state->type_A) {
2052 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2053 if (status < 0)
2054 break;
2055 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2056 if (status < 0)
2057 break;
2058
2059 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2060 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2061 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2062
2063 qpskIsGainMan =
2064 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2065 qam16IsGainMan =
2066 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2067 qam64IsGainMan =
2068 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2069
2070 qpskIsGainExp =
2071 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2072 qam16IsGainExp =
2073 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2074 qam64IsGainExp =
2075 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2076 }
2077 break;
2078 case HIERARCHY_4:
2079 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2080 if (state->type_A) {
2081 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2082 if (status < 0)
2083 break;
2084 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2085 if (status < 0)
2086 break;
2087
2088 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2089 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2090 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2091
2092 qpskIsGainMan =
2093 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2094 qam16IsGainMan =
2095 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2096 qam64IsGainMan =
2097 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2098
2099 qpskIsGainExp =
2100 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2101 qam16IsGainExp =
2102 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2103 qam64IsGainExp =
2104 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2105 }
2106 break;
2107 case HIERARCHY_AUTO:
2108 default:
2109 /* Not set, detect it automatically, start with none */
2110 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2111 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2112 if (state->type_A) {
2113 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2114 if (status < 0)
2115 break;
2116 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2117 if (status < 0)
2118 break;
2119
2120 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2121 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2122 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2123
2124 qpskIsGainMan =
2125 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2126 qam16IsGainMan =
2127 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2128 qam64IsGainMan =
2129 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2130
2131 qpskIsGainExp =
2132 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2133 qam16IsGainExp =
2134 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2135 qam64IsGainExp =
2136 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2137 }
2138 break;
2139 }
2140 if (status < 0)
2141 break;
2142
2143 switch (p->modulation) {
2144 default:
2145 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2146 /* fall through - try first guess DRX_CONSTELLATION_QAM64 */
2147 case QAM_64:
2148 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2149 if (state->type_A) {
2150 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2151 if (status < 0)
2152 break;
2153 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2154 if (status < 0)
2155 break;
2156 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2157 if (status < 0)
2158 break;
2159 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2160 if (status < 0)
2161 break;
2162 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2163 if (status < 0)
2164 break;
2165
2166 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2167 if (status < 0)
2168 break;
2169 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2170 if (status < 0)
2171 break;
2172 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2173 if (status < 0)
2174 break;
2175 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2176 if (status < 0)
2177 break;
2178 }
2179 break;
2180 case QPSK:
2181 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2182 if (state->type_A) {
2183 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2184 if (status < 0)
2185 break;
2186 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2187 if (status < 0)
2188 break;
2189 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2190 if (status < 0)
2191 break;
2192 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2193 if (status < 0)
2194 break;
2195 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2196 if (status < 0)
2197 break;
2198
2199 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2200 if (status < 0)
2201 break;
2202 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2203 if (status < 0)
2204 break;
2205 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2206 if (status < 0)
2207 break;
2208 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2209 if (status < 0)
2210 break;
2211 }
2212 break;
2213
2214 case QAM_16:
2215 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2216 if (state->type_A) {
2217 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2218 if (status < 0)
2219 break;
2220 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2221 if (status < 0)
2222 break;
2223 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2224 if (status < 0)
2225 break;
2226 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2227 if (status < 0)
2228 break;
2229 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2230 if (status < 0)
2231 break;
2232
2233 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2234 if (status < 0)
2235 break;
2236 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2237 if (status < 0)
2238 break;
2239 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2240 if (status < 0)
2241 break;
2242 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2243 if (status < 0)
2244 break;
2245 }
2246 break;
2247
2248 }
2249 if (status < 0)
2250 break;
2251
2252 switch (DRX_CHANNEL_HIGH) {
2253 default:
2254 case DRX_CHANNEL_AUTO:
2255 case DRX_CHANNEL_LOW:
2256 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2257 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2258 if (status < 0)
2259 break;
2260 break;
2261 case DRX_CHANNEL_HIGH:
2262 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2264 if (status < 0)
2265 break;
2266 break;
2267
2268 }
2269
2270 switch (p->code_rate_HP) {
2271 case FEC_1_2:
2272 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2273 if (state->type_A) {
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2275 if (status < 0)
2276 break;
2277 }
2278 break;
2279 default:
2280 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2281 /* fall through */
2282 case FEC_2_3:
2283 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2284 if (state->type_A) {
2285 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2286 if (status < 0)
2287 break;
2288 }
2289 break;
2290 case FEC_3_4:
2291 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2292 if (state->type_A) {
2293 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2294 if (status < 0)
2295 break;
2296 }
2297 break;
2298 case FEC_5_6:
2299 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2300 if (state->type_A) {
2301 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2302 if (status < 0)
2303 break;
2304 }
2305 break;
2306 case FEC_7_8:
2307 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2308 if (state->type_A) {
2309 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2310 if (status < 0)
2311 break;
2312 }
2313 break;
2314 }
2315 if (status < 0)
2316 break;
2317
2318 /* First determine real bandwidth (Hz) */
2319 /* Also set delay for impulse noise cruncher (only A2) */
2320 /* Also set parameters for EC_OC fix, note
2321 EC_OC_REG_TMD_HIL_MAR is changed
2322 by SC for fix for some 8K,1/8 guard but is restored by
2323 InitEC and ResetEC
2324 functions */
2325 switch (p->bandwidth_hz) {
2326 case 0:
2327 p->bandwidth_hz = 8000000;
2328 /* fall through */
2329 case 8000000:
2330 /* (64/7)*(8/8)*1000000 */
2331 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2332
2333 bandwidthParam = 0;
2334 status = Write16(state,
2335 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2336 break;
2337 case 7000000:
2338 /* (64/7)*(7/8)*1000000 */
2339 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2340 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2341 status = Write16(state,
2342 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2343 break;
2344 case 6000000:
2345 /* (64/7)*(6/8)*1000000 */
2346 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2347 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2348 status = Write16(state,
2349 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2350 break;
2351 default:
2352 status = -EINVAL;
2353 }
2354 if (status < 0)
2355 break;
2356
2357 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2358 if (status < 0)
2359 break;
2360
2361 {
2362 u16 sc_config;
2363 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2364 if (status < 0)
2365 break;
2366
2367 /* enable SLAVE mode in 2k 1/32 to
2368 prevent timing change glitches */
2369 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2370 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2371 /* enable slave */
2372 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2373 } else {
2374 /* disable slave */
2375 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2376 }
2377 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2378 if (status < 0)
2379 break;
2380 }
2381
2382 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2383 if (status < 0)
2384 break;
2385
2386 if (state->cscd_state == CSCD_INIT) {
2387 /* switch on SRMM scan in SC */
2388 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2389 if (status < 0)
2390 break;
2391 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2392 state->cscd_state = CSCD_SET;
2393 }
2394
2395 /* Now compute FE_IF_REG_INCR */
2396 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2397 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2398 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2399 (1ULL << 21), bandwidth) - (1 << 23);
2400 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2401 if (status < 0)
2402 break;
2403 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2404 if (status < 0)
2405 break;
2406 /* Bandwidth setting done */
2407
2408 /* Mirror & frequency offset */
2409 SetFrequencyShift(state, off, mirrorFreqSpect);
2410
2411 /* Start SC, write channel settings to SC */
2412
2413 /* Enable SC after setting all other parameters */
2414 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2415 if (status < 0)
2416 break;
2417 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2418 if (status < 0)
2419 break;
2420
2421 /* Write SC parameter registers, operation mode */
2422 #if 1
2423 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2424 SC_RA_RAM_OP_AUTO_GUARD__M |
2425 SC_RA_RAM_OP_AUTO_CONST__M |
2426 SC_RA_RAM_OP_AUTO_HIER__M |
2427 SC_RA_RAM_OP_AUTO_RATE__M);
2428 #endif
2429 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2430 if (status < 0)
2431 break;
2432
2433 /* Start correct processes to get in lock */
2434 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2435 if (status < 0)
2436 break;
2437
2438 status = StartOC(state);
2439 if (status < 0)
2440 break;
2441
2442 if (state->operation_mode != OM_Default) {
2443 status = StartDiversity(state);
2444 if (status < 0)
2445 break;
2446 }
2447
2448 state->drxd_state = DRXD_STARTED;
2449 } while (0);
2450
2451 return status;
2452 }
2453
2454 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2455 {
2456 u32 ulRfAgcOutputLevel = 0xffffffff;
2457 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2458 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2459 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2460 u32 ulRfAgcSpeed = 0; /* Currently unused */
2461 u32 ulRfAgcMode = 0; /*2; Off */
2462 u32 ulRfAgcR1 = 820;
2463 u32 ulRfAgcR2 = 2200;
2464 u32 ulRfAgcR3 = 150;
2465 u32 ulIfAgcMode = 0; /* Auto */
2466 u32 ulIfAgcOutputLevel = 0xffffffff;
2467 u32 ulIfAgcSettleLevel = 0xffffffff;
2468 u32 ulIfAgcMinLevel = 0xffffffff;
2469 u32 ulIfAgcMaxLevel = 0xffffffff;
2470 u32 ulIfAgcSpeed = 0xffffffff;
2471 u32 ulIfAgcR1 = 820;
2472 u32 ulIfAgcR2 = 2200;
2473 u32 ulIfAgcR3 = 150;
2474 u32 ulClock = state->config.clock;
2475 u32 ulSerialMode = 0;
2476 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2477 u32 ulHiI2cDelay = HI_I2C_DELAY;
2478 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2479 u32 ulHiI2cPatch = 0;
2480 u32 ulEnvironment = APPENV_PORTABLE;
2481 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2482 u32 ulIFFilter = IFFILTER_SAW;
2483
2484 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2485 state->if_agc_cfg.outputLevel = 0;
2486 state->if_agc_cfg.settleLevel = 140;
2487 state->if_agc_cfg.minOutputLevel = 0;
2488 state->if_agc_cfg.maxOutputLevel = 1023;
2489 state->if_agc_cfg.speed = 904;
2490
2491 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2492 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2493 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2494 }
2495
2496 if (ulIfAgcMode == 0 &&
2497 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2498 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2499 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2500 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2501 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2502 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2503 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2504 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2505 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2506 }
2507
2508 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2509 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2510 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2511
2512 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2513 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2514 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2515
2516 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2517 /* rest of the RFAgcCfg structure currently unused */
2518 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2519 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2520 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2521 }
2522
2523 if (ulRfAgcMode == 0 &&
2524 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2525 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2526 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2527 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2528 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2529 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2530 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2531 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2532 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2533 }
2534
2535 if (ulRfAgcMode == 2)
2536 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2537
2538 if (ulEnvironment <= 2)
2539 state->app_env_default = (enum app_env)
2540 (ulEnvironment);
2541 if (ulEnvironmentDiversity <= 2)
2542 state->app_env_diversity = (enum app_env)
2543 (ulEnvironmentDiversity);
2544
2545 if (ulIFFilter == IFFILTER_DISCRETE) {
2546 /* discrete filter */
2547 state->noise_cal.cpOpt = 0;
2548 state->noise_cal.cpNexpOfs = 40;
2549 state->noise_cal.tdCal2k = -40;
2550 state->noise_cal.tdCal8k = -24;
2551 } else {
2552 /* SAW filter */
2553 state->noise_cal.cpOpt = 1;
2554 state->noise_cal.cpNexpOfs = 0;
2555 state->noise_cal.tdCal2k = -21;
2556 state->noise_cal.tdCal8k = -24;
2557 }
2558 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2559
2560 state->chip_adr = (state->config.demod_address << 1) | 1;
2561 switch (ulHiI2cPatch) {
2562 case 1:
2563 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2564 break;
2565 case 3:
2566 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2567 break;
2568 default:
2569 state->m_HiI2cPatch = NULL;
2570 }
2571
2572 /* modify tuner and clock attributes */
2573 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2574 /* expected system clock frequency in kHz */
2575 state->expected_sys_clock_freq = 48000;
2576 /* real system clock frequency in kHz */
2577 state->sys_clock_freq = 48000;
2578 state->osc_clock_freq = (u16) ulClock;
2579 state->osc_clock_deviation = 0;
2580 state->cscd_state = CSCD_INIT;
2581 state->drxd_state = DRXD_UNINITIALIZED;
2582
2583 state->PGA = 0;
2584 state->type_A = 0;
2585 state->tuner_mirrors = 0;
2586
2587 /* modify MPEG output attributes */
2588 state->insert_rs_byte = state->config.insert_rs_byte;
2589 state->enable_parallel = (ulSerialMode != 1);
2590
2591 /* Timing div, 250ns/Psys */
2592 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2593
2594 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2595 ulHiI2cDelay) / 1000;
2596 /* Bridge delay, uses oscilator clock */
2597 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2598 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2599 ulHiI2cBridgeDelay) / 1000;
2600
2601 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2602 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2603 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2604 return 0;
2605 }
2606
2607 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2608 {
2609 int status = 0;
2610 u32 driverVersion;
2611
2612 if (state->init_done)
2613 return 0;
2614
2615 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2616
2617 do {
2618 state->operation_mode = OM_Default;
2619
2620 status = SetDeviceTypeId(state);
2621 if (status < 0)
2622 break;
2623
2624 /* Apply I2c address patch to B1 */
2625 if (!state->type_A && state->m_HiI2cPatch) {
2626 status = WriteTable(state, state->m_HiI2cPatch);
2627 if (status < 0)
2628 break;
2629 }
2630
2631 if (state->type_A) {
2632 /* HI firmware patch for UIO readout,
2633 avoid clearing of result register */
2634 status = Write16(state, 0x43012D, 0x047f, 0);
2635 if (status < 0)
2636 break;
2637 }
2638
2639 status = HI_ResetCommand(state);
2640 if (status < 0)
2641 break;
2642
2643 status = StopAllProcessors(state);
2644 if (status < 0)
2645 break;
2646 status = InitCC(state);
2647 if (status < 0)
2648 break;
2649
2650 state->osc_clock_deviation = 0;
2651
2652 if (state->config.osc_deviation)
2653 state->osc_clock_deviation =
2654 state->config.osc_deviation(state->priv, 0, 0);
2655 {
2656 /* Handle clock deviation */
2657 s32 devB;
2658 s32 devA = (s32) (state->osc_clock_deviation) *
2659 (s32) (state->expected_sys_clock_freq);
2660 /* deviation in kHz */
2661 s32 deviation = (devA / (1000000L));
2662 /* rounding, signed */
2663 if (devA > 0)
2664 devB = (2);
2665 else
2666 devB = (-2);
2667 if ((devB * (devA % 1000000L) > 1000000L)) {
2668 /* add +1 or -1 */
2669 deviation += (devB / 2);
2670 }
2671
2672 state->sys_clock_freq =
2673 (u16) ((state->expected_sys_clock_freq) +
2674 deviation);
2675 }
2676 status = InitHI(state);
2677 if (status < 0)
2678 break;
2679 status = InitAtomicRead(state);
2680 if (status < 0)
2681 break;
2682
2683 status = EnableAndResetMB(state);
2684 if (status < 0)
2685 break;
2686 if (state->type_A) {
2687 status = ResetCEFR(state);
2688 if (status < 0)
2689 break;
2690 }
2691 if (fw) {
2692 status = DownloadMicrocode(state, fw, fw_size);
2693 if (status < 0)
2694 break;
2695 } else {
2696 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2697 if (status < 0)
2698 break;
2699 }
2700
2701 if (state->PGA) {
2702 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2703 SetCfgPga(state, 0); /* PGA = 0 dB */
2704 } else {
2705 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2706 }
2707
2708 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2709
2710 status = InitFE(state);
2711 if (status < 0)
2712 break;
2713 status = InitFT(state);
2714 if (status < 0)
2715 break;
2716 status = InitCP(state);
2717 if (status < 0)
2718 break;
2719 status = InitCE(state);
2720 if (status < 0)
2721 break;
2722 status = InitEQ(state);
2723 if (status < 0)
2724 break;
2725 status = InitEC(state);
2726 if (status < 0)
2727 break;
2728 status = InitSC(state);
2729 if (status < 0)
2730 break;
2731
2732 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2733 if (status < 0)
2734 break;
2735 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2736 if (status < 0)
2737 break;
2738
2739 state->cscd_state = CSCD_INIT;
2740 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2741 if (status < 0)
2742 break;
2743 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2744 if (status < 0)
2745 break;
2746
2747 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2748 (VERSION_MAJOR % 10)) << 24;
2749 driverVersion += (((VERSION_MINOR / 10) << 4) +
2750 (VERSION_MINOR % 10)) << 16;
2751 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2752 ((VERSION_PATCH / 100) << 8) +
2753 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2754
2755 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2756 if (status < 0)
2757 break;
2758
2759 status = StopOC(state);
2760 if (status < 0)
2761 break;
2762
2763 state->drxd_state = DRXD_STOPPED;
2764 state->init_done = 1;
2765 status = 0;
2766 } while (0);
2767 return status;
2768 }
2769
2770 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2771 {
2772 DRX_GetLockStatus(state, pLockStatus);
2773
2774 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2775 if (*pLockStatus & DRX_LOCK_FEC) {
2776 ConfigureMPEGOutput(state, 1);
2777 /* Get status again, in case we have MPEG lock now */
2778 /*DRX_GetLockStatus(state, pLockStatus); */
2779 }
2780
2781 return 0;
2782 }
2783
2784 /****************************************************************************/
2785 /****************************************************************************/
2786 /****************************************************************************/
2787
2788 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2789 {
2790 struct drxd_state *state = fe->demodulator_priv;
2791 u32 value;
2792 int res;
2793
2794 res = ReadIFAgc(state, &value);
2795 if (res < 0)
2796 *strength = 0;
2797 else
2798 *strength = 0xffff - (value << 4);
2799 return 0;
2800 }
2801
2802 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
2803 {
2804 struct drxd_state *state = fe->demodulator_priv;
2805 u32 lock;
2806
2807 DRXD_status(state, &lock);
2808 *status = 0;
2809 /* No MPEG lock in V255 firmware, bug ? */
2810 #if 1
2811 if (lock & DRX_LOCK_MPEG)
2812 *status |= FE_HAS_LOCK;
2813 #else
2814 if (lock & DRX_LOCK_FEC)
2815 *status |= FE_HAS_LOCK;
2816 #endif
2817 if (lock & DRX_LOCK_FEC)
2818 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2819 if (lock & DRX_LOCK_DEMOD)
2820 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2821
2822 return 0;
2823 }
2824
2825 static int drxd_init(struct dvb_frontend *fe)
2826 {
2827 struct drxd_state *state = fe->demodulator_priv;
2828
2829 return DRXD_init(state, NULL, 0);
2830 }
2831
2832 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2833 {
2834 struct drxd_state *state = fe->demodulator_priv;
2835
2836 if (state->config.disable_i2c_gate_ctrl == 1)
2837 return 0;
2838
2839 return DRX_ConfigureI2CBridge(state, onoff);
2840 }
2841
2842 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2843 struct dvb_frontend_tune_settings *sets)
2844 {
2845 sets->min_delay_ms = 10000;
2846 sets->max_drift = 0;
2847 sets->step_size = 0;
2848 return 0;
2849 }
2850
2851 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2852 {
2853 *ber = 0;
2854 return 0;
2855 }
2856
2857 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2858 {
2859 *snr = 0;
2860 return 0;
2861 }
2862
2863 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2864 {
2865 *ucblocks = 0;
2866 return 0;
2867 }
2868
2869 static int drxd_sleep(struct dvb_frontend *fe)
2870 {
2871 struct drxd_state *state = fe->demodulator_priv;
2872
2873 ConfigureMPEGOutput(state, 0);
2874 return 0;
2875 }
2876
2877 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2878 {
2879 return drxd_config_i2c(fe, enable);
2880 }
2881
2882 static int drxd_set_frontend(struct dvb_frontend *fe)
2883 {
2884 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2885 struct drxd_state *state = fe->demodulator_priv;
2886 s32 off = 0;
2887
2888 state->props = *p;
2889 DRX_Stop(state);
2890
2891 if (fe->ops.tuner_ops.set_params) {
2892 fe->ops.tuner_ops.set_params(fe);
2893 if (fe->ops.i2c_gate_ctrl)
2894 fe->ops.i2c_gate_ctrl(fe, 0);
2895 }
2896
2897 msleep(200);
2898
2899 return DRX_Start(state, off);
2900 }
2901
2902 static void drxd_release(struct dvb_frontend *fe)
2903 {
2904 struct drxd_state *state = fe->demodulator_priv;
2905
2906 kfree(state);
2907 }
2908
2909 static const struct dvb_frontend_ops drxd_ops = {
2910 .delsys = { SYS_DVBT},
2911 .info = {
2912 .name = "Micronas DRXD DVB-T",
2913 .frequency_min_hz = 47125 * kHz,
2914 .frequency_max_hz = 855250 * kHz,
2915 .frequency_stepsize_hz = 166667,
2916 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2917 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2918 FE_CAN_FEC_AUTO |
2919 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2920 FE_CAN_QAM_AUTO |
2921 FE_CAN_TRANSMISSION_MODE_AUTO |
2922 FE_CAN_GUARD_INTERVAL_AUTO |
2923 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2924
2925 .release = drxd_release,
2926 .init = drxd_init,
2927 .sleep = drxd_sleep,
2928 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2929
2930 .set_frontend = drxd_set_frontend,
2931 .get_tune_settings = drxd_get_tune_settings,
2932
2933 .read_status = drxd_read_status,
2934 .read_ber = drxd_read_ber,
2935 .read_signal_strength = drxd_read_signal_strength,
2936 .read_snr = drxd_read_snr,
2937 .read_ucblocks = drxd_read_ucblocks,
2938 };
2939
2940 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2941 void *priv, struct i2c_adapter *i2c,
2942 struct device *dev)
2943 {
2944 struct drxd_state *state = NULL;
2945
2946 state = kzalloc(sizeof(*state), GFP_KERNEL);
2947 if (!state)
2948 return NULL;
2949
2950 state->ops = drxd_ops;
2951 state->dev = dev;
2952 state->config = *config;
2953 state->i2c = i2c;
2954 state->priv = priv;
2955
2956 mutex_init(&state->mutex);
2957
2958 if (Read16(state, 0, NULL, 0) < 0)
2959 goto error;
2960
2961 state->frontend.ops = drxd_ops;
2962 state->frontend.demodulator_priv = state;
2963 ConfigureMPEGOutput(state, 0);
2964 /* add few initialization to allow gate control */
2965 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2966 InitHI(state);
2967
2968 return &state->frontend;
2969
2970 error:
2971 printk(KERN_ERR "drxd: not found\n");
2972 kfree(state);
2973 return NULL;
2974 }
2975 EXPORT_SYMBOL(drxd_attach);
2976
2977 MODULE_DESCRIPTION("DRXD driver");
2978 MODULE_AUTHOR("Micronas");
2979 MODULE_LICENSE("GPL");
Linux with added FPC-III support